diff options
Diffstat (limited to 'tests/long/00.gzip/ref')
10 files changed, 305 insertions, 305 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 9ba264ef1..34e6ec7b4 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 17:09:58 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:05:30 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 090a41f44..c6d7a6e70 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 211142 # Simulator instruction rate (inst/s) -host_mem_usage 204372 # Number of bytes of host memory used -host_seconds 2678.54 # Real time elapsed on the host -host_tick_rate 62376647 # Simulator tick rate (ticks/s) +host_inst_rate 310118 # Simulator instruction rate (inst/s) +host_mem_usage 206072 # Number of bytes of host memory used +host_seconds 1823.67 # Real time elapsed on the host +host_tick_rate 91616419 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.167078 # Number of seconds simulated @@ -19,21 +19,23 @@ system.cpu.BPredUnit.usedRAS 1692219 # Nu system.cpu.commit.COM:branches 62547159 # Number of branches committed system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 322711250 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 108088758 3349.40% - 1 100475751 3113.49% - 2 37367184 1157.91% - 3 9733028 301.60% - 4 10676883 330.85% - 5 22147835 686.31% - 6 13251874 410.64% - 7 3269687 101.32% - 8 17700250 548.49% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 322711250 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 108088758 33.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 100475751 31.13% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 37367184 11.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 9733028 3.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 10676883 3.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 22147835 6.86% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 13251874 4.11% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 3269687 1.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 17700250 5.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 322711250 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.865001 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.301723 # Number of insts commited each cycle system.cpu.commit.COM:count 601856963 # Number of instructions committed system.cpu.commit.COM:loads 115049510 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -71,13 +73,13 @@ system.cpu.dcache.WriteReq_mshr_hits 1992407 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6922.723577 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21318.181818 # average number of cycles each access was blocked system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 123 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 851495 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 234500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency @@ -96,7 +98,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 149415339 # number of overall hits system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses @@ -149,21 +151,23 @@ system.cpu.fetch.branchRate 0.227555 # Nu system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 332581112 -system.cpu.fetch.rateDist.min_value 0 - 0 201466223 6057.66% - 1 10360747 311.53% - 2 15882081 477.54% - 3 14599006 438.96% - 4 12362950 371.73% - 5 14822134 445.67% - 6 6008311 180.66% - 7 3307530 99.45% - 8 53772130 1616.81% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 332581112 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 201466223 60.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 10360747 3.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 15882081 4.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 14599006 4.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 12362950 3.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 14822134 4.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 6008311 1.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 3307530 0.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53772130 16.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 332581112 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.101334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.065263 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency @@ -175,13 +179,13 @@ system.cpu.icache.ReadReq_mshr_hits 267 # nu system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency @@ -200,7 +204,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 66013237 # number of overall hits system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses @@ -263,58 +267,54 @@ system.cpu.iew.predictedNotTakenIncorrect 540315 # N system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 605718112 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 438834840 72.45% # Type of FU issued - IntMult 6546 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 29 0.00% # Type of FU issued - FloatCmp 5 0.00% # Type of FU issued - FloatCvt 5 0.00% # Type of FU issued - FloatMult 4 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 124855453 20.61% # Type of FU issued - MemWrite 42021230 6.94% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 438834840 72.45% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 6546 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 124855453 20.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 42021230 6.94% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 605718112 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 5390831 74.54% # attempts to use FU when none available - IntMult 67 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 1490139 20.60% # attempts to use FU when none available - MemWrite 351286 4.86% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 332581112 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 92203773 27.72% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 67051353 20.16% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 80133780 24.09% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 36043478 10.84% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 30084945 9.05% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 14579095 4.38% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 10850493 3.26% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 1143008 0.34% -system.cpu.iq.ISSUE:issued_per_cycle::8 491187 0.15% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 332581112 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.821264 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.674645 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 5390831 74.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 67 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 1490139 20.60% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 351286 4.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 332581112 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 92203773 27.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 67051353 20.16% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 80133780 24.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 36043478 10.84% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 30084945 9.05% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 14579095 4.38% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 10850493 3.26% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 1143008 0.34% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 491187 0.15% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 332581112 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.821264 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.674645 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued @@ -369,13 +369,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 80643 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 334123 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 334123 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 5083.333333 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5083.333333 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 3.723010 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 78 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 396500 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 78 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 396500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency @@ -394,7 +394,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 181383 # number of overall hits system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout index 3f5339a48..6de92788c 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 17:10:28 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:05:42 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index c10711f5d..dfa3f12e0 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1860782 # Simulator instruction rate (inst/s) -host_mem_usage 203344 # Number of bytes of host memory used -host_seconds 323.44 # Real time elapsed on the host -host_tick_rate 2405379783 # Simulator tick rate (ticks/s) +host_inst_rate 2876228 # Simulator instruction rate (inst/s) +host_mem_usage 205052 # Number of bytes of host memory used +host_seconds 209.25 # Real time elapsed on the host +host_tick_rate 3718015194 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.778004 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 328891 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 153435240 # number of overall hits system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses @@ -97,13 +97,13 @@ system.cpu.icache.ReadReq_misses 795 # nu system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency @@ -122,7 +122,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 601861103 # number of overall hits system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses @@ -187,13 +187,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -212,7 +212,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 167236 # number of overall hits system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 42dccffd2..04375240b 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:17:54 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:21:10 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 7ce31fb30..a99c3f466 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 110757 # Simulator instruction rate (inst/s) -host_mem_usage 206360 # Number of bytes of host memory used -host_seconds 12690.99 # Real time elapsed on the host -host_tick_rate 86885218 # Simulator tick rate (ticks/s) +host_inst_rate 148321 # Simulator instruction rate (inst/s) +host_mem_usage 208096 # Number of bytes of host memory used +host_seconds 9476.87 # Real time elapsed on the host +host_tick_rate 116352721 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405618365 # Number of instructions simulated sim_seconds 1.102659 # Number of seconds simulated @@ -19,21 +19,23 @@ system.cpu.BPredUnit.usedRAS 0 # Nu system.cpu.commit.COM:branches 86248929 # Number of branches committed system.cpu.commit.COM:bw_lim_events 8096109 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1964055004 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1088074201 5539.94% - 1 575643784 2930.89% - 2 120435541 613.20% - 3 120975798 615.95% - 4 27955067 142.33% - 5 8084166 41.16% - 6 10447088 53.19% - 7 4343250 22.11% - 8 8096109 41.22% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 1964055004 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 1088074201 55.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 575643784 29.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 120435541 6.13% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 120975798 6.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 27955067 1.42% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 8084166 0.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 10447088 0.53% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 4343250 0.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 8096109 0.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1964055004 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.758399 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.188214 # Number of insts commited each cycle system.cpu.commit.COM:count 1489537508 # Number of instructions committed system.cpu.commit.COM:loads 402517243 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed @@ -79,13 +81,13 @@ system.cpu.dcache.WriteReq_mshr_hits 1870625 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 12696288000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1119.158447 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 30916.284897 # average overall miss latency @@ -104,7 +106,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 30916.284897 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23961.331807 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 589980331 # number of overall hits system.cpu.dcache.overall_miss_latency 97022505500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses @@ -138,21 +140,23 @@ system.cpu.fetch.branchRate 0.115384 # Nu system.cpu.fetch.icacheStallCycles 354588619 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2203814981 -system.cpu.fetch.rateDist.min_value 0 - 0 1359102894 6167.05% - 1 256500547 1163.89% - 2 81150170 368.23% - 3 38425919 174.36% - 4 85384463 387.44% - 5 41200023 186.95% - 6 32567288 147.78% - 7 20688755 93.88% - 8 288794922 1310.43% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 2203814981 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 1359102894 61.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 256500547 11.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 81150170 3.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 38425919 1.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 85384463 3.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 41200023 1.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 32567288 1.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 20688755 0.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 288794922 13.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 2203814981 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.693518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.831719 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 354588619 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency @@ -164,13 +168,13 @@ system.cpu.icache.ReadReq_mshr_hits 748 # nu system.cpu.icache.ReadReq_mshr_miss_latency 47986500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 257319.660377 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 354588619 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency @@ -189,7 +193,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 354588619 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 354586492 # number of overall hits system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses @@ -252,58 +256,54 @@ system.cpu.iew.predictedNotTakenIncorrect 1481544 # N system.cpu.iew.predictedTakenIncorrect 90333500 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 1989307661 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 1186637129 59.65% # Type of FU issued - IntMult 0 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2990803 0.15% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 571681967 28.74% # Type of FU issued - MemWrite 227997762 11.46% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1186637129 59.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2990803 0.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 571681967 28.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 227997762 11.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 1989307661 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 4014627 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 142220 3.54% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 232755 5.80% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 3328922 82.92% # attempts to use FU when none available - MemWrite 310730 7.74% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 2203814981 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 1083881876 49.18% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 586425801 26.61% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 298714420 13.55% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 164995038 7.49% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 47215803 2.14% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 14943143 0.68% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 6716019 0.30% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 790183 0.04% -system.cpu.iq.ISSUE:issued_per_cycle::8 132698 0.01% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 2203814981 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902665 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.144866 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 142220 3.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 232755 5.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 3328922 82.92% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 310730 7.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 2203814981 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 1083881876 49.18% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 586425801 26.61% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 298714420 13.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 164995038 7.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 47215803 2.14% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 14943143 0.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 6716019 0.30% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 790183 0.04% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 132698 0.01% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 2203814981 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902665 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.144866 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate system.cpu.iq.iqInstsAdded 2506731488 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 1989307661 # Number of instructions issued @@ -342,13 +342,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 348749 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 348749 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 4.234507 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34273.636870 # average overall miss latency @@ -367,7 +367,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34273.636870 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.774576 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 214678 # number of overall hits system.cpu.l2cache.overall_miss_latency 10764492500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.593992 # miss rate for overall accesses diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index 87c6b0d93..224bbd08c 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:13:21 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:25:44 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 2bdd6d4c0..72665606e 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1263053 # Simulator instruction rate (inst/s) -host_mem_usage 205412 # Number of bytes of host memory used -host_seconds 1179.30 # Real time elapsed on the host -host_tick_rate 1760361196 # Simulator tick rate (ticks/s) +host_inst_rate 2042056 # Simulator instruction rate (inst/s) +host_mem_usage 207148 # Number of bytes of host memory used +host_seconds 729.42 # Real time elapsed on the host +host_tick_rate 2846083906 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 2.076001 # Number of seconds simulated @@ -38,13 +38,13 @@ system.cpu.dcache.WriteReq_misses 319595 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 42833.478535 # average overall miss latency @@ -63,7 +63,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 42833.478535 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 568846579 # number of overall hits system.cpu.dcache.overall_miss_latency 21977044000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses @@ -91,13 +91,13 @@ system.cpu.icache.ReadReq_misses 1107 # nu system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1485113012 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency @@ -116,7 +116,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1485111905 # number of overall hits system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses @@ -165,13 +165,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 316424 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 316424 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 3.428657 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -190,7 +190,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 160849 # number of overall hits system.cpu.l2cache.overall_miss_latency 15260908000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.645963 # miss rate for overall accesses diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 852b3d501..450751534 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 19:00:07 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 19:10:33 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:55 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:33:03 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 88ced5522..7585c05e4 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1809758 # Simulator instruction rate (inst/s) -host_mem_usage 205688 # Number of bytes of host memory used -host_seconds 894.80 # Real time elapsed on the host -host_tick_rate 2028277640 # Simulator tick rate (ticks/s) +host_inst_rate 1739159 # Simulator instruction rate (inst/s) +host_mem_usage 207648 # Number of bytes of host memory used +host_seconds 931.12 # Real time elapsed on the host +host_tick_rate 1949153444 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619365954 # Number of instructions simulated sim_seconds 1.814897 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 312146 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 16543738000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001659 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 312146 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1364.014744 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 607228174 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 42400.023531 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 607228174 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 42400.023531 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 39400.023531 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 606718219 # number of overall hits system.cpu.dcache.overall_miss_latency 21622104000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000840 # miss rate for overall accesses @@ -81,13 +81,13 @@ system.cpu.icache.ReadReq_misses 722 # nu system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 1643373.934903 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1186516703 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency @@ -106,7 +106,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 1186516703 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1186515981 # number of overall hits system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses @@ -155,13 +155,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 65104 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 308934 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 308934 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 3.437895 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 445573 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -180,7 +180,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 445573 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 165128 # number of overall hits system.cpu.l2cache.overall_miss_latency 14583140000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.629403 # miss rate for overall accesses |