diff options
Diffstat (limited to 'tests/long/00.gzip')
| -rw-r--r-- | tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini | 2 | ||||
| -rwxr-xr-x | tests/long/00.gzip/ref/x86/linux/o3-timing/simout | 10 | ||||
| -rw-r--r-- | tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt | 730 |
3 files changed, 371 insertions, 371 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index 503c61f1c..9a2e60122 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -488,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index 5ac6b64fd..d3a2b5cda 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 +M5 compiled Feb 12 2011 02:22:23 +M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch +M5 started Feb 12 2011 02:22:27 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -1067,4 +1067,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 758990697000 because target called exit() +Exiting @ tick 766217705000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 7fa355b9d..cc548bebc 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 240879 # Simulator instruction rate (inst/s) -host_mem_usage 232888 # Number of bytes of host memory used -host_seconds 6731.58 # Real time elapsed on the host -host_tick_rate 112750685 # Simulator tick rate (ticks/s) +host_inst_rate 123498 # Simulator instruction rate (inst/s) +host_mem_usage 236748 # Number of bytes of host memory used +host_seconds 13129.74 # Real time elapsed on the host +host_tick_rate 58357436 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493982 # Number of instructions simulated -sim_seconds 0.758991 # Number of seconds simulated -sim_ticks 758990697000 # Number of ticks simulated +sim_seconds 0.766218 # Number of seconds simulated +sim_ticks 766217705000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 123829137 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 124444739 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 169776992 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 171183773 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 5933451 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 124445048 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 124445048 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 8003535 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 180455810 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 180455810 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 107161579 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 4428744 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 7534042 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1488500908 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.089347 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.266465 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1432274296 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.132111 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.344268 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 544771983 36.60% 36.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 603082048 40.52% 77.11% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 142955782 9.60% 86.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 121627881 8.17% 94.89% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 42142525 2.83% 97.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 19097450 1.28% 99.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 4632040 0.31% 99.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 5762455 0.39% 99.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 4428744 0.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 536173455 37.44% 37.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 547306108 38.21% 75.65% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 130197340 9.09% 84.74% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 136647601 9.54% 94.28% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 42821104 2.99% 97.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 22915800 1.60% 98.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 3037283 0.21% 99.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 5641563 0.39% 99.47% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 7534042 0.53% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1488500908 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1432274296 # Number of insts commited each cycle system.cpu.commit.COM:count 1621493982 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,422 +44,422 @@ system.cpu.commit.COM:loads 419042125 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 607228182 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5933482 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 8003567 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 174503493 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 729601482 # The number of squashed insts skipped by commit system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.936162 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.936162 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 328666076 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10263.411891 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7269.320090 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 328458033 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2135231000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000633 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 208043 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1354 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1502488500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000629 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 206689 # number of ReadReq MSHR misses +system.cpu.cpi 0.945076 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.945076 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 330979138 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10103.492713 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7153.561618 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 330761084 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2203107000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000659 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 218054 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 3264 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1536513500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000649 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 214790 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 19664.658707 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9970.057484 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 186942755 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 24449109500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.006607 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1243302 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 995928 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2466333000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001315 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 247374 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 19459.417847 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10004.386505 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 186948986 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 24072681495 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.006574 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1237071 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 986986 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2501946999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 250085 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15814.402211 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1135.086514 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 16007.596007 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1113.654359 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 29308 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 29555 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 463488500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 473104500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 516852133 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18317.037300 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8740.684663 # average overall mshr miss latency -system.cpu.dcache.demand_hits 515400788 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26584340500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002808 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1451345 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 997282 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3968821500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000879 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 454063 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 519165195 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18057.409841 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency +system.cpu.dcache.demand_hits 517710070 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 26275788495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002803 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1455125 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 990250 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4038460499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000895 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 464875 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999777 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.087002 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 516852133 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18317.037300 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8740.684663 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999796 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.162912 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 519165195 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18057.409841 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 515400788 # number of overall hits -system.cpu.dcache.overall_miss_latency 26584340500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002808 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1451345 # number of overall misses -system.cpu.dcache.overall_mshr_hits 997282 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3968821500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000879 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 454063 # number of overall MSHR misses +system.cpu.dcache.overall_hits 517710070 # number of overall hits +system.cpu.dcache.overall_miss_latency 26275788495 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002803 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1455125 # number of overall misses +system.cpu.dcache.overall_mshr_hits 990250 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4038460499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000895 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 464875 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 449967 # number of replacements -system.cpu.dcache.sampled_refs 454063 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 460779 # number of replacements +system.cpu.dcache.sampled_refs 464875 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.087002 # Cycle average of tags in use -system.cpu.dcache.total_refs 515400788 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 331273000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 403776 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 134525635 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 1844468999 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 346793246 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 965499551 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 29266045 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 41682476 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 124445048 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 129713560 # Number of cache lines fetched -system.cpu.fetch.Cycles 1050276779 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 844154 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1022007635 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 12829021 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.081981 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 129713560 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 123829137 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.673268 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1517766953 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.229744 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.282154 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4095.162912 # Cycle average of tags in use +system.cpu.dcache.total_refs 517710070 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 317835000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 411288 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 610366395 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 2477699501 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 436378814 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 330621598 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 99870091 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 54907489 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 180455810 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 168863429 # Number of cache lines fetched +system.cpu.fetch.Cycles 400342229 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 931185 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1404767222 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 14936403 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.117758 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 168863429 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 169776992 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.916689 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1532144387 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.666939 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.038798 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 499259849 32.89% 32.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 507370292 33.43% 66.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 273389808 18.01% 84.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 210662042 13.88% 98.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8152383 0.54% 98.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1243560 0.08% 98.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 720 0.00% 98.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8664 0.00% 98.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 17679635 1.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1134818986 74.07% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25831687 1.69% 75.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14383456 0.94% 76.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13631087 0.89% 77.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 30570437 2.00% 79.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 20250642 1.32% 80.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 34285955 2.24% 83.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37728615 2.46% 85.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 220643522 14.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1517766953 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 2 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 129713560 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 37165.425532 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35455.808081 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 129712620 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 34935500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 1532144387 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 12 # number of floating regfile reads +system.cpu.icache.ReadReq_accesses 168863429 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 34706.050695 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35310.841984 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 168862206 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42445500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 940 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 148 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 28081000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 792 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_misses 1223 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 356 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 30614500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 867 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 163778.560606 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 194766.096886 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 129713560 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 37165.425532 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35455.808081 # average overall mshr miss latency -system.cpu.icache.demand_hits 129712620 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 34935500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 168863429 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 34706.050695 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency +system.cpu.icache.demand_hits 168862206 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42445500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_misses 940 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 148 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 28081000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 792 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_misses 1223 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 30614500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 867 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.352940 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 722.820283 # Average occupied blocks per context -system.cpu.icache.overall_accesses 129713560 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 37165.425532 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35455.808081 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.386137 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 790.808810 # Average occupied blocks per context +system.cpu.icache.overall_accesses 168863429 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 34706.050695 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 129712620 # number of overall hits -system.cpu.icache.overall_miss_latency 34935500 # number of overall miss cycles +system.cpu.icache.overall_hits 168862206 # number of overall hits +system.cpu.icache.overall_miss_latency 42445500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_misses 940 # number of overall misses -system.cpu.icache.overall_mshr_hits 148 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 28081000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 792 # number of overall MSHR misses +system.cpu.icache.overall_misses 1223 # number of overall misses +system.cpu.icache.overall_mshr_hits 356 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 30614500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 867 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.sampled_refs 792 # Sample count of references to valid blocks. +system.cpu.icache.replacements 11 # number of replacements +system.cpu.icache.sampled_refs 867 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 722.820283 # Cycle average of tags in use -system.cpu.icache.total_refs 129712620 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 790.808810 # Cycle average of tags in use +system.cpu.icache.total_refs 168862206 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 214442 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 108628514 # Number of branches executed +system.cpu.idleCycles 291024 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 111314295 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.113825 # Inst execution rate -system.cpu.iew.EXEC:refs 627755630 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 190105687 # Number of stores executed +system.cpu.iew.EXEC:rate 1.203312 # Inst execution rate +system.cpu.iew.EXEC:refs 636104355 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 191312994 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1860684264 # num instructions consuming a value -system.cpu.iew.WB:count 1687762822 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.711350 # average fanout of values written-back +system.cpu.iew.WB:consumers 2089450315 # num instructions consuming a value +system.cpu.iew.WB:count 1839101566 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.684612 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1323598001 # num instructions producing a value -system.cpu.iew.WB:rate 1.111847 # insts written-back per cycle -system.cpu.iew.WB:sent 1688206003 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6113342 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1234561 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 466864036 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3697894 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 198431314 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 1795988309 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 437649943 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 8316492 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1690766136 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 11689 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1430463261 # num instructions producing a value +system.cpu.iew.WB:rate 1.200117 # insts written-back per cycle +system.cpu.iew.WB:sent 1842290775 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 8145736 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1415270 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 617903270 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 633937 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 251132554 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2351086206 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 444791361 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11969895 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1843997360 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 60905 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 29266045 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 61051 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 99870091 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 117847 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 29308 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 108968785 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 18692 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 29753 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 113796852 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 8470 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6882405 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 14 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 47821911 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 10245257 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 6882405 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 2235 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 6111107 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 3195299120 # number of integer regfile reads -system.cpu.int_regfile_writes 1684589292 # number of integer regfile writes -system.cpu.ipc 1.068191 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.068191 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 24153767 1.42% 1.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1042557757 61.36% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 442155303 26.02% 88.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 190215801 11.20% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 6921754 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 21 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 198861145 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 62946497 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 6921754 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 3700861 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4444875 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 3233304065 # number of integer regfile reads +system.cpu.int_regfile_writes 1832324218 # number of integer regfile writes +system.cpu.ipc 1.058116 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.058116 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 27128947 1.46% 1.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1186880889 63.95% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 450365179 24.27% 89.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 191592240 10.32% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1699082628 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 898465 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000529 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1855967255 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 4437489 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002391 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 2 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 782842 87.13% 87.13% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 115621 12.87% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 118316 2.67% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 3486899 78.58% 81.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 832274 18.76% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1517766953 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.119462 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.970342 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1532144387 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.211353 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.177271 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 418312841 27.56% 27.56% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 673262157 44.36% 71.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 290551111 19.14% 91.06% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 102329684 6.74% 97.81% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 29422654 1.94% 99.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 3376155 0.22% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 428915 0.03% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 83172 0.01% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 264 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 466354124 30.44% 30.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 601647548 39.27% 69.71% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 244545222 15.96% 85.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 139808763 9.13% 94.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 60228260 3.93% 98.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 13792665 0.90% 99.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 4627487 0.30% 99.93% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 960857 0.06% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 179461 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1517766953 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.119304 # Inst issue rate -system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 1675827322 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 4916833706 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1687762820 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 1976960091 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 1795988242 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1699082628 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 67 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 174090375 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 3040 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 322977188 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 247374 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34288.873379 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31083.636921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 188632 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2014197000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.237462 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 58742 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1825915000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.237462 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58742 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 207481 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34134.816432 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.350224 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 174959 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1110132500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.156747 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32522 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1008356000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156747 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32522 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 403776 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 403776 # number of Writeback hits +system.cpu.iq.ISSUE:issued_per_cycle::total 1532144387 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.211123 # Inst issue rate +system.cpu.iq.fp_alu_accesses 18 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 33 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1833275779 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5248603279 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1839101554 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 3087460502 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 2351086128 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1855967255 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 729454588 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 86926 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1543114171 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 250094 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.888228 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31092.455043 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 191260 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2021765000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.235248 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 58834 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1829293500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235248 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 58834 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 215648 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34134.880348 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.967489 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 182552 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1129728000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.153472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33096 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1026173500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153472 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33096 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 411288 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 411288 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.963363 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.099303 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 454855 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34233.975061 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31055.739393 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 363591 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3124329500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.200644 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 91264 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 465742 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34281.442402 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 373812 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3151493000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.197384 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 91930 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2834271000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.200644 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 91264 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2855467000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.197384 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 91930 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.058891 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.491980 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1929.753834 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16121.198217 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 454855 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34233.975061 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31055.739393 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.059053 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.491352 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1935.054426 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16100.609355 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 465742 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34281.442402 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 363591 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3124329500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.200644 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 91264 # number of overall misses +system.cpu.l2cache.overall_hits 373812 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3151493000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.197384 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 91930 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2834271000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.200644 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 91264 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2855467000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.197384 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 91930 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 72998 # number of replacements -system.cpu.l2cache.sampled_refs 88598 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 73661 # number of replacements +system.cpu.l2cache.sampled_refs 89262 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18050.952051 # Cycle average of tags in use -system.cpu.l2cache.total_refs 439744 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18035.663781 # Cycle average of tags in use +system.cpu.l2cache.total_refs 455174 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58419 # number of writebacks -system.cpu.memDep0.conflictingLoads 312249439 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 119901234 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 466864036 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 198431314 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 865536711 # number of misc regfile reads -system.cpu.numCycles 1517981395 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 58542 # number of writebacks +system.cpu.memDep0.conflictingLoads 537232404 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 219207458 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 617903270 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 251132554 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 931505074 # number of misc regfile reads +system.cpu.numCycles 1532435411 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 28986025 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 175534951 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 33672472 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 389992916 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 45640252 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 23 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 4455391031 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 1827559293 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1825935922 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 951399892 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 29266045 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 118119949 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 207941272 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 32 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 4455390999 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 2126 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 68 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 172417007 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 68 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3280069639 # The number of ROB reads -system.cpu.rob.rob_writes 3621261017 # The number of ROB writes -system.cpu.timesIdled 45168 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 318243703 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 499996104 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 107154792 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 44 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 5827367622 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2403532061 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2403383901 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 306300874 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 99870091 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 450439326 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 785389251 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 5827367526 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 3041 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 87 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 739921776 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 87 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3775835718 # The number of ROB reads +system.cpu.rob.rob_writes 4802062478 # The number of ROB writes +system.cpu.timesIdled 45517 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- |