diff options
Diffstat (limited to 'tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 1862 |
1 files changed, 931 insertions, 931 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 39fd478e5..cba8f3d91 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,388 +1,388 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 160492 # Simulator instruction rate (inst/s) -host_mem_usage 293848 # Number of bytes of host memory used -host_seconds 355.10 # Real time elapsed on the host -host_tick_rate 5352987788 # Simulator tick rate (ticks/s) +host_inst_rate 123407 # Simulator instruction rate (inst/s) +host_mem_usage 293584 # Number of bytes of host memory used +host_seconds 461.81 # Real time elapsed on the host +host_tick_rate 4116011383 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56990213 # Number of instructions simulated -sim_seconds 1.900832 # Number of seconds simulated -sim_ticks 1900831708500 # Number of ticks simulated +sim_insts 56990797 # Number of instructions simulated +sim_seconds 1.900831 # Number of seconds simulated +sim_ticks 1900831034500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 5880494 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 11174244 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 27800 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 685606 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 10433425 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 12492393 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 880061 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 7524876 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 920219 # number cycles where commit BW limit reached +system.cpu0.BPredUnit.BTBHits 5875698 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 11164328 # Number of BTB lookups +system.cpu0.BPredUnit.RASInCorrect 27744 # Number of incorrect RAS predictions. +system.cpu0.BPredUnit.condIncorrect 509294 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 10430748 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 12489171 # Number of BP lookups +system.cpu0.BPredUnit.usedRAS 879952 # Number of times the RAS was used to get a target. +system.cpu0.commit.COM:branches 7522146 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 923087 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 78262011 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.636166 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 1.402915 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 78252168 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.636069 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 1.403085 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0 56998112 72.83% 72.83% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1 9312532 11.90% 84.73% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2 5431102 6.94% 91.67% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3 2441098 3.12% 94.79% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4 1859715 2.38% 97.16% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5 630504 0.81% 97.97% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6 344653 0.44% 98.41% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7 324076 0.41% 98.82% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 920219 1.18% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0 56997236 72.84% 72.84% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1 9310198 11.90% 84.74% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2 5423748 6.93% 91.67% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3 2443659 3.12% 94.79% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4 1857092 2.37% 97.16% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5 632524 0.81% 97.97% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6 342942 0.44% 98.41% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7 321682 0.41% 98.82% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 923087 1.18% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 78262011 # Number of insts commited each cycle -system.cpu0.commit.COM:count 49787612 # Number of instructions committed -system.cpu0.commit.COM:loads 7895841 # Number of loads committed +system.cpu0.commit.COM:committed_per_cycle::total 78252168 # Number of insts commited each cycle +system.cpu0.commit.COM:count 49773781 # Number of instructions committed +system.cpu0.commit.COM:loads 7894849 # Number of loads committed system.cpu0.commit.COM:membars 191655 # Number of memory barriers committed -system.cpu0.commit.COM:refs 13320204 # Number of memory references committed +system.cpu0.commit.COM:refs 13318728 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 652972 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 49787612 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 564765 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 7275284 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 46926792 # Number of Instructions Simulated -system.cpu0.committedInsts_total 46926792 # Number of Instructions Simulated -system.cpu0.cpi 2.403365 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.403365 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses::0 178266 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 178266 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14383.082008 # average LoadLockedReq miss latency +system.cpu0.commit.branchMispredicts 652792 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 49773781 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 564764 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 7279166 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 46913211 # Number of Instructions Simulated +system.cpu0.committedInsts_total 46913211 # Number of Instructions Simulated +system.cpu0.cpi 2.403631 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.403631 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses::0 178258 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 178258 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14381.476316 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10555.240699 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 158902 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 158902 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 278514000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108624 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 19364 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19364 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 4366 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158307500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084133 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10558.033333 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::0 158899 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 158899 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 278411000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108601 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 19359 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19359 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 4359 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158370500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084148 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 14998 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 8019167 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8019167 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 23754.581419 # average ReadReq miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses 15000 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::0 8018067 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8018067 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 23754.598189 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23767.536326 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.786651 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 6641537 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6641537 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 32725024000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.171792 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 1377630 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1377630 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 392532 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 23413352500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122843 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits::0 6640677 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6640677 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 32719346000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::0 0.171786 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1377390 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1377390 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 392262 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 23413327000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122864 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 985098 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920862000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 185115 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 185115 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13269.357045 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_mshr_misses 985128 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920863000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses::0 185114 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 185114 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13329.315068 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10269.978106 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 181460 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 181460 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 48499500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019744 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 3655 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3655 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37526500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019739 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10326.164384 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits::0 181464 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 181464 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 48652000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019718 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 3650 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3650 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37690500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019718 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 3654 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 5224194 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5224194 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 32391.467747 # average WriteReq miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses 3650 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses::0 5223711 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5223711 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 32400.753552 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30578.461362 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30590.522294 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 3607293 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3607293 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 52373796592 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.309502 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 1616901 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1616901 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1353492 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 8054641929 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050421 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_hits::0 3606992 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3606992 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 52382913882 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::0 0.309496 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 1616719 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1616719 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1353304 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 8058002430 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050427 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 263409 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320645998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8778.099961 # average number of cycles each access was blocked +system.cpu0.dcache.WriteReq_mshr_misses 263415 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320187498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8768.456221 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 8.500462 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 83583 # number of cycles access was blocked +system.cpu0.dcache.avg_refs 8.499270 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 83762 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 733699929 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 734463430 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 150500 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 13243361 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::0 13241778 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13243361 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 28418.079690 # average overall miss latency +system.cpu0.dcache.demand_accesses::total 13241778 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 28423.233717 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 25204.499798 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 10248830 # number of demand (read+write) hits +system.cpu0.dcache.demand_avg_mshr_miss_latency 25206.444175 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::0 10247669 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10248830 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 85098820592 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.226116 # miss rate for demand accesses +system.cpu0.dcache.demand_hits::total 10247669 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 85102259882 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::0 0.226111 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 2994531 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 2994109 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2994531 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1746024 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 31467994429 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.094274 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_misses::total 2994109 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1745566 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 31471329430 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0.094288 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1248507 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses 1248543 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.973616 # Average percentage of cache occupancy +system.cpu0.dcache.occ_%::0 0.973184 # Average percentage of cache occupancy system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 498.491430 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 498.270236 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses::0 13243361 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::0 13241778 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13243361 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 28418.079690 # average overall miss latency +system.cpu0.dcache.overall_accesses::total 13241778 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 28423.233717 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 25204.499798 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 25206.444175 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 10248830 # number of overall hits +system.cpu0.dcache.overall_hits::0 10247669 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 10248830 # number of overall hits -system.cpu0.dcache.overall_miss_latency 85098820592 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.226116 # miss rate for overall accesses +system.cpu0.dcache.overall_hits::total 10247669 # number of overall hits +system.cpu0.dcache.overall_miss_latency 85102259882 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate::0 0.226111 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 2994531 # number of overall misses +system.cpu0.dcache.overall_misses::0 2994109 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2994531 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1746024 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 31467994429 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.094274 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_misses::total 2994109 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1745566 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 31471329430 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate::0 0.094288 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1248507 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2241507998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_misses 1248543 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2241050498 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 1246700 # number of replacements -system.cpu0.dcache.sampled_refs 1247212 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1246737 # number of replacements +system.cpu0.dcache.sampled_refs 1247249 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 497.491430 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10601878 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 497.270236 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10600706 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 721554 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 33792520 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 33358 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 521061 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 62605463 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 32178672 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 11309201 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1270716 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 100684 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 981617 # Number of cycles decode is unblocking -system.cpu0.dtb.data_accesses 795304 # DTB accesses +system.cpu0.dcache.writebacks 721582 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 33790460 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 33337 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 520850 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 62592464 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 32176672 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 11304141 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1271125 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 100674 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 980894 # Number of cycles decode is unblocking +system.cpu0.dtb.data_accesses 795039 # DTB accesses system.cpu0.dtb.data_acv 690 # DTB access violations -system.cpu0.dtb.data_hits 14242761 # DTB hits -system.cpu0.dtb.data_misses 32467 # DTB misses +system.cpu0.dtb.data_hits 14240441 # DTB hits +system.cpu0.dtb.data_misses 32243 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 599691 # DTB read accesses -system.cpu0.dtb.read_acv 517 # DTB read access violations -system.cpu0.dtb.read_hits 8658240 # DTB read hits -system.cpu0.dtb.read_misses 26670 # DTB read misses -system.cpu0.dtb.write_accesses 195613 # DTB write accesses -system.cpu0.dtb.write_acv 173 # DTB write access violations -system.cpu0.dtb.write_hits 5584521 # DTB write hits -system.cpu0.dtb.write_misses 5797 # DTB write misses -system.cpu0.fetch.Branches 12492393 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 7792591 # Number of cache lines fetched -system.cpu0.fetch.Cycles 20275777 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 374501 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 63694095 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 1162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 745780 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.110766 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 7792591 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 6760555 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.564753 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 79532727 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.800854 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.104099 # Number of instructions fetched each cycle (Total) +system.cpu0.dtb.read_accesses 599364 # DTB read accesses +system.cpu0.dtb.read_acv 521 # DTB read access violations +system.cpu0.dtb.read_hits 8656203 # DTB read hits +system.cpu0.dtb.read_misses 26609 # DTB read misses +system.cpu0.dtb.write_accesses 195675 # DTB write accesses +system.cpu0.dtb.write_acv 169 # DTB write access violations +system.cpu0.dtb.write_hits 5584238 # DTB write hits +system.cpu0.dtb.write_misses 5634 # DTB write misses +system.cpu0.fetch.Branches 12489171 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 7790772 # Number of cache lines fetched +system.cpu0.fetch.Cycles 12447663 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 374479 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 63679882 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 30613 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 745308 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.110757 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 7790769 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 6755650 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.564728 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 79523293 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.800770 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.103978 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67079150 84.34% 84.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 900735 1.13% 85.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1776168 2.23% 87.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 808150 1.02% 88.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2746406 3.45% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 585611 0.74% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 679507 0.85% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 830147 1.04% 94.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4126853 5.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67075630 84.35% 84.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 894785 1.13% 85.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1774565 2.23% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 813228 1.02% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2745570 3.45% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 583311 0.73% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 681126 0.86% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 829932 1.04% 94.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4125146 5.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79532727 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses::0 7792591 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7792591 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 15067.531748 # average ReadReq miss latency +system.cpu0.fetch.rateDist::total 79523293 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses::0 7790772 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7790772 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.907100 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12017.722051 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 6935061 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6935061 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 12920860500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.110044 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 857530 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 857530 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 36660 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 9864987500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.105340 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12016.512006 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits::0 6933292 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6933292 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 12919571500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate::0 0.110064 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 857480 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 857480 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 36653 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 9863477500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.105359 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 820870 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11583.333333 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_mshr_misses 820827 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11372.727273 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 8.449643 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 54 # number of cycles access was blocked +system.cpu0.icache.avg_refs 8.447909 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 55 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_mshrs 625500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 7792591 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::0 7790772 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7792591 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 15067.531748 # average overall miss latency +system.cpu0.icache.demand_accesses::total 7790772 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 15066.907100 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12017.722051 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 6935061 # number of demand (read+write) hits +system.cpu0.icache.demand_avg_mshr_miss_latency 12016.512006 # average overall mshr miss latency +system.cpu0.icache.demand_hits::0 6933292 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6935061 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 12920860500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.110044 # miss rate for demand accesses +system.cpu0.icache.demand_hits::total 6933292 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 12919571500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::0 0.110064 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 857530 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::0 857480 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 857530 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 36660 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 9864987500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.105340 # mshr miss rate for demand accesses +system.cpu0.icache.demand_misses::total 857480 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 36653 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 9863477500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0.105359 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 820870 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses 820827 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.occ_%::0 0.995823 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 509.861229 # Average occupied blocks per context -system.cpu0.icache.overall_accesses::0 7792591 # number of overall (read+write) accesses +system.cpu0.icache.occ_blocks::0 509.861442 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 7790772 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7792591 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 15067.531748 # average overall miss latency +system.cpu0.icache.overall_accesses::total 7790772 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 15066.907100 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12017.722051 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12016.512006 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 6935061 # number of overall hits +system.cpu0.icache.overall_hits::0 6933292 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 6935061 # number of overall hits -system.cpu0.icache.overall_miss_latency 12920860500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.110044 # miss rate for overall accesses +system.cpu0.icache.overall_hits::total 6933292 # number of overall hits +system.cpu0.icache.overall_miss_latency 12919571500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::0 0.110064 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 857530 # number of overall misses +system.cpu0.icache.overall_misses::0 857480 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 857530 # number of overall misses -system.cpu0.icache.overall_mshr_hits 36660 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 9864987500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.105340 # mshr miss rate for overall accesses +system.cpu0.icache.overall_misses::total 857480 # number of overall misses +system.cpu0.icache.overall_mshr_hits 36653 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 9863477500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::0 0.105359 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 820870 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses 820827 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 820241 # number of replacements -system.cpu0.icache.sampled_refs 820752 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 820200 # number of replacements +system.cpu0.icache.sampled_refs 820711 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.861229 # Cycle average of tags in use -system.cpu0.icache.total_refs 6935061 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 509.861442 # Cycle average of tags in use +system.cpu0.icache.total_refs 6933292 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 24435382000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 109 # number of writebacks -system.cpu0.idleCycles 33249487 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 8091689 # Number of branches executed -system.cpu0.iew.EXEC:nop 3189515 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.446670 # Inst execution rate -system.cpu0.iew.EXEC:refs 14309755 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 5603066 # Number of stores executed +system.cpu0.icache.writebacks 107 # number of writebacks +system.cpu0.idleCycles 33238734 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 8088887 # Number of branches executed +system.cpu0.iew.EXEC:nop 3190702 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.446643 # Inst execution rate +system.cpu0.iew.EXEC:refs 14307235 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 5602635 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 31608779 # num instructions consuming a value -system.cpu0.iew.WB:count 49999865 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.758055 # average fanout of values written-back +system.cpu0.iew.WB:consumers 31606218 # num instructions consuming a value +system.cpu0.iew.WB:count 49988672 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.757998 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 23961182 # num instructions producing a value -system.cpu0.iew.WB:rate 0.443331 # insts written-back per cycle -system.cpu0.iew.WB:sent 50082132 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 711844 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 9016513 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 9135520 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1511943 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 755935 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 5842466 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 57173513 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 8706689 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 463253 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 50376392 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 59411 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 23957449 # num instructions producing a value +system.cpu0.iew.WB:rate 0.443311 # insts written-back per cycle +system.cpu0.iew.WB:sent 50070625 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 711853 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 9019183 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 9134564 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1512032 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 755923 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 5843380 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 57163450 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 8704600 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 462366 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 50364381 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 59583 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 6975 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1270716 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 547260 # Number of cycles IEW is unblocking +system.cpu0.iew.iewLSQFullEvents 7004 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1271125 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 547384 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 122212 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 411295 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 10786 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.cacheBlocked 122021 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 410783 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 10667 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 39006 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 18611 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1239679 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 418103 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 39006 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 331745 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 380099 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.416083 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.416083 # IPC: Total IPC of All Threads +system.cpu0.iew.lsq.thread.0.memOrderViolation 38522 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 18606 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1239715 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 419501 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 38522 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 332064 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 379789 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.416037 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.416037 # IPC: Total IPC of All Threads system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35332190 69.50% 69.50% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 55947 0.11% 69.61% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35322205 69.50% 69.50% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 55712 0.11% 69.61% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.61% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15323 0.03% 69.64% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.64% # Type of FU issued @@ -410,80 +410,80 @@ system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 69.65% system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 9005421 17.71% 87.36% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645944 11.11% 98.47% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779180 1.53% 100.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 9003021 17.71% 87.36% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645656 11.11% 98.47% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779190 1.53% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 50839647 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 380083 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.007476 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 50826749 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 382289 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007521 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 41221 10.85% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 225189 59.25% 70.09% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 113673 29.91% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 40958 10.71% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 226307 59.20% 69.91% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 115024 30.09% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 79532727 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.639229 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.210023 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 79523293 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.639143 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.209985 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0 54768244 68.86% 68.86% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1 12092577 15.20% 84.07% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2 5445890 6.85% 90.91% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3 3420529 4.30% 95.22% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4 2219923 2.79% 98.01% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5 995680 1.25% 99.26% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6 437086 0.55% 99.81% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7 109289 0.14% 99.95% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 43509 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0 54765331 68.87% 68.87% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1 12086611 15.20% 84.07% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2 5449422 6.85% 90.92% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3 3416951 4.30% 95.22% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4 2222762 2.80% 98.01% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5 992615 1.25% 99.26% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6 434574 0.55% 99.81% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7 111342 0.14% 99.95% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 43685 0.05% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 79532727 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.450777 # Inst issue rate -system.cpu0.iq.iqInstsAdded 52261894 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 50839647 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1722104 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 6736109 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 24176 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 1157339 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3425002 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.ISSUE:issued_per_cycle::total 79523293 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.450743 # Inst issue rate +system.cpu0.iq.iqInstsAdded 52250537 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 50826749 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1722211 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 6740578 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 24052 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 1157447 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3424469 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 951977 # ITB accesses -system.cpu0.itb.fetch_acv 722 # ITB acv -system.cpu0.itb.fetch_hits 923088 # ITB hits -system.cpu0.itb.fetch_misses 28889 # ITB misses +system.cpu0.itb.fetch_accesses 951927 # ITB accesses +system.cpu0.itb.fetch_acv 732 # ITB acv +system.cpu0.itb.fetch_hits 922973 # ITB hits +system.cpu0.itb.fetch_misses 28954 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_hits 0 # DTB read hits @@ -500,7 +500,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.22% # nu system.cpu0.kern.callpal::swpctx 3287 2.03% 2.25% # number of callpals executed system.cpu0.kern.callpal::tbi 43 0.03% 2.27% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed -system.cpu0.kern.callpal::swpipl 147043 90.75% 93.03% # number of callpals executed +system.cpu0.kern.callpal::swpipl 147045 90.75% 93.03% # number of callpals executed system.cpu0.kern.callpal::rdps 6369 3.93% 96.96% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.96% # number of callpals executed @@ -509,45 +509,45 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.96% # nu system.cpu0.kern.callpal::rti 4450 2.75% 99.71% # number of callpals executed system.cpu0.kern.callpal::callsys 330 0.20% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 162035 # number of callpals executed +system.cpu0.kern.callpal::total 162037 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.hwrei 176106 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6625 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 6624 # number of quiesce instructions executed system.cpu0.kern.ipl_count::0 62137 40.37% 40.37% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 238 0.15% 40.53% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1925 1.25% 41.78% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 254 0.17% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 89357 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 153911 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 89359 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 153913 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 61267 49.13% 49.13% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 238 0.19% 49.32% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1925 1.54% 50.87% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 254 0.20% 51.07% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 61013 48.93% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 124697 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862701571500 97.99% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 96288500 0.01% 98.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 398425500 0.02% 98.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 103369500 0.01% 98.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 37531203000 1.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1900830858000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1862706719500 97.99% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 96293500 0.01% 98.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 398446500 0.02% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 103381000 0.01% 98.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37525343500 1.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1900830184000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.985999 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682800 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good::kernel 1170 -system.cpu0.kern.mode_good::user 1171 +system.cpu0.kern.ipl_used::31 0.682785 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1172 +system.cpu0.kern.mode_good::user 1173 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1171 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 6890 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.169762 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.170102 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1898856944500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1973905500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1898860791500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1969384500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3288 # number of times the context was actually changed system.cpu0.kern.syscall::2 6 2.99% 2.99% # number of syscalls executed @@ -580,503 +580,503 @@ system.cpu0.kern.syscall::132 1 0.50% 98.51% # nu system.cpu0.kern.syscall::144 1 0.50% 99.00% # number of syscalls executed system.cpu0.kern.syscall::147 2 1.00% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 201 # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 2309039 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1917455 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 9135520 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5842466 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 112782214 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 12781389 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 33989509 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 1007909 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 33583011 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1370380 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 43256 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 72564759 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 59338809 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 39990302 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 11042113 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1270716 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 3987723 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 6000791 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 16867773 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1393581 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 10085074 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 207606 # count of temporary serializing insts renamed -system.cpu0.timesIdled 1187595 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.memDep0.conflictingLoads 2324520 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1920330 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 9134564 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5843380 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 112762027 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 12784616 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 33979042 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 1006695 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 33581656 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1371330 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 43310 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 72537525 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 59326371 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 39979107 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 11035754 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1271125 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3987965 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 6000063 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 16862175 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1393641 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 10087757 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 207582 # count of temporary serializing insts renamed +system.cpu0.timesIdled 1187239 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 1159628 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 2701076 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 8300 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 172219 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 2481214 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 2994712 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 209821 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 1517871 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 197774 # number cycles where commit BW limit reached +system.cpu1.BPredUnit.BTBHits 1159872 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 2699541 # Number of BTB lookups +system.cpu1.BPredUnit.RASInCorrect 8252 # Number of incorrect RAS predictions. +system.cpu1.BPredUnit.condIncorrect 107435 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 2484356 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 2997970 # Number of BP lookups +system.cpu1.BPredUnit.usedRAS 209804 # Number of times the RAS was used to get a target. +system.cpu1.commit.COM:branches 1520810 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 200192 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 17831958 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.593915 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.406567 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 17838555 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.594502 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.408069 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0 13448737 75.42% 75.42% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1 2070572 11.61% 87.03% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2 799926 4.49% 91.52% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3 567078 3.18% 94.70% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4 394341 2.21% 96.91% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5 151842 0.85% 97.76% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6 111575 0.63% 98.39% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7 90113 0.51% 98.89% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 197774 1.11% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0 13455309 75.43% 75.43% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1 2068240 11.59% 87.02% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2 796982 4.47% 91.49% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3 568404 3.19% 94.68% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4 398869 2.24% 96.91% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5 150882 0.85% 97.76% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6 111519 0.63% 98.38% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7 88158 0.49% 98.88% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 200192 1.12% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 17831958 # Number of insts commited each cycle -system.cpu1.commit.COM:count 10590665 # Number of instructions committed -system.cpu1.commit.COM:loads 1991024 # Number of loads committed -system.cpu1.commit.COM:membars 52740 # Number of memory barriers committed -system.cpu1.commit.COM:refs 3374947 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 17838555 # Number of insts commited each cycle +system.cpu1.commit.COM:count 10605058 # Number of instructions committed +system.cpu1.commit.COM:loads 1991974 # Number of loads committed +system.cpu1.commit.COM:membars 52733 # Number of memory barriers committed +system.cpu1.commit.COM:refs 3376359 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 164356 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 10590665 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 163015 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 1719784 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 10063421 # Number of Instructions Simulated -system.cpu1.committedInsts_total 10063421 # Number of Instructions Simulated -system.cpu1.cpi 1.950737 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.950737 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses::0 46382 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 46382 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11099.301842 # average LoadLockedReq miss latency +system.cpu1.commit.branchMispredicts 164468 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 10605058 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 163004 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 1721791 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 10077586 # Number of Instructions Simulated +system.cpu1.committedInsts_total 10077586 # Number of Instructions Simulated +system.cpu1.cpi 1.948890 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.948890 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses::0 46378 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 46378 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11069.539376 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8021.283727 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 39650 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 39650 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 74720500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145143 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 6732 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 6732 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 765 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47863000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128649 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7993.965806 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::0 39648 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 39648 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 74498000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145112 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 6730 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 6730 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 764 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47692000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128639 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 5967 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 2063263 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2063263 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15045.752696 # average ReadReq miss latency +system.cpu1.dcache.LoadLockedReq_mshr_misses 5966 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::0 2062902 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2062902 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15016.821540 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11684.073615 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11679.389313 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 1869340 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1869340 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 2917717500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.093989 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 193923 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 193923 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 98779 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 1111669500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046113 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits::0 1868657 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1868657 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 2916942500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::0 0.094161 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 194245 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 194245 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 99139 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 1110780000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046103 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 95144 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses 95106 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 17677500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 43195 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 43195 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13108.977686 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_accesses::0 43196 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 43196 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13130.603783 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10107.291126 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 39341 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 39341 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 50522000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089223 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 3854 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3854 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 38953500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089223 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10135.856884 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits::0 39337 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 39337 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 50671000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089337 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 3859 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3859 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 39094000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089291 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 3854 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 1334339 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1334339 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 21230.266809 # average WriteReq miss latency +system.cpu1.dcache.StoreCondReq_mshr_misses 3857 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses::0 1334800 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1334800 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 21227.985433 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18781.127505 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18769.279348 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 1084932 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1084932 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 5294977154 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.186914 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 249407 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 249407 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 200954 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 910001971 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.036312 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_hits::0 1085325 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1085325 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 5295851666 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::0 0.186901 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 249475 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 249475 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 201005 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 909746970 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.036313 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 48453 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377711000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9964.987699 # average number of cycles each access was blocked +system.cpu1.dcache.WriteReq_mshr_misses 48470 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377654500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9972.984645 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 22.877704 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 5284 # number of cycles access was blocked +system.cpu1.dcache.avg_refs 22.879556 # Average number of references to valid blocks. +system.cpu1.dcache.blocked::no_mshrs 5275 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 52654995 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 52607494 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 3397602 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::0 3397702 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3397602 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 18525.014445 # average overall miss latency +system.cpu1.dcache.demand_accesses::total 3397702 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 18508.956473 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14078.786263 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 2954272 # number of demand (read+write) hits +system.cpu1.dcache.demand_avg_mshr_miss_latency 14072.874088 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::0 2953982 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2954272 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 8212694654 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.130483 # miss rate for demand accesses +system.cpu1.dcache.demand_hits::total 2953982 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 8212794166 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::0 0.130594 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 443330 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 443720 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 443330 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 299733 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 2021671471 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.042264 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_misses::total 443720 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 300144 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 2020526970 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0.042257 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 143597 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses 143576 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.933246 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 477.822051 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses::0 3397602 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.933238 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 477.817937 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 3397702 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3397602 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 18525.014445 # average overall miss latency +system.cpu1.dcache.overall_accesses::total 3397702 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 18508.956473 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14078.786263 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14072.874088 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 2954272 # number of overall hits +system.cpu1.dcache.overall_hits::0 2953982 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 2954272 # number of overall hits -system.cpu1.dcache.overall_miss_latency 8212694654 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.130483 # miss rate for overall accesses +system.cpu1.dcache.overall_hits::total 2953982 # number of overall hits +system.cpu1.dcache.overall_miss_latency 8212794166 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::0 0.130594 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 443330 # number of overall misses +system.cpu1.dcache.overall_misses::0 443720 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 443330 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 299733 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 2021671471 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.042264 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_misses::total 443720 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 300144 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 2020526970 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::0 0.042257 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 143597 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 395388500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_misses 143576 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 395332000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 132546 # number of replacements -system.cpu1.dcache.sampled_refs 132940 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 132522 # number of replacements +system.cpu1.dcache.sampled_refs 132916 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 477.822051 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3041362 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1877659740000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 88702 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 6966662 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:BranchMispred 7945 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 127784 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 13937245 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 8263002 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 2503476 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 305841 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 23696 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 98817 # Number of cycles decode is unblocking -system.cpu1.dtb.data_accesses 453673 # DTB accesses +system.cpu1.dcache.tagsinuse 477.817937 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3041059 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1877659429000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 88703 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 6965197 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BranchMispred 7952 # Number of times decode detected a branch misprediction +system.cpu1.decode.DECODE:BranchResolved 127936 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 13953075 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 8268454 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 2505615 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 305805 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 23745 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 99288 # Number of cycles decode is unblocking +system.cpu1.dtb.data_accesses 453627 # DTB accesses system.cpu1.dtb.data_acv 183 # DTB access violations -system.cpu1.dtb.data_hits 3613751 # DTB hits -system.cpu1.dtb.data_misses 13007 # DTB misses +system.cpu1.dtb.data_hits 3614601 # DTB hits +system.cpu1.dtb.data_misses 12965 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 322326 # DTB read accesses -system.cpu1.dtb.read_acv 82 # DTB read access violations -system.cpu1.dtb.read_hits 2187602 # DTB read hits -system.cpu1.dtb.read_misses 10512 # DTB read misses -system.cpu1.dtb.write_accesses 131347 # DTB write accesses -system.cpu1.dtb.write_acv 101 # DTB write access violations -system.cpu1.dtb.write_hits 1426149 # DTB write hits -system.cpu1.dtb.write_misses 2495 # DTB write misses -system.cpu1.fetch.Branches 2994712 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 1675694 # Number of cache lines fetched -system.cpu1.fetch.Cycles 4319661 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 103833 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 14189706 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 562 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 191595 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.152550 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 1675694 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 1369449 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.722818 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 18137799 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.782328 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.130924 # Number of instructions fetched each cycle (Total) +system.cpu1.dtb.read_accesses 321686 # DTB read accesses +system.cpu1.dtb.read_acv 80 # DTB read access violations +system.cpu1.dtb.read_hits 2187439 # DTB read hits +system.cpu1.dtb.read_misses 10558 # DTB read misses +system.cpu1.dtb.write_accesses 131941 # DTB write accesses +system.cpu1.dtb.write_acv 103 # DTB write access violations +system.cpu1.dtb.write_hits 1427162 # DTB write hits +system.cpu1.dtb.write_misses 2407 # DTB write misses +system.cpu1.fetch.Branches 2997970 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 1676515 # Number of cache lines fetched +system.cpu1.fetch.Cycles 2637646 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 103832 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 14205200 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 9114 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 191574 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.152645 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 1676514 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 1369676 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.723275 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 18144360 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.782899 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.130950 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 15502694 85.47% 85.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 211332 1.17% 86.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 324186 1.79% 88.42% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 198526 1.09% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 376340 2.07% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 125878 0.69% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 169328 0.93% 93.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 252414 1.39% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 977101 5.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 15506714 85.46% 85.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 209351 1.15% 86.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 321604 1.77% 88.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 202250 1.11% 89.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 379744 2.09% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 126923 0.70% 92.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 169833 0.94% 93.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 250226 1.38% 94.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 977715 5.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 18137799 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses::0 1675694 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1675694 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 14669.843213 # average ReadReq miss latency +system.cpu1.fetch.rateDist::total 18144360 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses::0 1676515 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1676515 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.731413 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11629.039136 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 1411833 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1411833 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 3870799500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.157464 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 263861 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 263861 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 8268 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 2972301000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152530 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11628.822702 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits::0 1412481 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1412481 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 3874364000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::0 0.157490 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 264034 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 264034 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 8194 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 2975118000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152602 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 255593 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs 4444.444444 # average number of cycles each access was blocked +system.cpu1.icache.ReadReq_mshr_misses 255840 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs 5000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 5.524987 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu1.icache.avg_refs 5.522142 # Average number of references to valid blocks. +system.cpu1.icache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 40000 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 1675694 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::0 1676515 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1675694 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 14669.843213 # average overall miss latency +system.cpu1.icache.demand_accesses::total 1676515 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14673.731413 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11629.039136 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 1411833 # number of demand (read+write) hits +system.cpu1.icache.demand_avg_mshr_miss_latency 11628.822702 # average overall mshr miss latency +system.cpu1.icache.demand_hits::0 1412481 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1411833 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 3870799500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.157464 # miss rate for demand accesses +system.cpu1.icache.demand_hits::total 1412481 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 3874364000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::0 0.157490 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 263861 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::0 264034 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 263861 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 8268 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 2972301000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.152530 # mshr miss rate for demand accesses +system.cpu1.icache.demand_misses::total 264034 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 8194 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 2975118000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0.152602 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 255593 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses 255840 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.900435 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 461.022612 # Average occupied blocks per context -system.cpu1.icache.overall_accesses::0 1675694 # number of overall (read+write) accesses +system.cpu1.icache.occ_%::0 0.900434 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 461.022394 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 1676515 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1675694 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 14669.843213 # average overall miss latency +system.cpu1.icache.overall_accesses::total 1676515 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14673.731413 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11629.039136 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11628.822702 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 1411833 # number of overall hits +system.cpu1.icache.overall_hits::0 1412481 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 1411833 # number of overall hits -system.cpu1.icache.overall_miss_latency 3870799500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.157464 # miss rate for overall accesses +system.cpu1.icache.overall_hits::total 1412481 # number of overall hits +system.cpu1.icache.overall_miss_latency 3874364000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::0 0.157490 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 263861 # number of overall misses +system.cpu1.icache.overall_misses::0 264034 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 263861 # number of overall misses -system.cpu1.icache.overall_mshr_hits 8268 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 2972301000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.152530 # mshr miss rate for overall accesses +system.cpu1.icache.overall_misses::total 264034 # number of overall misses +system.cpu1.icache.overall_mshr_hits 8194 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 2975118000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::0 0.152602 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 255593 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses 255840 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 255024 # number of replacements -system.cpu1.icache.sampled_refs 255536 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 255273 # number of replacements +system.cpu1.icache.sampled_refs 255785 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 461.022612 # Cycle average of tags in use -system.cpu1.icache.total_refs 1411833 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1897916222000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 461.022394 # Cycle average of tags in use +system.cpu1.icache.total_refs 1412481 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1897915849000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 13 # number of writebacks -system.cpu1.idleCycles 1493284 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 1627599 # Number of branches executed -system.cpu1.iew.EXEC:nop 601660 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.551671 # Inst execution rate -system.cpu1.iew.EXEC:refs 3643304 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 1435691 # Number of stores executed +system.cpu1.idleCycles 1495744 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 1630347 # Number of branches executed +system.cpu1.iew.EXEC:nop 601729 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.552052 # Inst execution rate +system.cpu1.iew.EXEC:refs 3644132 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 1436628 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 6256127 # num instructions consuming a value -system.cpu1.iew.WB:count 10722196 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.736602 # average fanout of values written-back +system.cpu1.iew.WB:consumers 6274106 # num instructions consuming a value +system.cpu1.iew.WB:count 10735003 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.735138 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 4608274 # num instructions producing a value -system.cpu1.iew.WB:rate 0.546185 # insts written-back per cycle -system.cpu1.iew.WB:sent 10745464 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 178521 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 256730 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 2308752 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 500484 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 209358 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 1509923 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 12393438 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 2207613 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 106928 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 10829897 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 2615 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 4612335 # num instructions producing a value +system.cpu1.iew.WB:rate 0.546586 # insts written-back per cycle +system.cpu1.iew.WB:sent 10758148 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 178810 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 256636 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 2309588 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 500342 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 209309 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 1512714 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 12409933 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 2207504 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 107468 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 10842361 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 2486 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 4833 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 305841 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 10301 # Number of cycles IEW is unblocking +system.cpu1.iew.iewLSQFullEvents 4828 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 305805 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 10156 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 22559 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 67759 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 2215 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.cacheBlocked 22318 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 68189 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 2236 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 10819 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.memOrderViolation 10653 # Number of memory ordering violations system.cpu1.iew.lsq.thread.0.rescheduledLoads 380 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 317728 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 126000 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 10819 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 104538 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 73983 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.512627 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.512627 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3525 0.03% 0.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6858697 62.71% 62.74% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 17938 0.16% 62.91% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.91% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11432 0.10% 63.01% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.01% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.01% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.01% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 2282943 20.87% 83.90% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1452642 13.28% 97.18% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307886 2.82% 100.00% # Type of FU issued +system.cpu1.iew.lsq.thread.0.squashedLoads 317614 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 128329 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 10653 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 104816 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 73994 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.513113 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.513113 # IPC: Total IPC of All Threads +system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3524 0.03% 0.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6870860 62.75% 62.78% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 18138 0.17% 62.95% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.95% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11432 0.10% 63.05% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.05% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.05% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.05% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 2282503 20.85% 83.91% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1453754 13.28% 97.19% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307856 2.81% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 10936825 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 157834 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.014431 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 10949829 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 154910 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.014147 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 3969 2.51% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 94191 59.68% 62.19% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 59674 37.81% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 4092 2.64% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 90881 58.67% 61.31% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 59937 38.69% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 18137799 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.602985 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.207807 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 18144360 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.603484 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.209438 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0 12914156 71.20% 71.20% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1 2567061 14.15% 85.35% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2 1068417 5.89% 91.24% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3 686600 3.79% 95.03% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4 525581 2.90% 97.93% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5 238380 1.31% 99.24% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6 93711 0.52% 99.76% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7 34504 0.19% 99.95% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 9389 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0 12920190 71.21% 71.21% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1 2565455 14.14% 85.35% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2 1066502 5.88% 91.22% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3 689185 3.80% 95.02% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4 526783 2.90% 97.93% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5 236336 1.30% 99.23% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6 93675 0.52% 99.75% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7 36919 0.20% 99.95% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 9315 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 18137799 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.557118 # Inst issue rate -system.cpu1.iq.iqInstsAdded 11235835 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 10936825 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 555943 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 1653815 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 10214 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 392928 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 848491 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.ISSUE:issued_per_cycle::total 18144360 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.557524 # Inst issue rate +system.cpu1.iq.iqInstsAdded 11252421 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 10949829 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 555783 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 1655590 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 10152 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 392779 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 854299 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 449298 # ITB accesses -system.cpu1.itb.fetch_acv 268 # ITB acv -system.cpu1.itb.fetch_hits 440704 # ITB hits -system.cpu1.itb.fetch_misses 8594 # ITB misses +system.cpu1.itb.fetch_accesses 448461 # ITB accesses +system.cpu1.itb.fetch_acv 279 # ITB acv +system.cpu1.itb.fetch_hits 439821 # ITB hits +system.cpu1.itb.fetch_misses 8640 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_hits 0 # DTB read hits @@ -1092,7 +1092,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # nu system.cpu1.kern.callpal::swpctx 1450 2.54% 2.99% # number of callpals executed system.cpu1.kern.callpal::tbi 12 0.02% 3.01% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.02% # number of callpals executed -system.cpu1.kern.callpal::swpipl 49369 86.50% 89.53% # number of callpals executed +system.cpu1.kern.callpal::swpipl 49364 86.50% 89.53% # number of callpals executed system.cpu1.kern.callpal::rdps 2383 4.18% 93.70% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 93.71% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 93.71% # number of callpals executed @@ -1102,42 +1102,42 @@ system.cpu1.kern.callpal::rti 3352 5.87% 99.60% # nu system.cpu1.kern.callpal::callsys 187 0.33% 99.92% # number of callpals executed system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 57071 # number of callpals executed +system.cpu1.kern.callpal::total 57066 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 64910 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 64904 # number of hwrei instructions executed system.cpu1.kern.inst.quiesce 2510 # number of quiesce instructions executed -system.cpu1.kern.ipl_count::0 20666 37.58% 37.58% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1922 3.49% 41.07% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::0 20664 37.58% 37.58% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1922 3.50% 41.07% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 351 0.64% 41.71% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 32056 58.29% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 54995 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 20159 47.72% 47.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 32053 58.29% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 54990 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 20157 47.72% 47.72% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1922 4.55% 52.28% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 351 0.83% 53.11% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 19808 46.89% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 42240 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870775538500 98.44% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 348024500 0.02% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 137644500 0.01% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29219363500 1.54% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900480571000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.975467 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 19806 46.89% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 42236 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870770703000 98.44% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 347961500 0.02% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 137588500 0.01% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29223568000 1.54% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900479821000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.975465 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.617919 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 850 -system.cpu1.kern.mode_good::user 574 +system.cpu1.kern.ipl_used::31 0.617914 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 849 +system.cpu1.kern.mode_good::user 573 system.cpu1.kern.mode_good::idle 276 system.cpu1.kern.mode_switch::kernel 1766 # number of protection mode switches -system.cpu1.kern.mode_switch::user 574 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2543 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.481314 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch::user 573 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2541 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.480747 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.108533 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.589847 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 6310376000 0.33% 0.33% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1022366000 0.05% 0.39% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893135370000 99.61% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.108619 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.589366 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 6317362000 0.33% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1020701000 0.05% 0.39% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893129288000 99.61% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1451 # number of times the context was actually changed system.cpu1.kern.syscall::2 2 1.60% 1.60% # number of syscalls executed system.cpu1.kern.syscall::3 13 10.40% 12.00% # number of syscalls executed @@ -1162,29 +1162,29 @@ system.cpu1.kern.syscall::92 2 1.60% 96.80% # nu system.cpu1.kern.syscall::132 3 2.40% 99.20% # number of syscalls executed system.cpu1.kern.syscall::144 1 0.80% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 125 # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 490785 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 414407 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 2308752 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1509923 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 19631083 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 523690 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 7148714 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 34540 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 8495610 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 254592 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 15458 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 15445784 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 12915573 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 8478574 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 2357052 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 305841 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 801048 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 1329860 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 5654556 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 515569 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 2305021 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 52779 # count of temporary serializing insts renamed -system.cpu1.timesIdled 194610 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.memDep0.conflictingLoads 496033 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 413880 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 2309588 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1512714 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 19640104 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 522822 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 7159583 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 32718 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 8500925 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 256778 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 15506 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 15473473 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 12930857 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 8489204 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 2359874 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 305805 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 801183 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 1329621 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 5653749 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 515468 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 2303190 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 52722 # count of temporary serializing insts renamed +system.cpu1.timesIdled 194766 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1200,14 +1200,14 @@ system.disk2.dma_write_txs 1 # Nu system.iocache.ReadReq_accesses::1 172 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115273.244186 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115267.430233 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63273.244186 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19826998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63267.430233 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19825998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses::1 172 # number of ReadReq misses system.iocache.ReadReq_misses::total 172 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10882998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10881998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses @@ -1215,37 +1215,37 @@ system.iocache.ReadReq_mshr_misses 172 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137691.995716 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137704.871149 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85688.414469 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5721377806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85701.289902 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5721912806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3560524998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561059998 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6177.748159 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6175.549096 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64613068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64590068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41724 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137599.578276 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137612.376666 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85596.011792 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85608.810181 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5741204804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5741738804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -1253,7 +1253,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41724 # number of demand (read+write) misses system.iocache.demand_misses::total 41724 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3571407996 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571941996 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -1261,20 +1261,20 @@ system.iocache.demand_mshr_misses 41724 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.029207 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 0.467307 # Average occupied blocks per context +system.iocache.occ_%::1 0.029206 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.467303 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41724 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137599.578276 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137612.376666 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85596.011792 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85608.810181 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5741204804 # number of overall miss cycles +system.iocache.overall_miss_latency 5741738804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -1282,7 +1282,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41724 # number of overall misses system.iocache.overall_misses::total 41724 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3571407996 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571941996 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -1292,196 +1292,196 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41692 # number of replacements system.iocache.sampled_refs 41708 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.467307 # Cycle average of tags in use +system.iocache.tagsinuse 0.467303 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1711286220000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1711286190000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses::0 257314 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 42271 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 299585 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 55984.756831 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 837468.637532 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 257294 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 42294 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 299588 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 55984.033368 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 838025.398663 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40322.708602 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 140934 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 34491 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 175425 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6515506000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.452288 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.184051 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 116380 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 7780 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124160 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5006467500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.482523 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 2.937238 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40323.668210 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 140895 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 34518 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 175413 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 6516485500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.452397 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.183856 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 116399 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 7776 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124175 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 5007191500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.482619 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 2.935996 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 124160 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1807452 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 343469 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2150921 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52799.023345 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 3689312.055109 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 124175 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 1807450 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 343665 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2151115 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52801.925207 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3681603.345555 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40018.019200 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40018.264766 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1503148 # number of ReadReq hits -system.l2c.ReadReq_hits::1 339114 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1842262 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16066954000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.168361 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.012679 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 304304 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4355 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308659 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1503171 # number of ReadReq hits +system.l2c.ReadReq_hits::1 339301 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1842472 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16066517000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.168347 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.012698 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 304279 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4364 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308643 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12351281500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.170761 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.898605 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12350717000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.170753 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.898046 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 308643 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 840474000 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 607 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 600 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1207 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 4817.117117 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 4657.665505 # average SCUpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 308627 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 840465500 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 609 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 601 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1210 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 4879.928315 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 4727.430556 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40013.728964 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_hits::0 52 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 26 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_miss_latency 2673500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_rate::0 0.914333 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.956667 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 555 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 574 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1129 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 45175500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.859967 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.881667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40008.377425 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_hits::0 51 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 25 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 76 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_miss_latency 2723000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 0.916256 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.958403 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 558 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 576 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1134 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 45369500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.862069 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.886855 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 1129 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 2880 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 1625 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4505 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 5822.515585 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 12443.573668 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 1134 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 2885 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 1622 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4507 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 5855.677656 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 12557.737628 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.987260 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 153 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::0 155 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::1 349 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 502 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 15878000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.946875 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.785231 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 2727 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 1276 # number of UpgradeReq misses +system.l2c.UpgradeReq_hits::total 504 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 15986000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.946274 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.784834 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 2730 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 1273 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 4003 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 160188000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.389931 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.463385 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.387522 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.467941 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 4003 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1533346998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 810378 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 810378 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 810378 # number of Writeback hits -system.l2c.Writeback_hits::total 810378 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1532818498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 810405 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 810405 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 810405 # number of Writeback hits +system.l2c.Writeback_hits::total 810405 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.651210 # Average number of references to valid blocks. +system.l2c.avg_refs 5.657708 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2064766 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 385740 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2064744 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 385959 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2450506 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 53680.339637 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1860936.135146 # average overall miss latency +system.l2c.demand_accesses::total 2450703 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 53682.394848 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1860214.373970 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40105.426718 # average overall mshr miss latency -system.l2c.demand_hits::0 1644082 # number of demand (read+write) hits -system.l2c.demand_hits::1 373605 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40105.887912 # average overall mshr miss latency +system.l2c.demand_hits::0 1644066 # number of demand (read+write) hits +system.l2c.demand_hits::1 373819 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2017687 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22582460000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.203744 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.031459 # miss rate for demand accesses +system.l2c.demand_hits::total 2017885 # number of demand (read+write) hits +system.l2c.demand_miss_latency 22583002500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.203743 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.031454 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 420684 # number of demand (read+write) misses -system.l2c.demand_misses::1 12135 # number of demand (read+write) misses +system.l2c.demand_misses::0 420678 # number of demand (read+write) misses +system.l2c.demand_misses::1 12140 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 432819 # number of demand (read+write) misses +system.l2c.demand_misses::total 432818 # number of demand (read+write) misses system.l2c.demand_mshr_hits 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17357749000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.209614 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.122007 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 17357908500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.209615 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.121368 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 432803 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 432802 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.187928 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.005741 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.351843 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 12316.028373 # Average occupied blocks per context -system.l2c.occ_blocks::1 376.255092 # Average occupied blocks per context -system.l2c.occ_blocks::2 23058.373739 # Average occupied blocks per context -system.l2c.overall_accesses::0 2064766 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 385740 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.187715 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.005740 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.351851 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 12302.114841 # Average occupied blocks per context +system.l2c.occ_blocks::1 376.171902 # Average occupied blocks per context +system.l2c.occ_blocks::2 23058.891094 # Average occupied blocks per context +system.l2c.overall_accesses::0 2064744 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 385959 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2450506 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 53680.339637 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1860936.135146 # average overall miss latency +system.l2c.overall_accesses::total 2450703 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 53682.394848 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1860214.373970 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40105.426718 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40105.887912 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1644082 # number of overall hits -system.l2c.overall_hits::1 373605 # number of overall hits +system.l2c.overall_hits::0 1644066 # number of overall hits +system.l2c.overall_hits::1 373819 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2017687 # number of overall hits -system.l2c.overall_miss_latency 22582460000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.203744 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.031459 # miss rate for overall accesses +system.l2c.overall_hits::total 2017885 # number of overall hits +system.l2c.overall_miss_latency 22583002500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.203743 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.031454 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 420684 # number of overall misses -system.l2c.overall_misses::1 12135 # number of overall misses +system.l2c.overall_misses::0 420678 # number of overall misses +system.l2c.overall_misses::1 12140 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 432819 # number of overall misses +system.l2c.overall_misses::total 432818 # number of overall misses system.l2c.overall_mshr_hits 16 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17357749000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.209614 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.122007 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 17357908500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.209615 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.121368 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 432803 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2373820998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 432802 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2373283998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 395553 # number of replacements +system.l2c.replacements 395562 # number of replacements system.l2c.sampled_refs 431632 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 35750.657204 # Cycle average of tags in use -system.l2c.total_refs 2439243 # Total number of references to valid blocks. +system.l2c.tagsinuse 35737.177838 # Cycle average of tags in use +system.l2c.total_refs 2442048 # Total number of references to valid blocks. system.l2c.warmup_cycle 9270445000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 121365 # number of writebacks +system.l2c.writebacks 121361 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post |