diff options
Diffstat (limited to 'tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 2098 |
1 files changed, 1049 insertions, 1049 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index d4f86dcbd..d2a095e1d 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,133 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.897471 # Number of seconds simulated -sim_ticks 1897470973500 # Number of ticks simulated +sim_seconds 1.897465 # Number of seconds simulated +sim_ticks 1897465263500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112670 # Simulator instruction rate (inst/s) -host_tick_rate 3808310962 # Simulator tick rate (ticks/s) -host_mem_usage 344004 # Number of bytes of host memory used -host_seconds 498.24 # Real time elapsed on the host -sim_insts 56137023 # Number of instructions simulated -system.l2c.replacements 397425 # number of replacements -system.l2c.tagsinuse 35089.523512 # Cycle average of tags in use -system.l2c.total_refs 2483901 # Total number of references to valid blocks. -system.l2c.sampled_refs 433413 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.731026 # Average number of references to valid blocks. -system.l2c.warmup_cycle 9244135000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11999.654790 # Average occupied blocks per context -system.l2c.occ_blocks::1 233.124353 # Average occupied blocks per context -system.l2c.occ_blocks::2 22856.744369 # Average occupied blocks per context -system.l2c.occ_percent::0 0.183100 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.003557 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.348766 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1722706 # number of ReadReq hits -system.l2c.ReadReq_hits::1 146059 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1868765 # number of ReadReq hits -system.l2c.Writeback_hits::0 827102 # number of Writeback hits -system.l2c.Writeback_hits::total 827102 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 179 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 47 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 226 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 26 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 27 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 53 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 168351 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 11011 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179362 # number of ReadExReq hits -system.l2c.demand_hits::0 1891057 # number of demand (read+write) hits -system.l2c.demand_hits::1 157070 # number of demand (read+write) hits +host_inst_rate 131766 # Simulator instruction rate (inst/s) +host_tick_rate 4454253159 # Simulator tick rate (ticks/s) +host_mem_usage 298700 # Number of bytes of host memory used +host_seconds 425.99 # Real time elapsed on the host +sim_insts 56130966 # Number of instructions simulated +system.l2c.replacements 397795 # number of replacements +system.l2c.tagsinuse 35116.884908 # Cycle average of tags in use +system.l2c.total_refs 2482671 # Total number of references to valid blocks. +system.l2c.sampled_refs 433561 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.726232 # Average number of references to valid blocks. +system.l2c.warmup_cycle 9252063000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 12003.983788 # Average occupied blocks per context +system.l2c.occ_blocks::1 238.395777 # Average occupied blocks per context +system.l2c.occ_blocks::2 22874.505342 # Average occupied blocks per context +system.l2c.occ_percent::0 0.183166 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.003638 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.349037 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1719678 # number of ReadReq hits +system.l2c.ReadReq_hits::1 147350 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1867028 # number of ReadReq hits +system.l2c.Writeback_hits::0 826540 # number of Writeback hits +system.l2c.Writeback_hits::total 826540 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 172 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 46 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 28 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 28 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 168225 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 11091 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 179316 # number of ReadExReq hits +system.l2c.demand_hits::0 1887903 # number of demand (read+write) hits +system.l2c.demand_hits::1 158441 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2048127 # number of demand (read+write) hits -system.l2c.overall_hits::0 1891057 # number of overall hits -system.l2c.overall_hits::1 157070 # number of overall hits +system.l2c.demand_hits::total 2046344 # number of demand (read+write) hits +system.l2c.overall_hits::0 1887903 # number of overall hits +system.l2c.overall_hits::1 158441 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2048127 # number of overall hits -system.l2c.ReadReq_misses::0 305325 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4048 # number of ReadReq misses -system.l2c.ReadReq_misses::total 309373 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 2451 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 556 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3007 # number of UpgradeReq misses +system.l2c.overall_hits::total 2046344 # number of overall hits +system.l2c.ReadReq_misses::0 305537 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4057 # number of ReadReq misses +system.l2c.ReadReq_misses::total 309594 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 2453 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 560 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3013 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::0 48 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 82 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 130 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 113992 # number of ReadExReq misses +system.l2c.SCUpgradeReq_misses::1 84 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 132 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 113925 # number of ReadExReq misses system.l2c.ReadExReq_misses::1 10735 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124727 # number of ReadExReq misses -system.l2c.demand_misses::0 419317 # number of demand (read+write) misses -system.l2c.demand_misses::1 14783 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::total 124660 # number of ReadExReq misses +system.l2c.demand_misses::0 419462 # number of demand (read+write) misses +system.l2c.demand_misses::1 14792 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 434100 # number of demand (read+write) misses -system.l2c.overall_misses::0 419317 # number of overall misses -system.l2c.overall_misses::1 14783 # number of overall misses +system.l2c.demand_misses::total 434254 # number of demand (read+write) misses +system.l2c.overall_misses::0 419462 # number of overall misses +system.l2c.overall_misses::1 14792 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 434100 # number of overall misses -system.l2c.ReadReq_miss_latency 16104881500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 3975000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 681000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6543645500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22648527000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22648527000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2028031 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 150107 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2178138 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 827102 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 827102 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2630 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 603 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3233 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 74 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 109 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 183 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 282343 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 21746 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304089 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2310374 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 171853 # number of demand (read+write) accesses +system.l2c.overall_misses::total 434254 # number of overall misses +system.l2c.ReadReq_miss_latency 16116451000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 3978500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 680500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6538718500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22655169500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22655169500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2025215 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 151407 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2176622 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 826540 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 826540 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 2625 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 606 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3231 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 76 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 112 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 282150 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 21826 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 303976 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2307365 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 173233 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2482227 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2310374 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 171853 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2480598 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2307365 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 173233 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2482227 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.150552 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.026967 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.931939 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.922056 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.648649 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.752294 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.403736 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.493654 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.181493 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.086021 # miss rate for demand accesses +system.l2c.overall_accesses::total 2480598 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.150866 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.026795 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.934476 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.924092 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.631579 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.750000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.403775 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.491845 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.181793 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.085388 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.181493 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.086021 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.181793 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.085388 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52746.684680 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 3978478.631423 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52747.951967 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3972504.560020 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 1621.787026 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 7149.280576 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 1621.891561 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 7104.464286 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 14187.500000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 8304.878049 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 14177.083333 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 8101.190476 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 57404.427504 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 609561.760596 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 57394.939653 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 609102.794597 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 54012.899549 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1532065.683555 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 54010.064082 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1531582.578421 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 54012.899549 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1532065.683555 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 54010.064082 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1531582.578421 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -138,100 +138,100 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 122219 # number of writebacks -system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 309356 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3007 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 130 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 124727 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 434083 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 434083 # number of overall MSHR misses +system.l2c.writebacks 122051 # number of writebacks +system.l2c.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 18 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 18 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 309576 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3013 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 132 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 124660 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 434236 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 434236 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12384389500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 120345500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 5200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5026892500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17411282000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17411282000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 838237000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1420706998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 2258943998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.152540 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.060903 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12393243000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 120589000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 5280000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5022395000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17415638000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17415638000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 838122500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1421433998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 2259556498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.152861 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.044661 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.143346 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 4.986733 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.147810 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4.971947 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.756757 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.192661 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.736842 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.178571 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.441757 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 5.735630 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.441822 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 5.711537 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.187884 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 2.525897 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.188196 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 2.506659 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.187884 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 2.525897 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.188196 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 2.506659 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40032.808480 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40021.782507 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40032.957981 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40022.900763 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40303.162106 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40110.490390 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40110.490390 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40288.745387 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40106.389152 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40106.389152 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41699 # number of replacements -system.iocache.tagsinuse 0.463134 # Cycle average of tags in use +system.iocache.replacements 41697 # number of replacements +system.iocache.tagsinuse 0.463240 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41715 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1709323096000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.463134 # Average occupied blocks per context -system.iocache.occ_percent::1 0.028946 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1709322874000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.463240 # Average occupied blocks per context +system.iocache.occ_percent::1 0.028953 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 179 # number of ReadReq misses -system.iocache.ReadReq_misses::total 179 # number of ReadReq misses +system.iocache.ReadReq_misses::1 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41731 # number of demand (read+write) misses -system.iocache.demand_misses::total 41731 # number of demand (read+write) misses +system.iocache.demand_misses::1 41729 # number of demand (read+write) misses +system.iocache.demand_misses::total 41729 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41731 # number of overall misses -system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_miss_latency 20616998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5721081806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5741698804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5741698804 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 179 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) +system.iocache.overall_misses::1 41729 # number of overall misses +system.iocache.overall_misses::total 41729 # number of overall misses +system.iocache.ReadReq_miss_latency 20390998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5721236806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5741627804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5741627804 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41731 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41731 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -241,37 +241,37 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115178.759777 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115203.378531 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137684.872112 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137688.602378 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137588.334907 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137593.227827 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137588.334907 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137593.227827 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64637068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64620068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6180.633773 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6179.008223 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks 41520 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 179 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 41731 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 41731 # number of overall MSHR misses +system.iocache.demand_mshr_misses 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 41729 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 11308998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3560223994 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3571532992 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3571532992 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 11186998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3560378000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571564998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571564998 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -285,10 +285,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63178.759777 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85681.170437 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85584.649110 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85584.649110 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63203.378531 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85684.876781 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85589.518033 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85589.518033 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -309,22 +309,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9537119 # DTB read hits -system.cpu0.dtb.read_misses 35694 # DTB read misses -system.cpu0.dtb.read_acv 589 # DTB read access violations -system.cpu0.dtb.read_accesses 644456 # DTB read accesses -system.cpu0.dtb.write_hits 6201700 # DTB write hits -system.cpu0.dtb.write_misses 7404 # DTB write misses -system.cpu0.dtb.write_acv 340 # DTB write access violations -system.cpu0.dtb.write_accesses 219479 # DTB write accesses -system.cpu0.dtb.data_hits 15738819 # DTB hits -system.cpu0.dtb.data_misses 43098 # DTB misses -system.cpu0.dtb.data_acv 929 # DTB access violations -system.cpu0.dtb.data_accesses 863935 # DTB accesses -system.cpu0.itb.fetch_hits 1065001 # ITB hits -system.cpu0.itb.fetch_misses 28395 # ITB misses -system.cpu0.itb.fetch_acv 959 # ITB acv -system.cpu0.itb.fetch_accesses 1093396 # ITB accesses +system.cpu0.dtb.read_hits 9507417 # DTB read hits +system.cpu0.dtb.read_misses 35968 # DTB read misses +system.cpu0.dtb.read_acv 598 # DTB read access violations +system.cpu0.dtb.read_accesses 640032 # DTB read accesses +system.cpu0.dtb.write_hits 6191307 # DTB write hits +system.cpu0.dtb.write_misses 8160 # DTB write misses +system.cpu0.dtb.write_acv 353 # DTB write access violations +system.cpu0.dtb.write_accesses 218604 # DTB write accesses +system.cpu0.dtb.data_hits 15698724 # DTB hits +system.cpu0.dtb.data_misses 44128 # DTB misses +system.cpu0.dtb.data_acv 951 # DTB access violations +system.cpu0.dtb.data_accesses 858636 # DTB accesses +system.cpu0.itb.fetch_hits 1059111 # ITB hits +system.cpu0.itb.fetch_misses 28345 # ITB misses +system.cpu0.itb.fetch_acv 951 # ITB acv +system.cpu0.itb.fetch_accesses 1087456 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -337,147 +337,147 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 112251413 # number of cpu cycles simulated +system.cpu0.numCycles 112078637 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13715156 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11502951 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 484161 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 12377728 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 6363664 # Number of BTB hits +system.cpu0.BPredUnit.lookups 13676513 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 11471993 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 481224 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 12342117 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 6355141 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 918279 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 37972 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 28099564 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 69844028 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13715156 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 7281943 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 13538078 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2172072 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 34812736 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 29955 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 193219 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 330912 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 98 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8567969 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 303515 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 78411579 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.890736 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.207630 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 915334 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 37832 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 28007609 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 69419364 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13676513 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 7270475 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 13464854 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2130456 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 34838342 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 29311 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 192876 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 330870 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8508842 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 295697 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 78241728 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.887242 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.203788 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64873501 82.73% 82.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 956509 1.22% 83.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1906420 2.43% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 900643 1.15% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2836490 3.62% 91.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 653196 0.83% 91.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 748865 0.96% 92.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1020020 1.30% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4515935 5.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64776874 82.79% 82.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 958993 1.23% 84.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1895458 2.42% 86.44% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 896557 1.15% 87.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2826529 3.61% 91.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 644193 0.82% 92.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 736181 0.94% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1019927 1.30% 94.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4487016 5.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 78411579 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.122182 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.622211 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 29218734 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 34518564 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 12397503 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 907653 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1369124 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 565623 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 38130 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 68326357 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 115471 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1369124 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 30359966 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12420002 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18653448 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 11559609 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4049428 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 64489639 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6675 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 459269 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1452522 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 43185187 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 78281955 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 77849999 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 431956 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36504578 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 6680601 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1578071 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 238750 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11394232 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10044360 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6546770 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1193752 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 777018 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 56531127 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2009866 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 55005856 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 111558 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7605242 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3895552 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1371310 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 78411579 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.701502 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.348295 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 78241728 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.122026 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.619381 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 29114965 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34547748 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 12317154 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 921824 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1340036 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 563514 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 37992 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 67952438 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 114909 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1340036 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 30246504 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12447336 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18631420 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 11494424 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4082006 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 64196257 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6719 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 464674 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1470831 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 42946380 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 77900777 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 77469173 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 431604 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36477108 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 6469264 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1576496 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 238440 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11483101 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10008373 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6527102 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1185571 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 771360 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 56320474 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2007436 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 54875963 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 110266 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7429207 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3754226 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1369428 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 78241728 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.701364 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.347589 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54224531 69.15% 69.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10651966 13.58% 82.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 5211873 6.65% 89.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3322855 4.24% 93.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2518388 3.21% 96.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1465679 1.87% 98.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 653633 0.83% 99.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 263398 0.34% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 99256 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54100520 69.15% 69.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10639232 13.60% 82.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 5191485 6.64% 89.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3321136 4.24% 93.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2520069 3.22% 96.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1468713 1.88% 98.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 637402 0.81% 99.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 263268 0.34% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 99903 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 78411579 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 78241728 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 63058 8.97% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 343865 48.92% 57.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 295935 42.10% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 61581 8.74% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 342929 48.66% 57.40% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 300261 42.60% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3328 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37799296 68.72% 68.72% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60344 0.11% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15686 0.03% 68.86% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.86% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.86% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.86% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3329 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37711302 68.72% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60327 0.11% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15682 0.03% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.87% # Type of FU issued @@ -500,112 +500,112 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.87% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9967542 18.12% 86.99% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6280275 11.42% 98.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 877731 1.60% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9937545 18.11% 86.98% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6268980 11.42% 98.40% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 877144 1.60% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 55005856 # Type of FU issued -system.cpu0.iq.rate 0.490024 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 702858 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012778 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 188615716 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65871549 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53572345 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 621990 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 297473 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 294666 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 55378554 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 326832 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 547956 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 54875963 # Type of FU issued +system.cpu0.iq.rate 0.489620 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 704772 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012843 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 188187092 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65472775 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53463452 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 621599 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 297101 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 294471 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 55250754 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 326652 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 544032 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1439562 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 14656 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 23453 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 541104 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1411765 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 14119 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13054 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 526523 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18437 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 167543 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 19033 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 166880 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1369124 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8683441 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 605421 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 62052001 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 831027 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10044360 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6546770 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1774362 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 483184 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 10442 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 23453 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 350905 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 357470 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 708375 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 54360123 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9599991 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 645732 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1340036 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8692237 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 606269 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 61830785 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 830784 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10008373 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6527102 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1772467 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 482817 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 10549 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13054 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 346528 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 358003 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 704531 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 54241616 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9570533 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 634346 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3511008 # number of nop insts executed -system.cpu0.iew.exec_refs 15823517 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8665836 # Number of branches executed -system.cpu0.iew.exec_stores 6223526 # Number of stores executed -system.cpu0.iew.exec_rate 0.484271 # Inst execution rate -system.cpu0.iew.wb_sent 53987864 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53867011 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26614200 # num instructions producing a value -system.cpu0.iew.wb_consumers 35806994 # num instructions consuming a value +system.cpu0.iew.exec_nop 3502875 # number of nop insts executed +system.cpu0.iew.exec_refs 15784325 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8657029 # Number of branches executed +system.cpu0.iew.exec_stores 6213792 # Number of stores executed +system.cpu0.iew.exec_rate 0.483960 # Inst execution rate +system.cpu0.iew.wb_sent 53872827 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 53757923 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26542591 # num instructions producing a value +system.cpu0.iew.wb_consumers 35724968 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.479878 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.743268 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.479645 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742970 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 53695815 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 8260876 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638556 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 645745 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 77042455 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.696964 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.608185 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 53656716 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 8078010 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638008 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 642783 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 76901692 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.697731 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.609209 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 56792844 73.72% 73.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8505609 11.04% 84.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4528626 5.88% 90.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2490278 3.23% 93.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1477167 1.92% 95.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 617055 0.80% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 444256 0.58% 97.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 490319 0.64% 97.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1696301 2.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 56673915 73.70% 73.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8488315 11.04% 84.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4528829 5.89% 90.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2497024 3.25% 93.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1465718 1.91% 95.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 614414 0.80% 96.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 447034 0.58% 97.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 489019 0.64% 97.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1697424 2.21% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 77042455 # Number of insts commited each cycle -system.cpu0.commit.count 53695815 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 76901692 # Number of insts commited each cycle +system.cpu0.commit.count 53656716 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14610464 # Number of memory references committed -system.cpu0.commit.loads 8604798 # Number of loads committed -system.cpu0.commit.membars 217772 # Number of memory barriers committed -system.cpu0.commit.branches 8097271 # Number of branches committed -system.cpu0.commit.fp_insts 292136 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49674100 # Number of committed integer instructions. -system.cpu0.commit.function_calls 705369 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1696301 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14597187 # Number of memory references committed +system.cpu0.commit.loads 8596608 # Number of loads committed +system.cpu0.commit.membars 217615 # Number of memory barriers committed +system.cpu0.commit.branches 8092300 # Number of branches committed +system.cpu0.commit.fp_insts 291990 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 49637924 # Number of committed integer instructions. +system.cpu0.commit.function_calls 704482 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1697424 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 137112360 # The number of ROB reads -system.cpu0.rob.rob_writes 125284104 # The number of ROB writes -system.cpu0.timesIdled 1232970 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 33839834 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 50579161 # Number of Instructions Simulated -system.cpu0.committedInsts_total 50579161 # Number of Instructions Simulated -system.cpu0.cpi 2.219321 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.219321 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.450588 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.450588 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 71273377 # number of integer regfile reads -system.cpu0.int_regfile_writes 38974201 # number of integer regfile writes -system.cpu0.fp_regfile_reads 144005 # number of floating regfile reads -system.cpu0.fp_regfile_writes 146400 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1864820 # number of misc regfile reads -system.cpu0.misc_regfile_writes 888952 # number of misc regfile writes +system.cpu0.rob.rob_reads 136748495 # The number of ROB reads +system.cpu0.rob.rob_writes 124811050 # The number of ROB writes +system.cpu0.timesIdled 1231942 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 33836909 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 50542242 # Number of Instructions Simulated +system.cpu0.committedInsts_total 50542242 # Number of Instructions Simulated +system.cpu0.cpi 2.217524 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.217524 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.450953 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.450953 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 71124780 # number of integer regfile reads +system.cpu0.int_regfile_writes 38876207 # number of integer regfile writes +system.cpu0.fp_regfile_reads 143910 # number of floating regfile reads +system.cpu0.fp_regfile_writes 146325 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1863327 # number of misc regfile reads +system.cpu0.misc_regfile_writes 888204 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -637,233 +637,233 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 972255 # number of replacements -system.cpu0.icache.tagsinuse 509.997473 # Cycle average of tags in use -system.cpu0.icache.total_refs 7540990 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 972767 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.752103 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23351428000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 509.997473 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.996089 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 7540990 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7540990 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 7540990 # number of demand (read+write) hits +system.cpu0.icache.replacements 970482 # number of replacements +system.cpu0.icache.tagsinuse 510.008508 # Cycle average of tags in use +system.cpu0.icache.total_refs 7483994 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 970994 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.707559 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23358720000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 510.008508 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.996110 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::0 7483994 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7483994 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 7483994 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7540990 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 7540990 # number of overall hits +system.cpu0.icache.demand_hits::total 7483994 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 7483994 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 7540990 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 1026979 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1026979 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 1026979 # number of demand (read+write) misses +system.cpu0.icache.overall_hits::total 7483994 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 1024848 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1024848 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 1024848 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1026979 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 1026979 # number of overall misses +system.cpu0.icache.demand_misses::total 1024848 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 1024848 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 1026979 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 15345865496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 15345865496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 15345865496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 8567969 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8567969 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 8567969 # number of demand (read+write) accesses +system.cpu0.icache.overall_misses::total 1024848 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 15319794498 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 15319794498 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 15319794498 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 8508842 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8508842 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 8508842 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8567969 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 8567969 # number of overall (read+write) accesses +system.cpu0.icache.demand_accesses::total 8508842 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 8508842 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8567969 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.119863 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.119863 # miss rate for demand accesses +system.cpu0.icache.overall_accesses::total 8508842 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.120445 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.120445 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.119863 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::0 0.120445 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14942.725699 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::0 14948.357706 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14942.725699 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::0 14948.357706 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14942.725699 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 14948.357706 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1169997 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 1225998 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 101 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 103 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11584.128713 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11902.893204 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 201 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 54044 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 54044 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 54044 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 972935 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 972935 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 972935 # number of overall MSHR misses +system.cpu0.icache.writebacks 218 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 53716 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 53716 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 53716 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 971132 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 971132 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 971132 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 11633224497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 11633224497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 11633224497 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 11617050998 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 11617050998 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 11617050998 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.113555 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.114132 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.113555 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.114132 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.113555 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.114132 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11956.836271 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11956.836271 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11956.836271 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11962.381013 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11962.381013 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11962.381013 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1341445 # number of replacements -system.cpu0.dcache.tagsinuse 503.508011 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11371142 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1341956 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.473558 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1339905 # number of replacements +system.cpu0.dcache.tagsinuse 503.729057 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11343106 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1340416 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.462377 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 504.508011 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 504.729057 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.985367 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::0 0.985799 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7002154 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7002154 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 3971242 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3971242 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 182799 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 182799 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 208802 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208802 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 10973396 # number of demand (read+write) hits +system.cpu0.dcache.ReadReq_hits::0 6978274 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6978274 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::0 3967577 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3967577 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 182488 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 182488 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::0 208558 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 208558 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::0 10945851 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10973396 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 10973396 # number of overall hits +system.cpu0.dcache.demand_hits::total 10945851 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::0 10945851 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 10973396 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 1698188 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1698188 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 1810110 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1810110 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 21696 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21696 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 665 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 665 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 3508298 # number of demand (read+write) misses +system.cpu0.dcache.overall_hits::total 10945851 # number of overall hits +system.cpu0.dcache.ReadReq_misses::0 1696520 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1696520 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::0 1808915 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1808915 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::0 21731 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21731 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::0 693 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 693 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::0 3505435 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3508298 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 3508298 # number of overall misses +system.cpu0.dcache.demand_misses::total 3505435 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::0 3505435 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 3508298 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 37024597500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 55205693695 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 326548500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 6352500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 92230291195 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 92230291195 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8700342 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8700342 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 5781352 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5781352 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 204495 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 204495 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 209467 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 209467 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14481694 # number of demand (read+write) accesses +system.cpu0.dcache.overall_misses::total 3505435 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 37036233000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 55166183811 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency 327139500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 6516000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency 92202416811 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 92202416811 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 8674794 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8674794 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 5776492 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5776492 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 204219 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 204219 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 209251 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 209251 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 14451286 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14481694 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14481694 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14451286 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 14451286 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14481694 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.195186 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.313095 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106096 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003175 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.242257 # miss rate for demand accesses +system.cpu0.dcache.overall_accesses::total 14451286 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.195569 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.313151 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106410 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003312 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.242569 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.242257 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.242569 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 21802.413808 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 21830.708156 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 30498.529755 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 30496.835844 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15051.092367 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15054.047214 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9552.631579 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9402.597403 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 26289.183871 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 26302.703320 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 26289.183871 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 26302.703320 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 889959290 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 98831 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9004.859710 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 886352311 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 210500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 100011 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8862.548230 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 23388.888889 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 791115 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 651520 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1525368 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 4914 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 2176888 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 2176888 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 1046668 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 284742 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16782 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 665 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 1331410 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 1331410 # number of overall MSHR misses +system.cpu0.dcache.writebacks 790429 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 651194 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1524352 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 4898 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 2175546 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 2175546 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 1045326 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 284563 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 16833 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 693 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 1329889 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 1329889 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 24224955000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 8301968289 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 194959000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 4349000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 32526923289 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 32526923289 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 917419500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1254211998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 2171631498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.120302 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 24217800500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 8294565311 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 195726500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 4430000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 32512365811 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 32512365811 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 916795000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1253240498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 2170035498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.120502 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049252 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049262 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.082066 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.082426 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.003175 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.003312 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.091937 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.092026 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.091937 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.092026 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23144.831981 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29156.107244 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11617.149327 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6539.849624 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 24430.433367 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 24430.433367 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23167.701272 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29148.432196 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11627.547080 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6392.496392 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 24447.428177 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 24447.428177 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -874,22 +874,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1324275 # DTB read hits -system.cpu1.dtb.read_misses 10298 # DTB read misses +system.cpu1.dtb.read_hits 1326048 # DTB read hits +system.cpu1.dtb.read_misses 10245 # DTB read misses system.cpu1.dtb.read_acv 4 # DTB read access violations -system.cpu1.dtb.read_accesses 333543 # DTB read accesses -system.cpu1.dtb.write_hits 770562 # DTB write hits -system.cpu1.dtb.write_misses 3363 # DTB write misses -system.cpu1.dtb.write_acv 49 # DTB write access violations -system.cpu1.dtb.write_accesses 128416 # DTB write accesses -system.cpu1.dtb.data_hits 2094837 # DTB hits -system.cpu1.dtb.data_misses 13661 # DTB misses -system.cpu1.dtb.data_acv 53 # DTB access violations -system.cpu1.dtb.data_accesses 461959 # DTB accesses -system.cpu1.itb.fetch_hits 370005 # ITB hits -system.cpu1.itb.fetch_misses 7545 # ITB misses -system.cpu1.itb.fetch_acv 134 # ITB acv -system.cpu1.itb.fetch_accesses 377550 # ITB accesses +system.cpu1.dtb.read_accesses 331667 # DTB read accesses +system.cpu1.dtb.write_hits 775032 # DTB write hits +system.cpu1.dtb.write_misses 3356 # DTB write misses +system.cpu1.dtb.write_acv 50 # DTB write access violations +system.cpu1.dtb.write_accesses 128144 # DTB write accesses +system.cpu1.dtb.data_hits 2101080 # DTB hits +system.cpu1.dtb.data_misses 13601 # DTB misses +system.cpu1.dtb.data_acv 54 # DTB access violations +system.cpu1.dtb.data_accesses 459811 # DTB accesses +system.cpu1.itb.fetch_hits 367550 # ITB hits +system.cpu1.itb.fetch_misses 7752 # ITB misses +system.cpu1.itb.fetch_acv 129 # ITB acv +system.cpu1.itb.fetch_accesses 375302 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -902,500 +902,500 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 9912659 # number of cpu cycles simulated +system.cpu1.numCycles 9966962 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1745252 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1443345 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 65834 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 1584413 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 702878 # Number of BTB hits +system.cpu1.BPredUnit.lookups 1746608 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 1443175 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 66232 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 1579747 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 700902 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 119333 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 5152 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3326193 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 8368967 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1745252 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 822211 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1597560 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 342353 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 3930227 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65364 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 47873 # Number of stall cycles due to pending quiesce instructions +system.cpu1.BPredUnit.usedRAS 120007 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 5197 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 3352188 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 8389538 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1746608 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 820909 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1600088 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 340649 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 3953742 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24318 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65300 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 48169 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1048710 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 37506 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 9217508 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.907942 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.250031 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 1052111 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 37387 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 9268453 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.905171 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.248228 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 7619948 82.67% 82.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 115536 1.25% 83.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 231432 2.51% 86.43% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 132066 1.43% 87.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 251396 2.73% 90.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 87805 0.95% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 105965 1.15% 92.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 72910 0.79% 93.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 600450 6.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 7668365 82.74% 82.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 115994 1.25% 83.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 231226 2.49% 86.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 132329 1.43% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 251751 2.72% 90.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 85931 0.93% 91.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 105894 1.14% 92.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 73622 0.79% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 603341 6.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 9217508 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.176063 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.844271 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3400940 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 4036286 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1484850 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 73785 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 221646 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 74292 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4556 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 8102747 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 13778 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 221646 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3537754 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 421646 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3194279 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1408453 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 433728 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 7527296 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 85 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 45933 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 92379 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 5035349 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 9221754 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 9169185 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52569 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 3992895 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1042454 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 304748 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 22314 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1288706 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1415531 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 837109 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 144169 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 91214 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 6583258 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 323533 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6259296 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 22632 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1284449 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 724409 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 248666 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 9217508 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.679066 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.329101 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 9268453 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.175240 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.841735 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3426888 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 4059985 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1487039 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 74425 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 220115 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 74752 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4586 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 8123817 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 13801 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 220115 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3563676 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 426586 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3211249 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1411283 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 435542 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 7548530 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 102 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 46052 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 92764 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 5048861 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 9245845 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 9192898 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52947 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 4017246 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1031615 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 305905 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 22528 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1292369 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1416426 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 841512 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 141179 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 90021 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 6602199 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 325316 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 6284355 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 22621 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1273450 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 716539 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 249793 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 9268453 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.678037 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.328780 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 6458729 70.07% 70.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1222372 13.26% 83.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 577704 6.27% 89.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 392327 4.26% 93.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 292985 3.18% 97.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 159359 1.73% 98.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 73107 0.79% 99.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 30242 0.33% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10683 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 6498051 70.11% 70.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1227525 13.24% 83.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 582679 6.29% 89.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 391581 4.22% 93.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 294983 3.18% 97.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 158395 1.71% 98.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 72456 0.78% 99.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 32178 0.35% 99.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10605 0.11% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 9217508 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 9268453 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2814 1.95% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 81545 56.44% 58.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 60126 41.61% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2859 1.97% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 82047 56.45% 58.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 60446 41.59% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3976 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3873185 61.88% 61.94% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10062 0.16% 62.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10067 0.16% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1379075 22.03% 84.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 790293 12.63% 96.95% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 190650 3.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3978 0.06% 0.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3890788 61.91% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10226 0.16% 62.14% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10071 0.16% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1381194 21.98% 84.31% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 794695 12.65% 96.95% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 191415 3.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6259296 # Type of FU issued -system.cpu1.iq.rate 0.631445 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 144485 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.023083 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 21824812 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 8155075 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 6057514 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 78405 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 38858 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 37639 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6359227 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 40578 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 60856 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 6284355 # Type of FU issued +system.cpu1.iq.rate 0.630519 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 145352 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.023129 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 21926150 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 8163461 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 6082297 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 78986 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 39141 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 37853 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 6384800 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 40929 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 61528 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 266775 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6711 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3171 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 114531 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 262809 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6760 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1750 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 113415 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 348 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 21986 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 366 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 22210 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 221646 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 305727 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 11882 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7168806 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98535 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1415531 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 837109 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 301857 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4025 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4971 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3171 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 47886 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 59778 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 107664 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6180810 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1338159 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 78486 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 220115 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 309272 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 12037 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 7192077 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 99271 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1416426 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 841512 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 303434 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 3996 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4977 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1750 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 48213 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 60062 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 108275 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 6205529 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1339876 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 78826 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 262015 # number of nop insts executed -system.cpu1.iew.exec_refs 2115427 # number of memory reference insts executed -system.cpu1.iew.exec_branches 905329 # Number of branches executed -system.cpu1.iew.exec_stores 777268 # Number of stores executed -system.cpu1.iew.exec_rate 0.623527 # Inst execution rate -system.cpu1.iew.wb_sent 6122723 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6095153 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2947422 # num instructions producing a value -system.cpu1.iew.wb_consumers 4027218 # num instructions consuming a value +system.cpu1.iew.exec_nop 264562 # number of nop insts executed +system.cpu1.iew.exec_refs 2121617 # number of memory reference insts executed +system.cpu1.iew.exec_branches 906286 # Number of branches executed +system.cpu1.iew.exec_stores 781741 # Number of stores executed +system.cpu1.iew.exec_rate 0.622610 # Inst execution rate +system.cpu1.iew.wb_sent 6147670 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 6120150 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2958458 # num instructions producing a value +system.cpu1.iew.wb_consumers 4045224 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.614886 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.731875 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.614044 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.731346 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 5779093 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1316908 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 74867 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 99712 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 8995862 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.642417 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.546372 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 5812223 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1307029 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 75523 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 100285 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 9048338 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.642353 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.547343 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 6736606 74.89% 74.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1094915 12.17% 87.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 391523 4.35% 91.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 242834 2.70% 94.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 155077 1.72% 95.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 75617 0.84% 96.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 76298 0.85% 97.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 67487 0.75% 98.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 155505 1.73% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 6777327 74.90% 74.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1099919 12.16% 87.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 394591 4.36% 91.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 244546 2.70% 94.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 155405 1.72% 95.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 74689 0.83% 96.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 76341 0.84% 97.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 67787 0.75% 98.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 157733 1.74% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 8995862 # Number of insts commited each cycle -system.cpu1.commit.count 5779093 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 9048338 # Number of insts commited each cycle +system.cpu1.commit.count 5812223 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1871334 # Number of memory references committed -system.cpu1.commit.loads 1148756 # Number of loads committed -system.cpu1.commit.membars 20308 # Number of memory barriers committed -system.cpu1.commit.branches 819762 # Number of branches committed -system.cpu1.commit.fp_insts 36255 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5407958 # Number of committed integer instructions. -system.cpu1.commit.function_calls 88494 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 155505 # number cycles where commit BW limit reached +system.cpu1.commit.refs 1881714 # Number of memory references committed +system.cpu1.commit.loads 1153617 # Number of loads committed +system.cpu1.commit.membars 20508 # Number of memory barriers committed +system.cpu1.commit.branches 821256 # Number of branches committed +system.cpu1.commit.fp_insts 36401 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 5437919 # Number of committed integer instructions. +system.cpu1.commit.function_calls 89388 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 157733 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 15845699 # The number of ROB reads -system.cpu1.rob.rob_writes 14412433 # The number of ROB writes -system.cpu1.timesIdled 81222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 695151 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 5557862 # Number of Instructions Simulated -system.cpu1.committedInsts_total 5557862 # Number of Instructions Simulated -system.cpu1.cpi 1.783538 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.783538 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.560683 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.560683 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 8056762 # number of integer regfile reads -system.cpu1.int_regfile_writes 4390923 # number of integer regfile writes -system.cpu1.fp_regfile_reads 24497 # number of floating regfile reads -system.cpu1.fp_regfile_writes 23023 # number of floating regfile writes -system.cpu1.misc_regfile_reads 283037 # number of misc regfile reads -system.cpu1.misc_regfile_writes 133939 # number of misc regfile writes -system.cpu1.icache.replacements 109497 # number of replacements -system.cpu1.icache.tagsinuse 452.896457 # Cycle average of tags in use -system.cpu1.icache.total_refs 933398 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 110009 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.484742 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1874842259000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 452.896457 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.884563 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 933398 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 933398 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 933398 # number of demand (read+write) hits +system.cpu1.rob.rob_reads 15919184 # The number of ROB reads +system.cpu1.rob.rob_writes 14457399 # The number of ROB writes +system.cpu1.timesIdled 81947 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 698509 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 5588724 # Number of Instructions Simulated +system.cpu1.committedInsts_total 5588724 # Number of Instructions Simulated +system.cpu1.cpi 1.783406 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.783406 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.560725 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.560725 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 8091693 # number of integer regfile reads +system.cpu1.int_regfile_writes 4410635 # number of integer regfile writes +system.cpu1.fp_regfile_reads 24636 # number of floating regfile reads +system.cpu1.fp_regfile_writes 23087 # number of floating regfile writes +system.cpu1.misc_regfile_reads 284786 # number of misc regfile reads +system.cpu1.misc_regfile_writes 134830 # number of misc regfile writes +system.cpu1.icache.replacements 110610 # number of replacements +system.cpu1.icache.tagsinuse 452.934793 # Cycle average of tags in use +system.cpu1.icache.total_refs 935676 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 111121 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.420335 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1874818206000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 452.934793 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.884638 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::0 935676 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 935676 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 935676 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 933398 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 933398 # number of overall hits +system.cpu1.icache.demand_hits::total 935676 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 935676 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 933398 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 115312 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 115312 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 115312 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 935676 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 116435 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 116435 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 116435 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 115312 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 115312 # number of overall misses +system.cpu1.icache.demand_misses::total 116435 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 116435 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 115312 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 1734763499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 1734763499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 1734763499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 1048710 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1048710 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 1048710 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 116435 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 1751730499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 1751730499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 1751730499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 1052111 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1052111 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 1052111 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1048710 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 1048710 # number of overall (read+write) accesses +system.cpu1.icache.demand_accesses::total 1052111 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 1052111 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1048710 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.109956 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.109956 # miss rate for demand accesses +system.cpu1.icache.overall_accesses::total 1052111 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.110668 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.110668 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.109956 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.110668 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 15044.084735 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 15044.707339 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 15044.084735 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 15044.707339 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 15044.084735 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 15044.707339 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 115999 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 93999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6444.388889 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7230.692308 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 32 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 5233 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 5233 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 5233 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 110079 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 110079 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 110079 # number of overall MSHR misses +system.cpu1.icache.writebacks 37 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 5243 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 5243 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 5243 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 111192 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 111192 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 111192 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1320813499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 1320813499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 1320813499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 1333669999 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 1333669999 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 1333669999 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.104966 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.105685 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.104966 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.105685 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.104966 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.105685 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11998.778141 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11998.778141 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11998.778141 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11994.298142 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11994.298142 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11994.298142 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62178 # number of replacements -system.cpu1.dcache.tagsinuse 392.683341 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1692677 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62506 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 27.080232 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1874637412500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 392.683341 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.766960 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 1125457 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1125457 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 544800 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 544800 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 16569 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 16569 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 14697 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 14697 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 1670257 # number of demand (read+write) hits +system.cpu1.dcache.replacements 62429 # number of replacements +system.cpu1.dcache.tagsinuse 392.995073 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1698421 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62755 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 27.064314 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1874613639500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::0 392.995073 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.767569 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::0 1125916 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1125916 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::0 549554 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 549554 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 16796 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 16796 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::0 14923 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 14923 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::0 1675470 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1670257 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 1670257 # number of overall hits +system.cpu1.dcache.demand_hits::total 1675470 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 1675470 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 1670257 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 106593 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 106593 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 157299 # 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number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 8230500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 6939608762 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 6939608762 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 1232050 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1232050 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 702099 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 702099 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 18040 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 18040 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 15385 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 15385 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 1934149 # number of demand (read+write) accesses +system.cpu1.dcache.overall_misses::total 264505 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 1790096000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 5171682833 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 19414000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 8395500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 6961778833 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 6961778833 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 1232610 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1232610 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 707365 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 707365 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 18276 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 18276 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 15623 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 15623 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 1939975 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1934149 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 1934149 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1939975 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 1939975 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1934149 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.086517 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.224041 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.081541 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044719 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.136438 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 1939975 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.086559 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.223097 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.080981 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044806 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.136345 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.136438 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.136345 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 16690.725470 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 16777.850676 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 32806.910800 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 32771.371026 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13181.509177 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13117.567568 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 11962.936047 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 11993.571429 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 26297.154753 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 26320.027345 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 26297.154753 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 26320.027345 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 86924497 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 86579997 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6880 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6823 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12634.374564 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12689.432361 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 35754 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 63001 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 133631 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 299 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 196632 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 196632 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 43592 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 23668 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 1172 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 688 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 67260 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 67260 # number of overall MSHR misses +system.cpu1.dcache.writebacks 35856 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 62883 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 134026 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 295 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 196909 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 196909 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 43811 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 23785 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 1185 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 699 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 67596 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 67596 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 554109500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 750522486 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11597500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 6158000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 1304631986 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 1304631986 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 18620500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 319072500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 337693000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035382 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 556154000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 752491985 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11636500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 6289000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 1308645985 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 1308645985 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 19117500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 320801000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 339918500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035543 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.033710 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.033625 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.064967 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.064839 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.044719 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.044742 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.034775 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.034844 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.034775 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.034844 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12711.265829 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31710.431215 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9895.477816 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 8950.581395 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 19396.847844 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 19396.847844 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12694.391819 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31637.249737 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9819.831224 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 8997.138770 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 19359.813968 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 19359.813968 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1403,31 +1403,31 @@ system.cpu1.dcache.mshr_cap_events 0 # nu system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6377 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 199477 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71613 40.63% 40.63% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 237 0.13% 40.76% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1921 1.09% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 8 0.00% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 102492 58.14% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 176271 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 70248 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6372 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 199307 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 71537 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.13% 40.75% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1922 1.09% 41.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 8 0.00% 41.85% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 102421 58.15% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 176125 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 70172 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 237 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1921 1.35% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1922 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 8 0.01% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 70240 49.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 142654 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1858831999000 97.96% 97.96% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 90898500 0.00% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 391654500 0.02% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4204500 0.00% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 38151374000 2.01% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1897470130500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980939 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 70164 49.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 142503 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1858853057000 97.97% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 90805500 0.00% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 391568500 0.02% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 4023000 0.00% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 38125490000 2.01% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1897464944000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980919 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685322 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.685055 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.72% 3.72% # number of syscalls executed system.cpu0.kern.syscall::3 18 8.37% 12.09% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.40% 13.49% # number of syscalls executed @@ -1459,59 +1459,59 @@ system.cpu0.kern.syscall::144 2 0.93% 99.07% # nu system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 215 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 104 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wripir 105 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3842 2.08% 2.14% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3840 2.08% 2.14% # number of callpals executed system.cpu0.kern.callpal::tbi 50 0.03% 2.16% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal::swpipl 169337 91.54% 93.71% # number of callpals executed -system.cpu0.kern.callpal::rdps 6360 3.44% 97.14% # number of callpals executed +system.cpu0.kern.callpal::swpipl 169189 91.54% 93.71% # number of callpals executed +system.cpu0.kern.callpal::rdps 6337 3.43% 97.14% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.14% # number of callpals executed system.cpu0.kern.callpal::wrusp 2 0.00% 97.14% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 97.15% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::rti 4767 2.58% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4768 2.58% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed system.cpu0.kern.callpal::imb 135 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 184989 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7265 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1246 # number of protection mode switches +system.cpu0.kern.callpal::total 184818 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7264 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1248 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1245 -system.cpu0.kern.mode_good::user 1246 +system.cpu0.kern.mode_good::kernel 1247 +system.cpu0.kern.mode_good::user 1248 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.171370 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.171669 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1895606727500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1863395000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1895604498000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1860438000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3843 # number of times the context was actually changed +system.cpu0.kern.swap_context 3841 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2270 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 38355 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10172 33.29% 33.29% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1920 6.28% 39.57% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 104 0.34% 39.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18361 60.09% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30557 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10160 45.68% 45.68% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 8.63% 54.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 104 0.47% 54.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10056 45.22% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22240 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871109076500 98.61% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 343280000 0.02% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 41782500 0.00% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 25970941500 1.37% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1897465080500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998820 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2274 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 38564 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10256 33.36% 33.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1920 6.25% 39.61% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 105 0.34% 39.95% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18460 60.05% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30741 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10244 45.72% 45.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1920 8.57% 54.28% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 105 0.47% 54.75% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10139 45.25% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22408 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1871092276500 98.61% 98.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 343292500 0.02% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 42130500 0.00% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 25986985000 1.37% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1897464684500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998830 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.547683 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.549242 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 12 10.81% 10.81% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.90% 11.71% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.01% 20.72% # number of syscalls executed @@ -1531,32 +1531,32 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 8 0.03% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 391 1.24% 1.27% # number of callpals executed +system.cpu1.kern.callpal::swpctx 393 1.24% 1.27% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.01% 1.28% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.31% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26005 82.46% 83.77% # number of callpals executed -system.cpu1.kern.callpal::rdps 2390 7.58% 91.35% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.35% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.02% 91.37% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.38% # number of callpals executed -system.cpu1.kern.callpal::rti 2527 8.01% 99.39% # number of callpals executed -system.cpu1.kern.callpal::callsys 146 0.46% 99.85% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.30% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26187 82.50% 83.80% # number of callpals executed +system.cpu1.kern.callpal::rdps 2413 7.60% 91.40% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.41% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.02% 91.42% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.43% # number of callpals executed +system.cpu1.kern.callpal::rti 2528 7.96% 99.40% # number of callpals executed +system.cpu1.kern.callpal::callsys 146 0.46% 99.86% # number of callpals executed system.cpu1.kern.callpal::imb 45 0.14% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 31535 # number of callpals executed +system.cpu1.kern.callpal::total 31743 # number of callpals executed system.cpu1.kern.mode_switch::kernel 869 # number of protection mode switches system.cpu1.kern.mode_switch::user 492 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2051 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 521 +system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 522 system.cpu1.kern.mode_good::user 492 -system.cpu1.kern.mode_good::idle 29 -system.cpu1.kern.mode_switch_good::kernel 0.599540 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 30 +system.cpu1.kern.mode_switch_good::kernel 0.600690 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.014139 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.613679 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2030212000 0.11% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 852485500 0.04% 0.15% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893908030500 99.85% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 392 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.014606 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.615296 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2061638000 0.11% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 848590000 0.04% 0.15% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893876047000 99.85% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 394 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |