diff options
Diffstat (limited to 'tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt')
| -rw-r--r-- | tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 394 |
1 files changed, 284 insertions, 110 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index de748ed07..75071ea91 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 193554 # Simulator instruction rate (inst/s) -host_mem_usage 276972 # Number of bytes of host memory used -host_seconds 274.29 # Real time elapsed on the host -host_tick_rate 6807960214 # Simulator tick rate (ticks/s) +host_inst_rate 86499 # Simulator instruction rate (inst/s) +host_mem_usage 277924 # Number of bytes of host memory used +host_seconds 613.76 # Real time elapsed on the host +host_tick_rate 3042478511 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 53090223 # Number of instructions simulated sim_seconds 1.867363 # Number of seconds simulated @@ -49,51 +49,79 @@ system.cpu.committedInsts 53090223 # Nu system.cpu.committedInsts_total 53090223 # Number of Instructions Simulated system.cpu.cpi 2.580471 # CPI: Cycles Per Instruction system.cpu.cpi_total 2.580471 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 214422 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 15515.537615 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::0 214422 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214422 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15515.537615 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.147928 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 192250 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::0 192250 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192250 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_miss_latency 344010500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.103404 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 22172 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103404 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 22172 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22172 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 4650 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207007500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081717 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081717 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 17522 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 9342386 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 23884.018523 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses::0 9342386 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9342386 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 23884.018523 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22765.012818 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits 7810012 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::0 7810012 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7810012 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 36599249000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.164024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1532374 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate::0 0.164024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1532374 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1532374 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 447551 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 24696009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.116118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1084823 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904976000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses 219797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.488950 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_accesses::0 219797 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219797 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56331.488950 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.488950 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits 189796 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::0 189796 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 189796 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_miss_latency 1690001000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate 0.136494 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 30001 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.136494 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 30001 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 30001 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599998000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136494 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136494 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_misses 30001 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6157245 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 49037.572489 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses::0 6157245 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157245 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 49037.572489 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54494.404609 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits 3926713 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::0 3926713 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 3926713 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 109379874638 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.362261 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2230532 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate::0 0.362261 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 2230532 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2230532 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 1833591 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 21631063460 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.064467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 396941 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235842997 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs 10022.289139 # average number of cycles each access was blocked @@ -104,31 +132,57 @@ system.cpu.dcache.blocked::no_targets 4 # nu system.cpu.dcache.blocked_cycles::no_mshrs 1373885462 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 66000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15499631 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 38794.252006 # average overall miss latency +system.cpu.dcache.demand_accesses::0 15499631 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15499631 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 38794.252006 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency -system.cpu.dcache.demand_hits 11736725 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 11736725 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11736725 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 145979123638 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.242774 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3762906 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate::0 0.242774 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.demand_misses::0 3762906 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3762906 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 2281142 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 46327072960 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.095600 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.095600 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1481764 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15499631 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 38794.252006 # average overall miss latency +system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.995450 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15499631 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15499631 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 38794.252006 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 11736725 # number of overall hits +system.cpu.dcache.overall_hits::0 11736725 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 11736725 # number of overall hits system.cpu.dcache.overall_miss_latency 145979123638 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.242774 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3762906 # number of overall misses +system.cpu.dcache.overall_miss_rate::0 0.242774 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.overall_misses::0 3762906 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 3762906 # number of overall misses system.cpu.dcache.overall_mshr_hits 2281142 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 46327072960 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.095600 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.095600 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1481764 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 2140818997 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -192,16 +246,23 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 102272708 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 8997144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14906.743449 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses::0 8997144 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8997144 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14906.743449 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.437092 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 7949609 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::0 7949609 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7949609 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 15615335499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.116430 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1047535 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_rate::0 0.116430 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 1047535 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1047535 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 51877 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 11855735000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.110664 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110664 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 995658 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs 11545.454545 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked @@ -211,31 +272,57 @@ system.cpu.icache.blocked::no_targets 0 # nu system.cpu.icache.blocked_cycles::no_mshrs 635000 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 8997144 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14906.743449 # average overall miss latency +system.cpu.icache.demand_accesses::0 8997144 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8997144 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14906.743449 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency -system.cpu.icache.demand_hits 7949609 # number of demand (read+write) hits +system.cpu.icache.demand_hits::0 7949609 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7949609 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 15615335499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.116430 # miss rate for demand accesses -system.cpu.icache.demand_misses 1047535 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate::0 0.116430 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.demand_misses::0 1047535 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1047535 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 51877 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 11855735000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.110664 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.110664 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 995658 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 8997144 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14906.743449 # average overall miss latency +system.cpu.icache.occ_%::0 0.995649 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 509.772438 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 8997144 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8997144 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14906.743449 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 7949609 # number of overall hits +system.cpu.icache.overall_hits::0 7949609 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 7949609 # number of overall hits system.cpu.icache.overall_miss_latency 15615335499 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.116430 # miss rate for overall accesses -system.cpu.icache.overall_misses 1047535 # number of overall misses +system.cpu.icache.overall_miss_rate::0 0.116430 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.overall_misses::0 1047535 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 1047535 # number of overall misses system.cpu.icache.overall_mshr_hits 51877 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 11855735000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.110664 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.110664 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 995658 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -482,23 +569,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 115260.104046 # average ReadReq miss latency +system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 173 # number of ReadReq misses +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses::1 173 # number of ReadReq misses +system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137794.253129 # average WriteReq miss latency +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137794.253129 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.WriteReq_avg_mshr_miss_latency 85790.836302 # average WriteReq mshr miss latency system.iocache.WriteReq_miss_latency 5725626806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.WriteReq_mshr_miss_latency 3564780830 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses system.iocache.avg_blocked_cycles::no_mshrs 6161.136802 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked @@ -508,31 +607,57 @@ system.iocache.blocked::no_targets 0 # nu system.iocache.blocked_cycles::no_mshrs 64537908 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137700.822145 # average overall miss latency +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137700.822145 # average overall miss latency +system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.demand_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.demand_miss_latency 5745566804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41725 # number of demand (read+write) misses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41725 # number of demand (read+write) misses +system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.demand_mshr_miss_latency 3575724828 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137700.822145 # average overall miss latency +system.iocache.occ_%::1 0.079213 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.267415 # Average occupied blocks per context +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137700.822145 # average overall miss latency +system.iocache.overall_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits system.iocache.overall_miss_latency 5745566804 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41725 # number of overall misses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41725 # number of overall misses +system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.overall_mshr_miss_latency 3575724828 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -543,41 +668,62 @@ system.iocache.tagsinuse 1.267415 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1716179713000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 300582 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52361.965557 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 300582 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300582 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52361.965557 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40206.978448 # average ReadExReq mshr miss latency system.l2c.ReadExReq_miss_latency 15739064331 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 300582 # number of ReadExReq misses +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 300582 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 300582 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 12085493996 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 300582 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2097743 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52046.745492 # average ReadReq miss latency +system.l2c.ReadReq_accesses::0 2097743 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2097743 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52046.745492 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40015.135689 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1786590 # number of ReadReq hits +system.l2c.ReadReq_hits::0 1786590 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1786590 # number of ReadReq hits system.l2c.ReadReq_miss_latency 16194501000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.148328 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 311153 # number of ReadReq misses +system.l2c.ReadReq_miss_rate::0 0.148328 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 311153 # number of ReadReq misses +system.l2c.ReadReq_misses::total 311153 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_miss_latency 12450789500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.148327 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 0.148327 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 311152 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 810515500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 130274 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 52273.201045 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::0 130274 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 130274 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52273.201045 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.567435 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 6809838993 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 130274 # number of UpgradeReq misses +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 130274 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 130274 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 5223670500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 130274 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 1116273498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430447 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430447 # number of Writeback hits +system.l2c.Writeback_accesses::0 430447 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 430447 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 430447 # number of Writeback hits +system.l2c.Writeback_hits::total 430447 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 4.597861 # Average number of references to valid blocks. @@ -586,31 +732,59 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2398325 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52201.631966 # average overall miss latency +system.l2c.demand_accesses::0 2398325 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2398325 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52201.631966 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency +system.l2c.demand_avg_miss_latency::total inf # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency -system.l2c.demand_hits 1786590 # number of demand (read+write) hits +system.l2c.demand_hits::0 1786590 # number of demand (read+write) hits +system.l2c.demand_hits::1 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 1786590 # number of demand (read+write) hits system.l2c.demand_miss_latency 31933565331 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.255068 # miss rate for demand accesses -system.l2c.demand_misses 611735 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.255068 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.demand_misses::0 611735 # number of demand (read+write) misses +system.l2c.demand_misses::1 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 611735 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 24536283496 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.255067 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.255067 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 611734 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2398325 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52201.631966 # average overall miss latency +system.l2c.occ_%::0 0.090392 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.377907 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5923.908547 # Average occupied blocks per context +system.l2c.occ_blocks::1 24766.488602 # Average occupied blocks per context +system.l2c.overall_accesses::0 2398325 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2398325 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52201.631966 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency +system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1786590 # number of overall hits +system.l2c.overall_hits::0 1786590 # number of overall hits +system.l2c.overall_hits::1 0 # number of overall hits +system.l2c.overall_hits::total 1786590 # number of overall hits system.l2c.overall_miss_latency 31933565331 # number of overall miss cycles -system.l2c.overall_miss_rate 0.255068 # miss rate for overall accesses -system.l2c.overall_misses 611735 # number of overall misses +system.l2c.overall_miss_rate::0 0.255068 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.overall_misses::0 611735 # number of overall misses +system.l2c.overall_misses::1 0 # number of overall misses +system.l2c.overall_misses::total 611735 # number of overall misses system.l2c.overall_mshr_hits 1 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 24536283496 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.255067 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.255067 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 611734 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 1926788998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |