diff options
Diffstat (limited to 'tests/long/10.linux-boot/ref/alpha/linux')
6 files changed, 88 insertions, 53 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 035a139c8..636d3e4ce 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -660,7 +660,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -680,7 +680,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -806,7 +806,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index a7674462a..51c672072 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -7,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:50:36 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:50:38 -M5 executing on zizzer +M5 compiled Jun 16 2010 10:39:13 +M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats +M5 started Jun 16 2010 10:40:27 +M5 executing on phenom command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 125751000 Exiting @ tick 1907689250500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index a30544a1e..011675055 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 140959 # Simulator instruction rate (inst/s) -host_mem_usage 294084 # Number of bytes of host memory used -host_seconds 398.50 # Real time elapsed on the host -host_tick_rate 4787234846 # Simulator tick rate (ticks/s) +host_inst_rate 198866 # Simulator instruction rate (inst/s) +host_mem_usage 278256 # Number of bytes of host memory used +host_seconds 282.46 # Real time elapsed on the host +host_tick_rate 6753860070 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56171530 # Number of instructions simulated sim_seconds 1.907689 # Number of seconds simulated @@ -1250,26 +1250,46 @@ system.l2c.ReadReq_mshr_miss_rate::2 inf # ms system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 311951 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 839822000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 86460 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 54412 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 140872 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 83177.133796 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 132167.444461 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_accesses::0 17600 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 13825 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 31425 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 92935.170455 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 118311.681736 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40007.112172 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_miss_latency 1635659000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 17600 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 13825 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 31425 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 1257223500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.785511 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 2.273056 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_misses 31425 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 68860 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 40587 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 109447 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 80683.066918 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 136887.081775 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40094.049918 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 7191494988 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40119.011942 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 5555835988 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 86460 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 54412 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 140872 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5648129000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.629331 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.588988 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 68860 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 40587 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 109447 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 4390905500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.589413 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.696602 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 140872 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 109447 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 1423289998 # number of WriteReq MSHR uncacheable cycles system.l2c.Writeback_accesses::0 451661 # number of Writeback accesses(hits+misses) diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 8128ce648..3fe2f1fcc 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -355,7 +355,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -375,7 +375,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -501,7 +501,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 6a353dabf..dea7a38d9 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -7,12 +7,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:50:36 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:51:37 -M5 executing on zizzer +M5 compiled Jun 16 2010 10:39:13 +M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats +M5 started Jun 16 2010 10:39:35 +M5 executing on phenom command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1867360295500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 867b96dc0..330dece92 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 146942 # Simulator instruction rate (inst/s) -host_mem_usage 291780 # Number of bytes of host memory used -host_seconds 361.25 # Real time elapsed on the host -host_tick_rate 5169110276 # Simulator tick rate (ticks/s) +host_inst_rate 205161 # Simulator instruction rate (inst/s) +host_mem_usage 276364 # Number of bytes of host memory used +host_seconds 258.74 # Real time elapsed on the host +host_tick_rate 7217130781 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 53083414 # Number of instructions simulated sim_seconds 1.867360 # Number of seconds simulated @@ -705,21 +705,36 @@ system.l2c.ReadReq_mshr_miss_rate::1 inf # ms system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 311410 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 810521500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 130096 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 130096 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52274.462658 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_accesses::0 29987 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 29987 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 52320.338813 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40001.217194 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_miss_latency 1568930000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 29987 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 29987 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 1199516500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_misses 29987 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 100109 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 100109 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52260.720754 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.358873 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6800698494 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40126.157488 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 5231768494 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 130096 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 130096 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5216506000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses::0 100109 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 100109 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 4016989500 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 130096 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 100109 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 1116126498 # number of WriteReq MSHR uncacheable cycles system.l2c.Writeback_accesses::0 430200 # number of Writeback accesses(hits+misses) |