diff options
Diffstat (limited to 'tests/long/10.linux-boot/ref/alpha/linux')
8 files changed, 2452 insertions, 2422 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 674bf0325..085ebcfb6 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -10,12 +10,13 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/chips/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/chips/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +memories=system.physmem +pal=/chips/pd/randd/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -930,7 +931,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -950,7 +951,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1046,6 +1047,7 @@ port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system. [system.membus.badaddr_responder] type=IsaFake +fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 @@ -1078,7 +1080,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -1197,6 +1199,7 @@ pio=system.iobus.port[27] [system.tsunami.fake_OROM] type=IsaFake +fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 @@ -1213,6 +1216,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake +fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 @@ -1229,6 +1233,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake +fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 @@ -1245,6 +1250,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake +fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 @@ -1261,6 +1267,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake +fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 @@ -1277,6 +1284,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake +fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 @@ -1293,6 +1301,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake +fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 @@ -1309,6 +1318,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake +fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 @@ -1325,6 +1335,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake +fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 @@ -1341,6 +1352,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake +fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 @@ -1357,6 +1369,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake +fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 @@ -1373,6 +1386,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake +fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 @@ -1389,6 +1403,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake +fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 @@ -1405,6 +1420,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake +fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 @@ -1421,6 +1437,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake +fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 @@ -1437,6 +1454,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake +fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 @@ -1453,6 +1471,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake +fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 @@ -1469,6 +1488,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake +fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 @@ -1485,6 +1505,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake +fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr index 0372a3b05..0bcb6e870 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -1,9 +1,5 @@ warn: Sockets disabled, not accepting terminal connections -For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 6aab5269d..9c91bbd4a 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,17 +1,13 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 12:02:59 -M5 started Apr 21 2011 13:21:52 -M5 executing on maize -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual +gem5 compiled Jul 8 2011 15:02:59 +gem5 started Jul 8 2011 18:23:45 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 109002500 -Exiting @ tick 1901725056500 because m5_exit instruction encountered +info: Launching CPU 1 @ 107915000 +Exiting @ tick 1898652239500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index a973eefe5..049977b68 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,1563 +1,1573 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 146685 # Simulator instruction rate (inst/s) -host_mem_usage 297796 # Number of bytes of host memory used -host_seconds 389.14 # Real time elapsed on the host -host_tick_rate 4887032789 # Simulator tick rate (ticks/s) +sim_seconds 1.898652 # Number of seconds simulated +sim_ticks 1898652239500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 57080594 # Number of instructions simulated -sim_seconds 1.901725 # Number of seconds simulated -sim_ticks 1901725056500 # Number of ticks simulated +host_inst_rate 56630 # Simulator instruction rate (inst/s) +host_tick_rate 1915374267 # Simulator tick rate (ticks/s) +host_mem_usage 336120 # Number of bytes of host memory used +host_seconds 991.27 # Real time elapsed on the host +sim_insts 56136028 # Number of instructions simulated +system.l2c.replacements 398212 # number of replacements +system.l2c.tagsinuse 35264.339871 # Cycle average of tags in use +system.l2c.total_refs 2531779 # Total number of references to valid blocks. +system.l2c.sampled_refs 433064 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.846201 # Average number of references to valid blocks. +system.l2c.warmup_cycle 9253572000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 10247.642027 # Average occupied blocks per context +system.l2c.occ_blocks::1 2471.458479 # Average occupied blocks per context +system.l2c.occ_blocks::2 22545.239365 # Average occupied blocks per context +system.l2c.occ_percent::0 0.156367 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.037711 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.344013 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 988451 # number of ReadReq hits +system.l2c.ReadReq_hits::1 903729 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1892180 # number of ReadReq hits +system.l2c.Writeback_hits::0 854494 # number of Writeback hits +system.l2c.Writeback_hits::total 854494 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 118 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 98 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 216 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 35 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 33 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 107958 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 83389 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 191347 # number of ReadExReq hits +system.l2c.demand_hits::0 1096409 # number of demand (read+write) hits +system.l2c.demand_hits::1 987118 # number of demand (read+write) hits +system.l2c.demand_hits::2 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 2083527 # number of demand (read+write) hits +system.l2c.overall_hits::0 1096409 # number of overall hits +system.l2c.overall_hits::1 987118 # number of overall hits +system.l2c.overall_hits::2 0 # number of overall hits +system.l2c.overall_hits::total 2083527 # number of overall hits +system.l2c.ReadReq_misses::0 301714 # number of ReadReq misses +system.l2c.ReadReq_misses::1 8229 # number of ReadReq misses +system.l2c.ReadReq_misses::total 309943 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 2585 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 556 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3141 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 58 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 106 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 164 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 104499 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 19805 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124304 # number of ReadExReq misses +system.l2c.demand_misses::0 406213 # number of demand (read+write) misses +system.l2c.demand_misses::1 28034 # number of demand (read+write) misses +system.l2c.demand_misses::2 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 434247 # number of demand (read+write) misses +system.l2c.overall_misses::0 406213 # number of overall misses +system.l2c.overall_misses::1 28034 # number of overall misses +system.l2c.overall_misses::2 0 # number of overall misses +system.l2c.overall_misses::total 434247 # number of overall misses +system.l2c.ReadReq_miss_latency 16115869500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 5950500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 996000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6519390500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22635260000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22635260000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 1290165 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 911958 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2202123 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 854494 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 854494 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 2703 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 654 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3357 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 93 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 139 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 232 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 212457 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 103194 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 315651 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 1502622 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 1015152 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2517774 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 1502622 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 1015152 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2517774 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.233857 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.009023 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.956345 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.850153 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.623656 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.762590 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.491860 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.191920 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.270336 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.027616 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.270336 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.027616 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 53414.390781 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 1958423.806052 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 2301.934236 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 10702.338129 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 17172.413793 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 9396.226415 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 62387.108968 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 329179.020449 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::0 55722.638123 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 807421.702219 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency +system.l2c.demand_avg_miss_latency::total inf # average overall miss latency +system.l2c.overall_avg_miss_latency::0 55722.638123 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 807421.702219 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency +system.l2c.overall_avg_miss_latency::total inf # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks 122541 # number of writebacks +system.l2c.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 22 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 22 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 309921 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3141 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 164 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 124304 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 434225 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 434225 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency 12396913500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 125650000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 6563500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5007569500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17404483000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17404483000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 838548000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1423652498 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 2262200498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.240218 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.339841 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.162042 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4.802752 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.763441 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.179856 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.585078 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 1.204566 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::0 0.288978 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0.427744 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.288978 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0.427744 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40000.237157 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40003.183699 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40021.341463 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40284.862112 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40081.715700 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40081.715700 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.replacements 41701 # number of replacements +system.iocache.tagsinuse 0.379408 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 41717 # Sample count of references to valid blocks. +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.warmup_cycle 1709327692000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.379408 # Average occupied blocks per context +system.iocache.occ_percent::1 0.023713 # Average percentage of cache occupancy +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits +system.iocache.ReadReq_misses::1 179 # number of ReadReq misses +system.iocache.ReadReq_misses::total 179 # number of ReadReq misses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41731 # number of demand (read+write) misses +system.iocache.demand_misses::total 41731 # number of demand (read+write) misses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41731 # number of overall misses +system.iocache.overall_misses::total 41731 # number of overall misses +system.iocache.ReadReq_miss_latency 20617998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5720950806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5741568804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5741568804 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 179 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41731 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41731 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115184.346369 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137681.719436 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137585.219717 # average overall miss latency +system.iocache.demand_avg_miss_latency::total inf # average overall miss latency +system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137585.219717 # average overall miss latency +system.iocache.overall_avg_miss_latency::total inf # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64667028 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6183.498566 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks 41522 # number of writebacks +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.ReadReq_mshr_misses 179 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses 41731 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 41731 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.ReadReq_mshr_miss_latency 11309998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3560091958 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571401956 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571401956 # number of overall MSHR miss cycles +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency 63184.346369 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85677.992828 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85581.509094 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85581.509094 # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.cpu0.dtb.fetch_hits 0 # ITB hits +system.cpu0.dtb.fetch_misses 0 # ITB misses +system.cpu0.dtb.fetch_acv 0 # ITB acv +system.cpu0.dtb.fetch_accesses 0 # ITB accesses +system.cpu0.dtb.read_hits 6880123 # DTB read hits +system.cpu0.dtb.read_misses 27029 # DTB read misses +system.cpu0.dtb.read_acv 463 # DTB read access violations +system.cpu0.dtb.read_accesses 649764 # DTB read accesses +system.cpu0.dtb.write_hits 4434059 # DTB write hits +system.cpu0.dtb.write_misses 4980 # DTB write misses +system.cpu0.dtb.write_acv 206 # DTB write access violations +system.cpu0.dtb.write_accesses 207730 # DTB write accesses +system.cpu0.dtb.data_hits 11314182 # DTB hits +system.cpu0.dtb.data_misses 32009 # DTB misses +system.cpu0.dtb.data_acv 669 # DTB access violations +system.cpu0.dtb.data_accesses 857494 # DTB accesses +system.cpu0.itb.fetch_hits 880445 # ITB hits +system.cpu0.itb.fetch_misses 30276 # ITB misses +system.cpu0.itb.fetch_acv 796 # ITB acv +system.cpu0.itb.fetch_accesses 910721 # ITB accesses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.read_acv 0 # DTB read access violations +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.write_acv 0 # DTB write access violations +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.data_hits 0 # DTB hits +system.cpu0.itb.data_misses 0 # DTB misses +system.cpu0.itb.data_acv 0 # DTB access violations +system.cpu0.itb.data_accesses 0 # DTB accesses +system.cpu0.numCycles 86706401 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.BPredUnit.lookups 9688854 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 8181343 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 315076 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 8774584 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 4716459 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 5478793 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 10568954 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 28086 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 455851 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 9912652 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 11764241 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 785162 # Number of times the RAS was used to get a target. -system.cpu0.commit.branchMispredicts 606344 # The number of times a branch was mispredicted -system.cpu0.commit.branches 7026012 # Number of branches committed -system.cpu0.commit.bw_lim_events 938799 # number cycles where commit BW limit reached -system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.commitCommittedInsts 47025846 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 585526 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 5969393 # The number of squashed insts skipped by commit -system.cpu0.commit.committed_per_cycle::samples 72953049 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.644604 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.459058 # Number of insts commited each cycle +system.cpu0.BPredUnit.usedRAS 623303 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 24682 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 18567041 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 50425492 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 9688854 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5339762 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 9915303 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1544367 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 26514797 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 7883 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 184619 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 223130 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 114 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6371925 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 198240 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 56424843 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.893675 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.198082 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 46509540 82.43% 82.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 722585 1.28% 83.71% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1421448 2.52% 86.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 628845 1.11% 87.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2255580 4.00% 91.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 483816 0.86% 92.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 510012 0.90% 93.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 672132 1.19% 94.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3220885 5.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 56424843 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.111743 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.581566 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19801968 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 25882509 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8989466 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 763548 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 987351 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 383922 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 24849 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 49347154 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 75527 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 987351 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 20629203 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 9499998 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13447452 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8452255 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3408582 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 46738624 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 3619 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 624032 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1191344 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 31596053 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 57298293 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 57042075 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 256218 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 26711174 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4884879 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1120422 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 175328 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8812934 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7283662 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 4733758 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1431112 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1440543 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 41212860 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1406639 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 39893176 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 57069 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5631702 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3133217 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 960480 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 56424843 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.707014 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.300043 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 37805881 67.00% 67.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 8674612 15.37% 82.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4282035 7.59% 89.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2440705 4.33% 94.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1659937 2.94% 97.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 878759 1.56% 98.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 516481 0.92% 99.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 131514 0.23% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 34919 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 56424843 # Number of insts issued each cycle +system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 44960 12.13% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 207193 55.91% 68.04% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 118450 31.96% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.FU_type_0::No_OpClass 4482 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 27545306 69.05% 69.06% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 42376 0.11% 69.17% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 14767 0.04% 69.20% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.20% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.20% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.20% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 2231 0.01% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7173118 17.98% 87.19% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 4487292 11.25% 98.44% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 623604 1.56% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::total 39893176 # Type of FU issued +system.cpu0.iq.rate 0.460095 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 370605 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.009290 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 136270898 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 48090698 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 38918381 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 367971 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 179542 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 176099 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 40067792 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 191507 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 416583 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread0.squashedLoads 1090641 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 12429 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 20965 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 441226 # Number of stores squashed +system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread0.rescheduledLoads 12240 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 165915 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu0.iew.iewSquashCycles 987351 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6354184 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 491419 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 45032066 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 578341 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7283662 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 4733758 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1245675 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 448555 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 7135 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 20965 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 225122 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 243860 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 468982 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 39459085 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 6924497 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 434091 # Number of squashed instructions skipped in execute +system.cpu0.iew.exec_swp 0 # number of swp insts executed +system.cpu0.iew.exec_nop 2412567 # number of nop insts executed +system.cpu0.iew.exec_refs 11372805 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6223343 # Number of branches executed +system.cpu0.iew.exec_stores 4448308 # Number of stores executed +system.cpu0.iew.exec_rate 0.455088 # Inst execution rate +system.cpu0.iew.wb_sent 39184807 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 39094480 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 19569580 # num instructions producing a value +system.cpu0.iew.wb_consumers 25865337 # num instructions consuming a value +system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu0.iew.wb_rate 0.450883 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.756595 # average fanout of values written-back +system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu0.commit.commitCommittedInsts 38900399 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6019570 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 446159 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 429799 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 55437492 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.701698 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.560671 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 53597246 73.47% 73.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8417746 11.54% 85.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4840163 6.63% 91.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2111570 2.89% 94.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1587453 2.18% 96.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 575078 0.79% 97.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 337488 0.46% 97.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 547506 0.75% 98.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 938799 1.29% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 40051862 72.25% 72.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6559971 11.83% 84.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3806221 6.87% 90.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1668838 3.01% 93.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1194660 2.15% 96.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 396856 0.72% 96.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 307618 0.55% 97.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 498884 0.90% 98.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 952582 1.72% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 72953049 # Number of insts commited each cycle -system.cpu0.commit.count 47025846 # Number of instructions committed -system.cpu0.commit.fp_insts 287589 # Number of committed floating point instructions. -system.cpu0.commit.function_calls 606692 # Number of function calls committed. -system.cpu0.commit.int_insts 43528406 # Number of committed integer instructions. -system.cpu0.commit.loads 7569996 # Number of loads committed -system.cpu0.commit.membars 198353 # Number of memory barriers committed -system.cpu0.commit.refs 12959088 # Number of memory references committed +system.cpu0.commit.committed_per_cycle::total 55437492 # Number of insts commited each cycle +system.cpu0.commit.count 38900399 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.committedInsts 44336308 # Number of Instructions Simulated -system.cpu0.committedInsts_total 44336308 # Number of Instructions Simulated -system.cpu0.cpi 2.365714 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.365714 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses::0 187921 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 187921 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 13445.030972 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10250.543228 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 169356 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 169356 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 249607000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.098792 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 18565 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18565 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 3378 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 155675000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.080816 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 15187 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 7569121 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7569121 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 24067.489407 # average ReadReq miss latency +system.cpu0.commit.refs 10485553 # Number of memory references committed +system.cpu0.commit.loads 6193021 # Number of loads committed +system.cpu0.commit.membars 147117 # Number of memory barriers committed +system.cpu0.commit.branches 5834794 # Number of branches committed +system.cpu0.commit.fp_insts 173443 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 36122415 # Number of committed integer instructions. +system.cpu0.commit.function_calls 477666 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 952582 # number cycles where commit BW limit reached +system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu0.rob.rob_reads 99224913 # The number of ROB reads +system.cpu0.rob.rob_writes 90827622 # The number of ROB writes +system.cpu0.timesIdled 838575 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 30281558 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 36751342 # Number of Instructions Simulated +system.cpu0.committedInsts_total 36751342 # Number of Instructions Simulated +system.cpu0.cpi 2.359272 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.359272 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.423860 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.423860 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 52035955 # number of integer regfile reads +system.cpu0.int_regfile_writes 28508894 # number of integer regfile writes +system.cpu0.fp_regfile_reads 87486 # number of floating regfile reads +system.cpu0.fp_regfile_writes 87606 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1265189 # number of misc regfile reads +system.cpu0.misc_regfile_writes 638472 # number of misc regfile writes +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.cpu0.icache.replacements 604064 # number of replacements +system.cpu0.icache.tagsinuse 509.990240 # Cycle average of tags in use +system.cpu0.icache.total_refs 5734171 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 604576 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.484616 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23368350000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 509.990240 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.996075 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::0 5734171 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5734171 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 5734171 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5734171 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 5734171 # number of overall hits +system.cpu0.icache.overall_hits::1 0 # number of overall hits +system.cpu0.icache.overall_hits::total 5734171 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 637754 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 637754 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 637754 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 637754 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 637754 # number of overall misses +system.cpu0.icache.overall_misses::1 0 # number of overall misses +system.cpu0.icache.overall_misses::total 637754 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 9712599996 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 9712599996 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 9712599996 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 6371925 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6371925 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 6371925 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6371925 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 6371925 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6371925 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.100088 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.100088 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::0 0.100088 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::0 15229.383110 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::0 15229.383110 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 15229.383110 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1053998 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 101 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 10435.623762 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks 253 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 33035 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 33035 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 33035 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 604719 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 604719 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 604719 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency 7372056498 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 7372056498 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 7372056498 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.094904 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.094904 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.094904 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12190.879562 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 12190.879562 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12190.879562 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.replacements 899634 # number of replacements +system.cpu0.dcache.tagsinuse 446.158722 # Cycle average of tags in use +system.cpu0.dcache.total_refs 8155860 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 900023 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.061835 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::0 447.158722 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.873357 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::0 5166195 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5166195 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::0 2708345 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 2708345 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 133652 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 133652 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::0 151966 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 151966 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::0 7874540 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 7874540 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::0 7874540 # number of overall hits +system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::total 7874540 # number of overall hits +system.cpu0.dcache.ReadReq_misses::0 1064203 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1064203 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::0 1419249 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1419249 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::0 11793 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11793 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::0 744 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 744 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::0 2483452 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2483452 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::0 2483452 # number of overall misses +system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::total 2483452 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 27896641000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 47260927840 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency 183691500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 7368500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency 75157568840 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 75157568840 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 6230398 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6230398 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 4127594 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4127594 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 145445 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 145445 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 152710 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 152710 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 10357992 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10357992 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 10357992 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10357992 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.170808 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.343844 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.081082 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.004872 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.239762 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::0 0.239762 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::0 26213.646269 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 26547.034409 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 6281230 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6281230 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 30996303000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.170151 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 1287891 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1287891 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 494238 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 21069133500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.104854 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 793653 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 636739500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 196148 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 196148 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 12580.258745 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 9578.581696 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 191974 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191974 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 52510000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.021280 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 4174 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4174 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 39981000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.021280 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 4174 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 5179136 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5179136 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 31904.477186 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 33299.955004 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30396.485851 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 3600390 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3600390 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 50369065740 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.304828 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 1578746 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1578746 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1328268 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 7613650983 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.048363 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 250478 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1111159498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8752.803276 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.840448 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 95418 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 835174983 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 12748257 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12748257 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 28383.561902 # average overall miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15576.316459 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9903.897849 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 30263.346680 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 27470.484530 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 9881620 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9881620 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 81365368740 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.224865 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 2866637 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2866637 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1822506 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 28682784483 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.081904 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1044131 # number of demand (read+write) MSHR misses -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_blocks::0 489.863061 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.956764 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.overall_accesses::0 12748257 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12748257 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 28383.561902 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 30263.346680 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 27470.484530 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 9881620 # number of overall hits -system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 9881620 # number of overall hits -system.cpu0.dcache.overall_miss_latency 81365368740 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.224865 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 2866637 # number of overall misses -system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2866637 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1822506 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 28682784483 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.081904 # mshr miss rate for overall accesses +system.cpu0.dcache.blocked_cycles::no_mshrs 831922069 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 188000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 93842 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8865.135749 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 23500 # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks 419465 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 382209 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1203298 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 2986 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 1585507 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 1585507 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 681994 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 215951 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 8807 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 744 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 897945 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 897945 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 19802710500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 7045833069 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 103680500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 5132500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 5001 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 26848543569 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 26848543569 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 634638000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1036991998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 1671629998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.109462 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.052319 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.060552 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.004872 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.086691 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.086691 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1044131 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 1747898998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 1041325 # number of replacements -system.cpu0.dcache.sampled_refs 1041715 # Sample count of references to valid blocks. +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 29036.487858 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 32626.999037 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11772.510503 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6898.521505 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 29899.986713 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 29899.986713 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 488.863062 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10250942 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 532971 # number of writebacks -system.cpu0.decode.BlockedCycles 30335443 # Number of cycles decode is blocked -system.cpu0.decode.BranchMispred 32433 # Number of times decode detected a branch misprediction -system.cpu0.decode.BranchResolved 467445 # Number of times decode resolved a branch -system.cpu0.decode.DecodedInsts 58302731 # Number of instructions handled by decode -system.cpu0.decode.IdleCycles 31236137 # Number of cycles decode is idle -system.cpu0.decode.RunCycles 10506640 # Number of cycles decode is running -system.cpu0.decode.SquashCycles 1085015 # Number of cycles decode is squashing -system.cpu0.decode.SquashedInsts 96992 # Number of squashed instructions handled by decode -system.cpu0.decode.UnblockCycles 874828 # Number of cycles decode is unblocking -system.cpu0.dtb.data_accesses 755162 # DTB accesses -system.cpu0.dtb.data_acv 768 # DTB access violations -system.cpu0.dtb.data_hits 13777358 # DTB hits -system.cpu0.dtb.data_misses 33542 # DTB misses -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 569569 # DTB read accesses -system.cpu0.dtb.read_acv 514 # DTB read access violations -system.cpu0.dtb.read_hits 8255195 # DTB read hits -system.cpu0.dtb.read_misses 26791 # DTB read misses -system.cpu0.dtb.write_accesses 185593 # DTB write accesses -system.cpu0.dtb.write_acv 254 # DTB write access violations -system.cpu0.dtb.write_hits 5522163 # DTB write hits -system.cpu0.dtb.write_misses 6751 # DTB write misses -system.cpu0.fetch.Branches 11764241 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 7276849 # Number of cache lines fetched -system.cpu0.fetch.Cycles 11546182 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 354114 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 59401999 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 28935 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 709322 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.112161 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 7276849 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 6263955 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.566343 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 74038064 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.802317 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.109343 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 62491882 84.41% 84.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 859667 1.16% 85.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1580756 2.14% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 707840 0.96% 88.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2540715 3.43% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 543724 0.73% 92.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 599348 0.81% 93.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 933324 1.26% 94.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3780808 5.11% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 74038064 # Number of instructions fetched each cycle (Total) -system.cpu0.fp_regfile_reads 141418 # number of floating regfile reads -system.cpu0.fp_regfile_writes 143630 # number of floating regfile writes -system.cpu0.icache.ReadReq_accesses::0 7276849 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7276849 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 14969.786485 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11880.005982 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 6407354 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6407354 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 13016154500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.119488 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 869495 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 869495 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 30374 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 9968762500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.115314 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 839121 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11944.444444 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 7.637231 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 36 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 430000 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 7276849 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7276849 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 14969.786485 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11880.005982 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 6407354 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6407354 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 13016154500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.119488 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 869495 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 869495 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 30374 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 9968762500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.115314 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 839121 # number of demand (read+write) MSHR misses -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_blocks::0 509.875783 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.995851 # Average percentage of cache occupancy -system.cpu0.icache.overall_accesses::0 7276849 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7276849 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 14969.786485 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11880.005982 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 6407354 # number of overall hits -system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 6407354 # number of overall hits -system.cpu0.icache.overall_miss_latency 13016154500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.119488 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 869495 # number of overall misses -system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 869495 # number of overall misses -system.cpu0.icache.overall_mshr_hits 30374 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 9968762500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.115314 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 839121 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 838452 # number of replacements -system.cpu0.icache.sampled_refs 838963 # Sample count of references to valid blocks. -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.875783 # Cycle average of tags in use -system.cpu0.icache.total_refs 6407354 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23816238000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 147 # number of writebacks -system.cpu0.idleCycles 30848962 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.branchMispredicts 654991 # Number of branch mispredicts detected at execute -system.cpu0.iew.exec_branches 7463719 # Number of branches executed -system.cpu0.iew.exec_nop 2952874 # number of nop insts executed -system.cpu0.iew.exec_rate 0.449724 # Inst execution rate -system.cpu0.iew.exec_refs 13848442 # number of memory reference insts executed -system.cpu0.iew.exec_stores 5542976 # Number of stores executed -system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.iewBlockCycles 7417251 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 8574378 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1551984 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 727686 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 5707393 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 53103916 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 8305466 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 392048 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 47170169 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 90492 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 5675 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1085015 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 526785 # Number of cycles IEW is unblocking -system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.cacheBlocked 157871 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread0.forwLoads 427137 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread0.ignoredResponses 7542 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread0.memOrderViolation 14768 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.rescheduledLoads 12869 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.squashedLoads 1004382 # Number of loads squashed -system.cpu0.iew.lsq.thread0.squashedStores 318301 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 14768 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 331464 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 323527 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.wb_consumers 29600256 # num instructions consuming a value -system.cpu0.iew.wb_count 46794498 # cumulative count of insts written-back -system.cpu0.iew.wb_fanout 0.755402 # average fanout of values written-back -system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.wb_producers 22360092 # num instructions producing a value -system.cpu0.iew.wb_rate 0.446142 # insts written-back per cycle -system.cpu0.iew.wb_sent 46875004 # cumulative count of insts sent to commit -system.cpu0.int_regfile_reads 61873527 # number of integer regfile reads -system.cpu0.int_regfile_writes 33807346 # number of integer regfile writes -system.cpu0.ipc 0.422705 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.422705 # IPC: Total IPC of All Threads -system.cpu0.iq.FU_type_0::No_OpClass 3310 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 32518161 68.37% 68.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 52150 0.11% 68.49% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.49% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15557 0.03% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1653 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8591465 18.06% 86.59% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5582440 11.74% 98.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 797481 1.68% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 47562217 # Type of FU issued -system.cpu0.iq.fp_alu_accesses 318343 # Number of floating point alu accesses -system.cpu0.iq.fp_inst_queue_reads 608219 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_wakeup_accesses 289004 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_writes 292979 # Number of floating instruction queue writes -system.cpu0.iq.fu_busy_cnt 465945 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.009797 # FU busy rate (busy events/executed inst) -system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 32168 6.90% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 239318 51.36% 58.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 194459 41.73% 100.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.int_alu_accesses 47706509 # Number of integer alu accesses -system.cpu0.iq.int_inst_queue_reads 169046393 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_wakeup_accesses 46505494 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.int_inst_queue_writes 55364625 # Number of integer instruction queue writes -system.cpu0.iq.iqInstsAdded 48386629 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 47562217 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1764413 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 5493402 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 26169 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 1178887 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 2580822 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.issued_per_cycle::samples 74038064 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.642402 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.245120 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 51535584 69.61% 69.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10789742 14.57% 84.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4855288 6.56% 90.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3076859 4.16% 94.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2068166 2.79% 97.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 951116 1.28% 98.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 576531 0.78% 99.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 134332 0.18% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 50446 0.07% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 74038064 # Number of insts issued each cycle -system.cpu0.iq.rate 0.453461 # Inst issue rate -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 933233 # ITB accesses -system.cpu0.itb.fetch_acv 717 # ITB acv -system.cpu0.itb.fetch_hits 905545 # ITB hits -system.cpu0.itb.fetch_misses 27688 # ITB misses -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 371 0.22% 0.22% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.22% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.22% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.22% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3671 2.19% 2.42% # number of callpals executed -system.cpu0.kern.callpal::tbi 42 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 151594 90.58% 93.02% # number of callpals executed -system.cpu0.kern.callpal::rdps 6330 3.78% 96.81% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.81% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 96.81% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 96.81% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.81% # number of callpals executed -system.cpu0.kern.callpal::rti 4884 2.92% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 315 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 135 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 167365 # number of callpals executed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 180838 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 5105 # number of quiesce instructions executed -system.cpu0.kern.ipl_count::0 63498 39.95% 39.95% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 238 0.15% 40.10% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.21% 41.31% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 288 0.18% 41.50% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92981 58.50% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 158931 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 62140 49.14% 49.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 238 0.19% 49.33% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.52% 50.86% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 288 0.23% 51.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 61852 48.92% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 126444 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864722249000 98.07% 98.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 96095500 0.01% 98.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 397148000 0.02% 98.10% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 112025000 0.01% 98.10% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 36054288500 1.90% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1901381806000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.978613 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.665211 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good::kernel 1076 -system.cpu0.kern.mode_good::user 1076 -system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch::kernel 7211 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1076 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.149216 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1899282367000 99.91% 99.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1748332500 0.09% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3672 # number of times the context was actually changed -system.cpu0.kern.syscall::2 6 3.17% 3.17% # number of syscalls executed -system.cpu0.kern.syscall::3 16 8.47% 11.64% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.59% 13.23% # number of syscalls executed -system.cpu0.kern.syscall::6 26 13.76% 26.98% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.53% 27.51% # number of syscalls executed -system.cpu0.kern.syscall::17 8 4.23% 31.75% # number of syscalls executed -system.cpu0.kern.syscall::19 6 3.17% 34.92% # number of syscalls executed -system.cpu0.kern.syscall::20 4 2.12% 37.04% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.53% 37.57% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.59% 39.15% # number of syscalls executed -system.cpu0.kern.syscall::33 6 3.17% 42.33% # number of syscalls executed -system.cpu0.kern.syscall::41 2 1.06% 43.39% # number of syscalls executed -system.cpu0.kern.syscall::45 33 17.46% 60.85% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.59% 62.43% # number of syscalls executed -system.cpu0.kern.syscall::48 7 3.70% 66.14% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.76% 70.90% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.53% 71.43% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.65% 74.07% # number of syscalls executed -system.cpu0.kern.syscall::71 23 12.17% 86.24% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.59% 87.83% # number of syscalls executed -system.cpu0.kern.syscall::74 6 3.17% 91.01% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.53% 91.53% # number of syscalls executed -system.cpu0.kern.syscall::90 1 0.53% 92.06% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.70% 95.77% # number of syscalls executed -system.cpu0.kern.syscall::97 2 1.06% 96.83% # number of syscalls executed -system.cpu0.kern.syscall::98 2 1.06% 97.88% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.53% 98.41% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.53% 98.94% # number of syscalls executed -system.cpu0.kern.syscall::147 2 1.06% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 189 # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 1239149 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1190008 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 8574378 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5707393 # Number of stores inserted to the mem dependence unit. -system.cpu0.misc_regfile_reads 1734015 # number of misc regfile reads -system.cpu0.misc_regfile_writes 822223 # number of misc regfile writes -system.cpu0.numCycles 104887026 # number of cpu cycles simulated -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.rename.BlockCycles 10226952 # Number of cycles rename is blocking -system.cpu0.rename.CommittedMaps 32010277 # Number of HB maps that are committed -system.cpu0.rename.IQFullEvents 742771 # Number of times rename has blocked due to IQ full -system.cpu0.rename.IdleCycles 32554760 # Number of cycles rename is idle -system.cpu0.rename.LSQFullEvents 1133948 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.ROBFullEvents 1272 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RenameLookups 67011150 # Number of register rename lookups that rename has made -system.cpu0.rename.RenamedInsts 55116446 # Number of instructions processed by rename -system.cpu0.rename.RenamedOperands 36911598 # Number of destination operands rename has renamed -system.cpu0.rename.RunCycles 10340148 # Number of cycles rename is running -system.cpu0.rename.SquashCycles 1085015 # Number of cycles rename is squashing -system.cpu0.rename.UnblockCycles 3374476 # Number of cycles rename is unblocking -system.cpu0.rename.UndoneMaps 4901321 # Number of HB maps that are undone due to squashing -system.cpu0.rename.fp_rename_lookups 420638 # Number of floating rename lookups -system.cpu0.rename.int_rename_lookups 66590512 # Number of integer rename lookups -system.cpu0.rename.serializeStallCycles 16456711 # count of cycles rename stalled for serializing inst -system.cpu0.rename.serializingInsts 1432211 # count of serializing insts renamed -system.cpu0.rename.skidInsts 8924178 # count of insts added to the skid buffer -system.cpu0.rename.tempSerializingInsts 217463 # count of temporary serializing insts renamed -system.cpu0.rob.rob_reads 124831913 # The number of ROB reads -system.cpu0.rob.rob_writes 107074537 # The number of ROB writes -system.cpu0.timesIdled 1083848 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dtb.fetch_hits 0 # ITB hits +system.cpu1.dtb.fetch_misses 0 # ITB misses +system.cpu1.dtb.fetch_acv 0 # ITB acv +system.cpu1.dtb.fetch_accesses 0 # ITB accesses +system.cpu1.dtb.read_hits 4024884 # DTB read hits +system.cpu1.dtb.read_misses 17321 # DTB read misses +system.cpu1.dtb.read_acv 119 # DTB read access violations +system.cpu1.dtb.read_accesses 318700 # DTB read accesses +system.cpu1.dtb.write_hits 2545920 # DTB write hits +system.cpu1.dtb.write_misses 4459 # DTB write misses +system.cpu1.dtb.write_acv 131 # DTB write access violations +system.cpu1.dtb.write_accesses 133305 # DTB write accesses +system.cpu1.dtb.data_hits 6570804 # DTB hits +system.cpu1.dtb.data_misses 21780 # DTB misses +system.cpu1.dtb.data_acv 250 # DTB access violations +system.cpu1.dtb.data_accesses 452005 # DTB accesses +system.cpu1.itb.fetch_hits 565000 # ITB hits +system.cpu1.itb.fetch_misses 8360 # ITB misses +system.cpu1.itb.fetch_acv 355 # ITB acv +system.cpu1.itb.fetch_accesses 573360 # ITB accesses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.read_acv 0 # DTB read access violations +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.write_acv 0 # DTB write access violations +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.data_hits 0 # DTB hits +system.cpu1.itb.data_misses 0 # DTB misses +system.cpu1.itb.data_acv 0 # DTB access violations +system.cpu1.itb.data_accesses 0 # DTB accesses +system.cpu1.numCycles 36324508 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.BPredUnit.lookups 5837794 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 4807752 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 236405 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 5114419 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 2355373 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 1509705 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 3127444 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 7361 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 156935 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 2982175 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 3622579 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 265553 # Number of times the RAS was used to get a target. -system.cpu1.commit.branchMispredicts 207236 # The number of times a branch was mispredicted -system.cpu1.commit.branches 2030517 # Number of branches committed -system.cpu1.commit.bw_lim_events 301379 # number cycles where commit BW limit reached -system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.commitCommittedInsts 13448285 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 143621 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 2329974 # The number of squashed insts skipped by commit -system.cpu1.commit.committed_per_cycle::samples 21012360 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.640018 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.474919 # Number of insts commited each cycle +system.cpu1.BPredUnit.usedRAS 425756 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 18870 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 12975380 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 28382917 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 5837794 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2781129 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 5303525 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 1029370 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 12998724 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 3277 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 80064 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 157005 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 3308770 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 142735 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 32191429 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.881692 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.232987 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 26887904 83.53% 83.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 353233 1.10% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 711039 2.21% 86.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 413904 1.29% 88.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 842441 2.62% 90.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 260322 0.81% 91.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 338125 1.05% 92.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 409918 1.27% 93.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1974543 6.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 32191429 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.160712 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.781371 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 12951837 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 13394594 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 4901613 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 288063 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 655321 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 259847 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 18216 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 27639459 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 54136 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 655321 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 13441589 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3341745 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 8668513 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 4556322 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1527937 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 25800670 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 384 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 324513 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 337358 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 16998396 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 30868000 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 30637033 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 230967 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 13782341 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 3216047 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 763704 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 85939 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 4786247 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 4278315 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2704053 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 527948 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 347634 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 22339353 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 928348 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 21581640 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 44138 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 3694956 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1842331 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 660792 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 32191429 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.670416 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.349411 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 23032002 71.55% 71.55% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 3880534 12.05% 83.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1841751 5.72% 89.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1343655 4.17% 93.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 1100926 3.42% 96.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 572017 1.78% 98.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 269219 0.84% 99.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 103064 0.32% 99.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 48261 0.15% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 32191429 # Number of insts issued each cycle +system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 27325 8.19% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 173483 52.02% 60.21% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 132688 39.79% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.FU_type_0::No_OpClass 2823 0.01% 0.01% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 14285140 66.19% 66.20% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 29916 0.14% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11006 0.05% 66.39% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.39% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.39% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.39% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1411 0.01% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 4218514 19.55% 85.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 2587729 11.99% 97.94% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 445101 2.06% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::total 21581640 # Type of FU issued +system.cpu1.iq.rate 0.594134 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 333496 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.015453 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 75401338 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 26810016 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 20892220 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 331004 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 159326 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 156915 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 21738437 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 173876 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 181996 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread0.squashedLoads 722762 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 9242 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 8212 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 265030 # Number of stores squashed +system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread0.rescheduledLoads 7445 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 45661 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu1.iew.iewSquashCycles 655321 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2533054 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 130038 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 24654122 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 348083 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 4278315 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 2704053 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 831283 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 42195 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6811 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 8212 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 170867 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 176891 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 347758 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 21288201 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 4056224 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 293438 # Number of squashed instructions skipped in execute +system.cpu1.iew.exec_swp 0 # number of swp insts executed +system.cpu1.iew.exec_nop 1386421 # number of nop insts executed +system.cpu1.iew.exec_refs 6615012 # number of memory reference insts executed +system.cpu1.iew.exec_branches 3371082 # Number of branches executed +system.cpu1.iew.exec_stores 2558788 # Number of stores executed +system.cpu1.iew.exec_rate 0.586056 # Inst execution rate +system.cpu1.iew.wb_sent 21107487 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 21049135 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 10120752 # num instructions producing a value +system.cpu1.iew.wb_consumers 14228146 # num instructions consuming a value +system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu1.iew.wb_rate 0.579475 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.711319 # average fanout of values written-back +system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu1.commit.commitCommittedInsts 20574037 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 4003646 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 267556 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 316871 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 31536108 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.652396 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.582786 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 15563519 74.07% 74.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2436778 11.60% 85.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1200178 5.71% 91.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 640529 3.05% 94.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 421093 2.00% 96.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 209093 1.00% 97.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 129842 0.62% 98.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 109949 0.52% 98.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 301379 1.43% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 23929669 75.88% 75.88% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 3216209 10.20% 86.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1611477 5.11% 91.19% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 871112 2.76% 93.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 572339 1.81% 95.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 274054 0.87% 96.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 208667 0.66% 97.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 210738 0.67% 97.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 641843 2.04% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 21012360 # Number of insts commited each cycle -system.cpu1.commit.count 13448285 # Number of instructions committed -system.cpu1.commit.fp_insts 77652 # Number of committed floating point instructions. -system.cpu1.commit.function_calls 196980 # Number of function calls committed. -system.cpu1.commit.int_insts 12472477 # Number of committed integer instructions. -system.cpu1.commit.loads 2329401 # Number of loads committed -system.cpu1.commit.membars 46552 # Number of memory barriers committed -system.cpu1.commit.refs 3759357 # Number of memory references committed +system.cpu1.commit.committed_per_cycle::total 31536108 # Number of insts commited each cycle +system.cpu1.commit.count 20574037 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.committedInsts 12744286 # Number of Instructions Simulated -system.cpu1.committedInsts_total 12744286 # Number of Instructions Simulated -system.cpu1.cpi 1.922547 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.922547 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses::0 34084 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 34084 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 12032.319953 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7746.929907 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 27308 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 27308 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 81531000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.198803 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 6776 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 6776 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 1483 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 41004500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.155293 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 5293 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 2478047 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2478047 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15160.837325 # average ReadReq miss latency +system.cpu1.commit.refs 5994576 # Number of memory references committed +system.cpu1.commit.loads 3555553 # Number of loads committed +system.cpu1.commit.membars 91088 # Number of memory barriers committed +system.cpu1.commit.branches 3081632 # Number of branches committed +system.cpu1.commit.fp_insts 155618 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 18958031 # Number of committed integer instructions. +system.cpu1.commit.function_calls 316244 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 641843 # number cycles where commit BW limit reached +system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu1.rob.rob_reads 55370614 # The number of ROB reads +system.cpu1.rob.rob_writes 49810796 # The number of ROB writes +system.cpu1.timesIdled 461933 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 4133079 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 19384686 # Number of Instructions Simulated +system.cpu1.committedInsts_total 19384686 # Number of Instructions Simulated +system.cpu1.cpi 1.873877 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.873877 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.533653 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.533653 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 27536671 # number of integer regfile reads +system.cpu1.int_regfile_writes 15012037 # number of integer regfile writes +system.cpu1.fp_regfile_reads 81305 # number of floating regfile reads +system.cpu1.fp_regfile_writes 82180 # number of floating regfile writes +system.cpu1.misc_regfile_reads 884105 # number of misc regfile reads +system.cpu1.misc_regfile_writes 384773 # number of misc regfile writes +system.cpu1.icache.replacements 474445 # number of replacements +system.cpu1.icache.tagsinuse 505.356684 # Cycle average of tags in use +system.cpu1.icache.total_refs 2809266 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 474955 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.914805 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 46541421000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 505.356684 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.987025 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::0 2809266 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 2809266 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 2809266 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 2809266 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 2809266 # number of overall hits +system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::total 2809266 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 499504 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 499504 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 499504 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 499504 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 499504 # number of overall misses +system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::total 499504 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 7358434998 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 7358434998 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 7358434998 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 3308770 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 3308770 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 3308770 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 3308770 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 3308770 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 3308770 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.150964 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.150964 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::0 0.150964 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::0 14731.483628 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::0 14731.483628 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 14731.483628 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 428499 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 44 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 9738.613636 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks 33 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 24498 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 24498 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 24498 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 475006 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 475006 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 475006 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency 5595943999 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 5595943999 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 5595943999 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.143560 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.143560 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.143560 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11780.785925 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11780.785925 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11780.785925 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.replacements 557180 # number of replacements +system.cpu1.dcache.tagsinuse 488.553100 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4834021 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 557692 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 8.667905 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 34444090000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::0 488.553100 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.954205 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::0 2945256 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2945256 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::0 1749855 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1749855 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 63493 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 63493 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::0 71374 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71374 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::0 4695111 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4695111 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 4695111 # number of overall hits +system.cpu1.dcache.overall_hits::1 0 # number of overall hits +system.cpu1.dcache.overall_hits::total 4695111 # number of overall hits +system.cpu1.dcache.ReadReq_misses::0 787154 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 787154 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::0 609216 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 609216 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::0 13718 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13718 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::0 830 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 830 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::0 1396370 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1396370 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::0 1396370 # number of overall misses +system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::total 1396370 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 11151181000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 13606670637 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 199877000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 10316000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 24757851637 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 24757851637 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 3732410 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3732410 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 2359071 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2359071 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 77211 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 77211 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 72204 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 72204 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 6091481 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6091481 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 6091481 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6091481 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.210897 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.258244 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.177669 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.011495 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.229233 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::0 0.229233 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::0 14166.454086 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12203.806584 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 2047581 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2047581 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 6526225000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.173712 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 430466 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 430466 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 150924 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 3411476500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.112807 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 279542 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 299904000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 32610 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 32610 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13453.081410 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10450.798884 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 28667 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 28667 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 53045500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.120914 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 3943 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3943 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 41207500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.120914 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 3943 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 1389552 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1389552 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 29195.465224 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 22334.723049 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26358.387662 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 1086825 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1086825 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 8838255601 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.217859 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 302727 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 302727 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 250029 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 1389034313 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.037924 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 52698 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 600087500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12134.424364 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 11000 # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 9.983135 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 9506 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 115349838 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 11000 # number of cycles access was blocked -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 3867599 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3867599 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 20955.574591 # average overall miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14570.418428 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12428.915663 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 17730.151491 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14448.924913 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 3134406 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3134406 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 15364480601 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.189573 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 733193 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 733193 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 400953 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 4800510813 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.085903 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 332240 # number of demand (read+write) MSHR misses -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_blocks::0 478.607338 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.934780 # Average percentage of cache occupancy -system.cpu1.dcache.overall_accesses::0 3867599 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3867599 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 20955.574591 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 17730.151491 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14448.924913 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 3134406 # number of overall hits -system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 3134406 # number of overall hits -system.cpu1.dcache.overall_miss_latency 15364480601 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.189573 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 733193 # number of overall misses -system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 733193 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 400953 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 4800510813 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.085903 # mshr miss rate for overall accesses +system.cpu1.dcache.blocked_cycles::no_mshrs 143111212 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 22000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 13232 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10815.538996 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks 434743 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 338033 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 504690 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 2893 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 842723 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 842723 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 449121 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 104526 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 10825 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 830 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 553647 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 553647 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 5367032500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 2133420198 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 121712000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 7814500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 7500452698 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 7500452698 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 301848000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 539476500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 841324500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.120330 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.044308 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.140200 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.011495 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.090889 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.090889 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 332240 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 899991500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 320146 # number of replacements -system.cpu1.dcache.sampled_refs 320658 # Sample count of references to valid blocks. +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11950.081381 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 20410.426095 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11243.602771 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 9415.060241 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 13547.355441 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 13547.355441 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 478.607338 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3201172 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 38945924000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 258747 # number of writebacks -system.cpu1.decode.BlockedCycles 8810954 # Number of cycles decode is blocked -system.cpu1.decode.BranchMispred 10399 # Number of times decode detected a branch misprediction -system.cpu1.decode.BranchResolved 165542 # Number of times decode resolved a branch -system.cpu1.decode.DecodedInsts 17654641 # Number of instructions handled by decode -system.cpu1.decode.IdleCycles 8825966 # Number of cycles decode is idle -system.cpu1.decode.RunCycles 3267842 # Number of cycles decode is running -system.cpu1.decode.SquashCycles 401676 # Number of cycles decode is squashing -system.cpu1.decode.SquashedInsts 25654 # Number of squashed instructions handled by decode -system.cpu1.decode.UnblockCycles 107597 # Number of cycles decode is unblocking -system.cpu1.dtb.data_accesses 513633 # DTB accesses -system.cpu1.dtb.data_acv 185 # DTB access violations -system.cpu1.dtb.data_hits 4112878 # DTB hits -system.cpu1.dtb.data_misses 16265 # DTB misses -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 363334 # DTB read accesses -system.cpu1.dtb.read_acv 74 # DTB read access violations -system.cpu1.dtb.read_hits 2619291 # DTB read hits -system.cpu1.dtb.read_misses 12612 # DTB read misses -system.cpu1.dtb.write_accesses 150299 # DTB write accesses -system.cpu1.dtb.write_acv 111 # DTB write access violations -system.cpu1.dtb.write_hits 1493587 # DTB write hits -system.cpu1.dtb.write_misses 3653 # DTB write misses -system.cpu1.fetch.Branches 3622579 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 2099932 # Number of cache lines fetched -system.cpu1.fetch.Cycles 3426887 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 116518 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 18019858 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 11061 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 232369 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.147851 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 2099931 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 1775258 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.735460 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 21414036 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.841498 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.178120 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 17987149 84.00% 84.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 213365 1.00% 84.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 513318 2.40% 87.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 281609 1.32% 88.71% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 570957 2.67% 91.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 173244 0.81% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 240049 1.12% 93.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 130072 0.61% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1304273 6.09% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 21414036 # Number of instructions fetched each cycle (Total) -system.cpu1.fp_regfile_reads 44611 # number of floating regfile reads -system.cpu1.fp_regfile_writes 43862 # number of floating regfile writes -system.cpu1.icache.ReadReq_accesses::0 2099932 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2099932 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 15131.623612 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12110.189366 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 1856598 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1856598 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 3682038500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.115877 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 243334 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 243334 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 9659 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 2829848500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.111277 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 233675 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs 10681.818182 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 7.947119 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 22 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_mshrs 235000 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 2099932 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2099932 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 15131.623612 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 12110.189366 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 1856598 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1856598 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 3682038500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.115877 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 243334 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 243334 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 9659 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 2829848500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.111277 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 233675 # number of demand (read+write) MSHR misses -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_blocks::0 501.781584 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.980042 # Average percentage of cache occupancy -system.cpu1.icache.overall_accesses::0 2099932 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2099932 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 15131.623612 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 12110.189366 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 1856598 # number of overall hits -system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 1856598 # number of overall hits -system.cpu1.icache.overall_miss_latency 3682038500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.115877 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 243334 # number of overall misses -system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 243334 # number of overall misses -system.cpu1.icache.overall_mshr_hits 9659 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 2829848500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.111277 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 233675 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 233107 # number of replacements -system.cpu1.icache.sampled_refs 233619 # Sample count of references to valid blocks. -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 501.781584 # Cycle average of tags in use -system.cpu1.icache.total_refs 1856598 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1710247615000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.writebacks 27 # number of writebacks -system.cpu1.idleCycles 3087450 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.branchMispredicts 229368 # Number of branch mispredicts detected at execute -system.cpu1.iew.exec_branches 2215124 # Number of branches executed -system.cpu1.iew.exec_nop 807214 # number of nop insts executed -system.cpu1.iew.exec_rate 0.568172 # Inst execution rate -system.cpu1.iew.exec_refs 4143059 # number of memory reference insts executed -system.cpu1.iew.exec_stores 1503378 # Number of stores executed -system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.iewBlockCycles 1971298 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 2745592 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 455487 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 238559 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 1578351 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 15868399 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 2639681 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 166261 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 13921060 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 10672 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 5665 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 401676 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 76714 # Number of cycles IEW is unblocking -system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.cacheBlocked 25188 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread0.forwLoads 88996 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread0.ignoredResponses 4435 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread0.memOrderViolation 4299 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.rescheduledLoads 5923 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.squashedLoads 416191 # Number of loads squashed -system.cpu1.iew.lsq.thread0.squashedStores 148395 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 4299 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 105547 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 123821 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.wb_consumers 9185033 # num instructions consuming a value -system.cpu1.iew.wb_count 13765716 # cumulative count of insts written-back -system.cpu1.iew.wb_fanout 0.723664 # average fanout of values written-back -system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.wb_producers 6646874 # num instructions producing a value -system.cpu1.iew.wb_rate 0.561832 # insts written-back per cycle -system.cpu1.iew.wb_sent 13802747 # cumulative count of insts sent to commit -system.cpu1.int_regfile_reads 18282773 # number of integer regfile reads -system.cpu1.int_regfile_writes 9947337 # number of integer regfile writes -system.cpu1.ipc 0.520143 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.520143 # IPC: Total IPC of All Threads -system.cpu1.iq.FU_type_0::No_OpClass 3979 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 9510353 67.51% 67.54% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 21826 0.15% 67.69% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11300 0.08% 67.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1989 0.01% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2724274 19.34% 87.13% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1523321 10.81% 97.94% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 290281 2.06% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 14087323 # Type of FU issued -system.cpu1.iq.fp_alu_accesses 84267 # Number of floating point alu accesses -system.cpu1.iq.fp_inst_queue_reads 163543 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_wakeup_accesses 78913 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_writes 80927 # Number of floating instruction queue writes -system.cpu1.iq.fu_busy_cnt 199599 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014169 # FU busy rate (busy events/executed inst) -system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 10735 5.38% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 110682 55.45% 60.83% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 78182 39.17% 100.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.int_alu_accesses 14198676 # Number of integer alu accesses -system.cpu1.iq.int_inst_queue_reads 49640351 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_wakeup_accesses 13686803 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.int_inst_queue_writes 17182956 # Number of integer instruction queue writes -system.cpu1.iq.iqInstsAdded 14556864 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 14087323 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 504321 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 2199611 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 15615 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 360700 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 1165068 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.issued_per_cycle::samples 21414036 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.657855 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.314285 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 15246065 71.20% 71.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2762432 12.90% 84.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1149877 5.37% 89.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 942390 4.40% 93.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 699267 3.27% 97.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 379191 1.77% 98.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 160390 0.75% 99.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 52788 0.25% 99.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 21636 0.10% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 21414036 # Number of insts issued each cycle -system.cpu1.iq.rate 0.574958 # Inst issue rate -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 456053 # ITB accesses -system.cpu1.itb.fetch_acv 249 # ITB acv -system.cpu1.itb.fetch_hits 445822 # ITB hits -system.cpu1.itb.fetch_misses 10231 # ITB misses -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 288 0.55% 0.56% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.56% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.56% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1111 2.14% 2.70% # number of callpals executed -system.cpu1.kern.callpal::tbi 11 0.02% 2.72% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.73% # number of callpals executed -system.cpu1.kern.callpal::swpipl 44860 86.39% 89.12% # number of callpals executed -system.cpu1.kern.callpal::rdps 2426 4.67% 93.79% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.79% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 93.80% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.00% 93.81% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.81% # number of callpals executed -system.cpu1.kern.callpal::rti 2967 5.71% 99.53% # number of callpals executed -system.cpu1.kern.callpal::callsys 200 0.39% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 45 0.09% 100.00% # number of callpals executed -system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 51930 # number of callpals executed +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 139328 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 46150 38.89% 38.89% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 238 0.20% 39.09% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1923 1.62% 40.71% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 40.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 70336 59.27% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 118663 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 45525 48.84% 48.84% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 238 0.26% 49.10% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1923 2.06% 51.16% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 45509 48.82% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 93211 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865602561500 98.27% 98.27% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 91021500 0.00% 98.28% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 389859500 0.02% 98.30% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 7895500 0.00% 98.30% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 32350102500 1.70% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1898441440500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.986457 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.647023 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 5 2.39% 2.39% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.13% 10.53% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.44% 11.96% # number of syscalls executed +system.cpu0.kern.syscall::6 28 13.40% 25.36% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.48% 25.84% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.48% 26.32% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.31% 30.62% # number of syscalls executed +system.cpu0.kern.syscall::19 5 2.39% 33.01% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.91% 34.93% # number of syscalls executed +system.cpu0.kern.syscall::23 2 0.96% 35.89% # number of syscalls executed +system.cpu0.kern.syscall::24 4 1.91% 37.80% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.35% 41.15% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.96% 42.11% # number of syscalls executed +system.cpu0.kern.syscall::45 35 16.75% 58.85% # number of syscalls executed +system.cpu0.kern.syscall::47 4 1.91% 60.77% # number of syscalls executed +system.cpu0.kern.syscall::48 6 2.87% 63.64% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.31% 67.94% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.48% 68.42% # number of syscalls executed +system.cpu0.kern.syscall::59 4 1.91% 70.33% # number of syscalls executed +system.cpu0.kern.syscall::71 32 15.31% 85.65% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.44% 87.08% # number of syscalls executed +system.cpu0.kern.syscall::74 9 4.31% 91.39% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.48% 91.87% # number of syscalls executed +system.cpu0.kern.syscall::90 1 0.48% 92.34% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.35% 95.69% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.96% 96.65% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.96% 97.61% # number of syscalls executed +system.cpu0.kern.syscall::132 2 0.96% 98.56% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.48% 99.04% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 209 # number of syscalls executed +system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed +system.cpu0.kern.callpal::wripir 105 0.08% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2219 1.77% 1.85% # number of callpals executed +system.cpu0.kern.callpal::tbi 37 0.03% 1.88% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 1.89% # number of callpals executed +system.cpu0.kern.callpal::swpipl 112588 89.60% 91.49% # number of callpals executed +system.cpu0.kern.callpal::rdps 6309 5.02% 96.51% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.51% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.52% # number of callpals executed +system.cpu0.kern.callpal::rdusp 6 0.00% 96.52% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.52% # number of callpals executed +system.cpu0.kern.callpal::rti 3897 3.10% 99.62% # number of callpals executed +system.cpu0.kern.callpal::callsys 326 0.26% 99.88% # number of callpals executed +system.cpu0.kern.callpal::imb 146 0.12% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 125650 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5507 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1097 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1097 +system.cpu0.kern.mode_good::user 1097 +system.cpu0.kern.mode_good::idle 0 +system.cpu0.kern.mode_switch_good::kernel 0.199201 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1896108272000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1865257500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 2220 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 60321 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 4094 # number of quiesce instructions executed -system.cpu1.kern.ipl_count::0 19374 38.65% 38.65% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1924 3.84% 42.49% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 371 0.74% 43.23% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 28454 56.77% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 50123 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 19355 47.63% 47.63% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1924 4.73% 52.37% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 371 0.91% 53.28% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 18984 46.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 40634 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871185338500 98.39% 98.39% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 350210000 0.02% 98.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 149885000 0.01% 98.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 30038792500 1.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1901724226000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999019 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3828 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 98562 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 35646 40.41% 40.41% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1921 2.18% 42.59% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 105 0.12% 42.71% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 50532 57.29% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 88204 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 34894 48.66% 48.66% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1921 2.68% 51.34% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 105 0.15% 51.49% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 34789 48.51% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 71709 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1866332283500 98.30% 98.30% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 346173000 0.02% 98.32% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 42378500 0.00% 98.32% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 31930549500 1.68% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1898651384500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978904 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.667182 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 994 -system.cpu1.kern.mode_good::user 661 -system.cpu1.kern.mode_good::idle 333 -system.cpu1.kern.mode_switch::kernel 1487 # number of protection mode switches -system.cpu1.kern.mode_switch::user 661 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2593 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.668460 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used::31 0.688455 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 3 2.56% 2.56% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.11% 13.68% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.85% 14.53% # number of syscalls executed +system.cpu1.kern.syscall::6 14 11.97% 26.50% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.13% 31.62% # number of syscalls executed +system.cpu1.kern.syscall::19 5 4.27% 35.90% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.71% 37.61% # number of syscalls executed +system.cpu1.kern.syscall::23 2 1.71% 39.32% # number of syscalls executed +system.cpu1.kern.syscall::24 2 1.71% 41.03% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.42% 44.44% # number of syscalls executed +system.cpu1.kern.syscall::45 19 16.24% 60.68% # number of syscalls executed +system.cpu1.kern.syscall::47 2 1.71% 62.39% # number of syscalls executed +system.cpu1.kern.syscall::48 4 3.42% 65.81% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.85% 66.67% # number of syscalls executed +system.cpu1.kern.syscall::59 3 2.56% 69.23% # number of syscalls executed +system.cpu1.kern.syscall::71 22 18.80% 88.03% # number of syscalls executed +system.cpu1.kern.syscall::74 7 5.98% 94.02% # number of syscalls executed +system.cpu1.kern.syscall::90 2 1.71% 95.73% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.71% 97.44% # number of syscalls executed +system.cpu1.kern.syscall::132 2 1.71% 99.15% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.85% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 117 # number of syscalls executed +system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2023 2.23% 2.25% # number of callpals executed +system.cpu1.kern.callpal::tbi 16 0.02% 2.26% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.27% # number of callpals executed +system.cpu1.kern.callpal::swpipl 82767 91.03% 93.30% # number of callpals executed +system.cpu1.kern.callpal::rdps 2444 2.69% 95.99% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.99% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.00% 96.00% # number of callpals executed +system.cpu1.kern.callpal::rdusp 3 0.00% 96.00% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 96.00% # number of callpals executed +system.cpu1.kern.callpal::rti 3410 3.75% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 189 0.21% 99.96% # number of callpals executed +system.cpu1.kern.callpal::imb 34 0.04% 100.00% # number of callpals executed +system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed +system.cpu1.kern.callpal::total 90921 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2651 # number of protection mode switches +system.cpu1.kern.mode_switch::user 640 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2049 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 706 +system.cpu1.kern.mode_good::user 640 +system.cpu1.kern.mode_good::idle 66 +system.cpu1.kern.mode_switch_good::kernel 0.266315 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.128423 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.796883 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 37276082000 1.96% 1.96% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1059454000 0.06% 2.02% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1863388682000 97.98% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1112 # number of times the context was actually changed -system.cpu1.kern.syscall::2 2 1.46% 1.46% # number of syscalls executed -system.cpu1.kern.syscall::3 14 10.22% 11.68% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.73% 12.41% # number of syscalls executed -system.cpu1.kern.syscall::6 16 11.68% 24.09% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.73% 24.82% # number of syscalls executed -system.cpu1.kern.syscall::17 7 5.11% 29.93% # number of syscalls executed -system.cpu1.kern.syscall::19 4 2.92% 32.85% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.46% 34.31% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.19% 36.50% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.19% 38.69% # number of syscalls executed -system.cpu1.kern.syscall::33 5 3.65% 42.34% # number of syscalls executed -system.cpu1.kern.syscall::45 21 15.33% 57.66% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.19% 59.85% # number of syscalls executed -system.cpu1.kern.syscall::48 3 2.19% 62.04% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.73% 62.77% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.46% 64.23% # number of syscalls executed -system.cpu1.kern.syscall::71 31 22.63% 86.86% # number of syscalls executed -system.cpu1.kern.syscall::74 10 7.30% 94.16% # number of syscalls executed -system.cpu1.kern.syscall::90 2 1.46% 95.62% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.46% 97.08% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.19% 99.27% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.73% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 137 # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 315526 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 194379 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 2745592 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1578351 # Number of stores inserted to the mem dependence unit. -system.cpu1.misc_regfile_reads 493874 # number of misc regfile reads -system.cpu1.misc_regfile_writes 221749 # number of misc regfile writes -system.cpu1.numCycles 24501486 # number of cpu cycles simulated -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.rename.BlockCycles 2575160 # Number of cycles rename is blocking -system.cpu1.rename.CommittedMaps 9194083 # Number of HB maps that are committed -system.cpu1.rename.IQFullEvents 253610 # Number of times rename has blocked due to IQ full -system.cpu1.rename.IdleCycles 9125188 # Number of cycles rename is idle -system.cpu1.rename.LSQFullEvents 96900 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.ROBFullEvents 103 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RenameLookups 20382349 # Number of register rename lookups that rename has made -system.cpu1.rename.RenamedInsts 16583054 # Number of instructions processed by rename -system.cpu1.rename.RenamedOperands 11154403 # Number of destination operands rename has renamed -system.cpu1.rename.RunCycles 2970670 # Number of cycles rename is running -system.cpu1.rename.SquashCycles 401676 # Number of cycles rename is squashing -system.cpu1.rename.UnblockCycles 911632 # Number of cycles rename is unblocking -system.cpu1.rename.UndoneMaps 1960318 # Number of HB maps that are undone due to squashing -system.cpu1.rename.fp_rename_lookups 113596 # Number of floating rename lookups -system.cpu1.rename.int_rename_lookups 20268753 # Number of integer rename lookups -system.cpu1.rename.serializeStallCycles 5429708 # count of cycles rename stalled for serializing inst -system.cpu1.rename.serializingInsts 475094 # count of serializing insts renamed -system.cpu1.rename.skidInsts 2839642 # count of insts added to the skid buffer -system.cpu1.rename.tempSerializingInsts 40509 # count of temporary serializing insts renamed -system.cpu1.rob.rob_reads 36377887 # The number of ROB reads -system.cpu1.rob.rob_writes 31956605 # The number of ROB writes -system.cpu1.timesIdled 286877 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses::1 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115257.131429 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63257.131429 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 20169998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 11069998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses -system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137655.487245 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85651.857817 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5719860806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3559005996 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6179.103844 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64621068 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137561.550171 # average overall miss latency -system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85557.935965 # average overall mshr miss latency -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5740030804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3570075994 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_blocks::1 0.207263 # Average occupied blocks per context -system.iocache.occ_percent::1 0.012954 # Average percentage of cache occupancy -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137561.550171 # average overall miss latency -system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85557.935965 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5740030804 # number of overall miss cycles -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3570075994 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 41695 # number of replacements -system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.207263 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1710304111000 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses::0 243081 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 47227 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 290308 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 61154.932642 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 368564.170526 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40302.705557 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 135076 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 29306 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 164382 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6605038500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.444317 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.379465 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 108005 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 17921 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 125926 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5075158500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.518041 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 2.666398 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 125926 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1634357 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 503467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2137824 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 53314.961165 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 2119707.492415 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40003.636264 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1332950 # number of ReadReq hits -system.l2c.ReadReq_hits::1 495886 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1828836 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16069502500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.184419 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.015058 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 301407 # number of ReadReq misses -system.l2c.ReadReq_misses::1 7581 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308988 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12359963500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.189047 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.613687 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 308971 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 838535000 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 620 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 656 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1276 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 18379.965458 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 17109.324759 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40002.081599 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_hits::0 41 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 34 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_miss_latency 10642000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_rate::0 0.933871 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.948171 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 579 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 622 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1201 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 48042500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.937097 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.830793 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 1201 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 3788 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 897 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4685 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 1321.100917 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 5809.290954 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40001.698754 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 191 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 79 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 270 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 4752000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.949578 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.911929 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 3597 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 818 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4415 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 176607500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.165523 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 4.921962 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 4415 # number of UpgradeReq MSHR misses -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1545168498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 791892 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 791892 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 791892 # number of Writeback hits -system.l2c.Writeback_hits::total 791892 # number of Writeback hits -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.551399 # Average number of references to valid blocks. -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 1877438 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 550694 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2428132 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 55383.186130 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 889127.950749 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency -system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40090.232860 # average overall mshr miss latency -system.l2c.demand_hits::0 1468026 # number of demand (read+write) hits -system.l2c.demand_hits::1 525192 # number of demand (read+write) hits -system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1993218 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22674541000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.218070 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.046309 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses -system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 409412 # number of demand (read+write) misses -system.l2c.demand_misses::1 25502 # number of demand (read+write) misses -system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 434914 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17435122000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.231644 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.789725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 434897 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 10408.866153 # Average occupied blocks per context -system.l2c.occ_blocks::1 2398.359333 # Average occupied blocks per context -system.l2c.occ_blocks::2 23061.577659 # Average occupied blocks per context -system.l2c.occ_percent::0 0.158827 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.036596 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.351892 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 1877438 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 550694 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2428132 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 55383.186130 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 889127.950749 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency -system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40090.232860 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1468026 # number of overall hits -system.l2c.overall_hits::1 525192 # number of overall hits -system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 1993218 # number of overall hits -system.l2c.overall_miss_latency 22674541000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.218070 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.046309 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses -system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 409412 # number of overall misses -system.l2c.overall_misses::1 25502 # number of overall misses -system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 434914 # number of overall misses -system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17435122000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.231644 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.789725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 434897 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2383703498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 397174 # number of replacements -system.l2c.sampled_refs 433601 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 35868.803144 # Cycle average of tags in use -system.l2c.total_refs 2407092 # Total number of references to valid blocks. -system.l2c.warmup_cycle 9258990000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 122449 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.cpu1.kern.mode_switch_good::idle 0.032211 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.298525 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 43748791000 2.30% 2.30% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 905692500 0.05% 2.35% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1853996893000 97.65% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2024 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 2121232b8..be4d1c60b 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -10,12 +10,13 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/chips/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/chips/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +memories=system.physmem +pal=/chips/pd/randd/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -495,7 +496,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -515,7 +516,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -611,6 +612,7 @@ port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system. [system.membus.badaddr_responder] type=IsaFake +fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 @@ -643,7 +645,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -762,6 +764,7 @@ pio=system.iobus.port[27] [system.tsunami.fake_OROM] type=IsaFake +fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 @@ -778,6 +781,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake +fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 @@ -794,6 +798,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake +fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 @@ -810,6 +815,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake +fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 @@ -826,6 +832,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake +fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 @@ -842,6 +849,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake +fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 @@ -858,6 +866,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake +fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 @@ -874,6 +883,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake +fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 @@ -890,6 +900,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake +fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 @@ -906,6 +917,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake +fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 @@ -922,6 +934,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake +fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 @@ -938,6 +951,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake +fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 @@ -954,6 +968,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake +fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 @@ -970,6 +985,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake +fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 @@ -986,6 +1002,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake +fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 @@ -1002,6 +1019,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake +fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 @@ -1018,6 +1036,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake +fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 @@ -1034,6 +1053,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake +fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 @@ -1050,6 +1070,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake +fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr index 0372a3b05..0bcb6e870 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr @@ -1,9 +1,5 @@ warn: Sockets disabled, not accepting terminal connections -For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 6e8d29977..9aa3b6fd7 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,16 +1,12 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 12:02:59 -M5 started Apr 21 2011 13:21:52 -M5 executing on maize -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 +gem5 compiled Jul 8 2011 15:02:59 +gem5 started Jul 8 2011 18:21:28 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1863702170500 because m5_exit instruction encountered +Exiting @ tick 1860642398500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 3d92c2fae..3bf0e1e63 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,563 +1,843 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 146689 # Simulator instruction rate (inst/s) -host_mem_usage 295516 # Number of bytes of host memory used -host_seconds 361.92 # Real time elapsed on the host -host_tick_rate 5149474067 # Simulator tick rate (ticks/s) +sim_seconds 1.860642 # Number of seconds simulated +sim_ticks 1860642398500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53089625 # Number of instructions simulated -sim_seconds 1.863702 # Number of seconds simulated -sim_ticks 1863702170500 # Number of ticks simulated +host_inst_rate 59629 # Simulator instruction rate (inst/s) +host_tick_rate 2089604255 # Simulator tick rate (ticks/s) +host_mem_usage 333232 # Number of bytes of host memory used +host_seconds 890.43 # Real time elapsed on the host +sim_insts 53094994 # Number of instructions simulated +system.l2c.replacements 391412 # number of replacements +system.l2c.tagsinuse 34941.270648 # Cycle average of tags in use +system.l2c.total_refs 2407591 # Total number of references to valid blocks. +system.l2c.sampled_refs 424295 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.674333 # Average number of references to valid blocks. +system.l2c.warmup_cycle 5621019000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 12366.621064 # Average occupied blocks per context +system.l2c.occ_blocks::1 22574.649583 # Average occupied blocks per context +system.l2c.occ_percent::0 0.188700 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.344462 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1801894 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1801894 # number of ReadReq hits +system.l2c.Writeback_hits::0 835599 # number of Writeback hits +system.l2c.Writeback_hits::total 835599 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 183225 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183225 # number of ReadExReq hits +system.l2c.demand_hits::0 1985119 # number of demand (read+write) hits +system.l2c.demand_hits::1 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 1985119 # number of demand (read+write) hits +system.l2c.overall_hits::0 1985119 # number of overall hits +system.l2c.overall_hits::1 0 # number of overall hits +system.l2c.overall_hits::total 1985119 # number of overall hits +system.l2c.ReadReq_misses::0 308127 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308127 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 31 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 31 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 116938 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116938 # number of ReadExReq misses +system.l2c.demand_misses::0 425065 # number of demand (read+write) misses +system.l2c.demand_misses::1 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 425065 # number of demand (read+write) misses +system.l2c.overall_misses::0 425065 # number of overall misses +system.l2c.overall_misses::1 0 # number of overall misses +system.l2c.overall_misses::total 425065 # number of overall misses +system.l2c.ReadReq_miss_latency 16037568500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 372000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6135692000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22173260500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22173260500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2110021 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2110021 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 835599 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835599 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 48 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 48 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 300163 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300163 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2410184 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2410184 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2410184 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2410184 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.146030 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.645833 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.389582 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.176362 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.176362 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52048.566013 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 12000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52469.616378 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::0 52164.399562 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency +system.l2c.demand_avg_miss_latency::total inf # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52164.399562 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency +system.l2c.overall_avg_miss_latency::total inf # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks 117788 # number of writebacks +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 308127 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 31 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 116938 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 425065 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 425065 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency 12333883500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 1300000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4713361500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17047245000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17047245000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 810033500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1115471498 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 1925504998 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146030 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.645833 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.389582 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::0 0.176362 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.176362 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40028.571011 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 41935.483871 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40306.500026 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40105.030995 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40105.030995 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.replacements 41685 # number of replacements +system.iocache.tagsinuse 1.282104 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.warmup_cycle 1708339230000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 1.282104 # Average occupied blocks per context +system.iocache.occ_percent::1 0.080132 # Average percentage of cache occupancy +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits +system.iocache.ReadReq_misses::1 173 # number of ReadReq misses +system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41725 # number of demand (read+write) misses +system.iocache.demand_misses::total 41725 # number of demand (read+write) misses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41725 # number of overall misses +system.iocache.overall_misses::total 41725 # number of overall misses +system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5723029806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5742967804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5742967804 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137731.753129 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137638.533349 # average overall miss latency +system.iocache.demand_avg_miss_latency::total inf # average overall miss latency +system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137638.533349 # average overall miss latency +system.iocache.overall_avg_miss_latency::total inf # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64649956 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6171.244368 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks 41512 # number of writebacks +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3562178882 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3573120880 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3573120880 # number of overall MSHR miss cycles +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85728.217222 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85635.012103 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85635.012103 # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 10181490 # DTB read hits +system.cpu.dtb.read_misses 43507 # DTB read misses +system.cpu.dtb.read_acv 584 # DTB read access violations +system.cpu.dtb.read_accesses 956517 # DTB read accesses +system.cpu.dtb.write_hits 6638592 # DTB write hits +system.cpu.dtb.write_misses 9235 # DTB write misses +system.cpu.dtb.write_acv 315 # DTB write access violations +system.cpu.dtb.write_accesses 335365 # DTB write accesses +system.cpu.dtb.data_hits 16820082 # DTB hits +system.cpu.dtb.data_misses 52742 # DTB misses +system.cpu.dtb.data_acv 899 # DTB access violations +system.cpu.dtb.data_accesses 1291882 # DTB accesses +system.cpu.itb.fetch_hits 1343321 # ITB hits +system.cpu.itb.fetch_misses 39871 # ITB misses +system.cpu.itb.fetch_acv 1097 # ITB acv +system.cpu.itb.fetch_accesses 1383192 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.numCycles 117574512 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 14520870 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12129881 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 536127 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13102888 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 6784816 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6622434 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 12800990 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 39895 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 599479 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11925971 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14248722 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 975192 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 769874 # The number of times a branch was mispredicted -system.cpu.commit.branches 8461745 # Number of branches committed -system.cpu.commit.bw_lim_events 1125976 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 56284256 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667734 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8032073 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 87254730 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.645057 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459520 # Number of insts commited each cycle +system.cpu.BPredUnit.usedRAS 988023 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45439 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29297731 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 74578036 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14520870 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7772839 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 14464966 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2480365 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37381696 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 11813 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 262360 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 335674 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9188867 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 332159 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 83395171 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.894273 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.211331 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68930205 82.65% 82.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1027253 1.23% 83.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2037570 2.44% 86.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 996261 1.19% 87.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2986489 3.58% 91.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 701042 0.84% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 810374 0.97% 92.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1074366 1.29% 94.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4831611 5.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 83395171 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123504 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.634304 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30605129 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36986989 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 13179583 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1024525 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1598944 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 618757 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42149 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 72864512 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 127083 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1598944 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31853597 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12955306 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19880213 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 12336598 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4770511 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 68839007 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4216 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 997134 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1470879 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 46134135 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 83694616 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 83214897 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479719 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38263079 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7871048 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1701317 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251479 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12958659 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10852157 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7063465 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2081084 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2219281 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 60395993 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2119342 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 58286883 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 83117 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9015512 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4849087 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1451479 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 83395171 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.698924 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.313462 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56889866 68.22% 68.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11980340 14.37% 82.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5968113 7.16% 89.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3572850 4.28% 94.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2610876 3.13% 97.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1337370 1.60% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 787156 0.94% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 190323 0.23% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 58277 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 83395171 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 67430 12.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 313148 55.72% 67.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 181376 32.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39850306 68.37% 68.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 63779 0.11% 68.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25609 0.04% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10660229 18.29% 86.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6723519 11.54% 98.37% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952524 1.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 58286883 # Type of FU issued +system.cpu.iq.rate 0.495744 # Inst issue rate +system.cpu.iq.fu_busy_cnt 561954 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009641 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 199927311 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 71222511 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56715823 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 686696 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 334075 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327925 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58483404 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 358152 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 548522 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 1737768 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13937 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28744 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 670362 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 19001 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 170467 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 1598944 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9012018 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 624424 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 66178582 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 871819 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10852157 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7063465 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1871966 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 491038 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13897 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28744 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 390552 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 383693 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 774245 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57578164 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10255391 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 708718 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 3663247 # number of nop insts executed +system.cpu.iew.exec_refs 16918441 # number of memory reference insts executed +system.cpu.iew.exec_branches 9135643 # Number of branches executed +system.cpu.iew.exec_stores 6663050 # Number of stores executed +system.cpu.iew.exec_rate 0.489716 # Inst execution rate +system.cpu.iew.wb_sent 57177610 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 57043748 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28229071 # num instructions producing a value +system.cpu.iew.wb_consumers 38069273 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.485171 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.741519 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 56289833 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9752851 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667863 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 705919 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 81796227 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.688172 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.561050 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 64129239 73.50% 73.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 10001511 11.46% 84.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5794569 6.64% 91.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2584226 2.96% 94.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1856466 2.13% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 706744 0.81% 97.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 418456 0.48% 97.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 637543 0.73% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1125976 1.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59880576 73.21% 73.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9259582 11.32% 84.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5272761 6.45% 90.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2451209 3.00% 93.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1681883 2.06% 96.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 629564 0.77% 96.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 461991 0.56% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 785484 0.96% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1373177 1.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 87254730 # Number of insts commited each cycle -system.cpu.commit.count 56284256 # Number of instructions committed -system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. -system.cpu.commit.function_calls 744594 # Number of function calls committed. -system.cpu.commit.int_insts 52122555 # Number of committed integer instructions. -system.cpu.commit.loads 9113387 # Number of loads committed -system.cpu.commit.membars 227959 # Number of memory barriers committed -system.cpu.commit.refs 15505823 # Number of memory references committed +system.cpu.commit.committed_per_cycle::total 81796227 # Number of insts commited each cycle +system.cpu.commit.count 56289833 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 53089625 # Number of Instructions Simulated -system.cpu.committedInsts_total 53089625 # Number of Instructions Simulated -system.cpu.cpi 2.304358 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.304358 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 213395 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 213395 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14731.007611 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11798.670030 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 191452 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 191452 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 323242500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.102828 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 21943 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 21943 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4499 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 205816000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081745 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17444 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9261736 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9261736 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 21557.160878 # average ReadReq miss latency +system.cpu.commit.refs 15507492 # Number of memory references committed +system.cpu.commit.loads 9114389 # Number of loads committed +system.cpu.commit.membars 227923 # Number of memory barriers committed +system.cpu.commit.branches 8462531 # Number of branches committed +system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. +system.cpu.commit.int_insts 52127847 # Number of committed integer instructions. +system.cpu.commit.function_calls 744622 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1373177 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 146214633 # The number of ROB reads +system.cpu.rob.rob_writes 133687068 # The number of ROB writes +system.cpu.timesIdled 1253330 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34179341 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 53094994 # Number of Instructions Simulated +system.cpu.committedInsts_total 53094994 # Number of Instructions Simulated +system.cpu.cpi 2.214418 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.214418 # CPI: Total CPI of All Threads +system.cpu.ipc 0.451586 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.451586 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 75460784 # number of integer regfile reads +system.cpu.int_regfile_writes 41231418 # number of integer regfile writes +system.cpu.fp_regfile_reads 165968 # number of floating regfile reads +system.cpu.fp_regfile_writes 167480 # number of floating regfile writes +system.cpu.misc_regfile_reads 1996655 # number of misc regfile reads +system.cpu.misc_regfile_writes 950059 # number of misc regfile writes +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.cpu.icache.replacements 1005236 # number of replacements +system.cpu.icache.tagsinuse 509.950687 # Cycle average of tags in use +system.cpu.icache.total_refs 8124069 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1005745 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.077663 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23367185000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 509.950687 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.995997 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8124070 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8124070 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8124070 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8124070 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8124070 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 8124070 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1064797 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1064797 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1064797 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1064797 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1064797 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 1064797 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15924471495 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15924471495 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15924471495 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9188867 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9188867 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9188867 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9188867 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9188867 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9188867 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.115879 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.115879 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::0 0.115879 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::0 14955.406049 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::0 14955.406049 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14955.406049 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1315997 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 122 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10786.860656 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 236 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 58840 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 58840 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 58840 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1005957 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1005957 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1005957 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 12050949497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12050949497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12050949497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.109476 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.109476 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.109476 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11979.587097 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11979.587097 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11979.587097 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1403927 # number of replacements +system.cpu.dcache.tagsinuse 511.995946 # Cycle average of tags in use +system.cpu.dcache.total_refs 12182577 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1404439 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.674337 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 19464000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 511.995946 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 7545727 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7545727 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4224455 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4224455 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 192092 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192092 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 220106 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 220106 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 11770182 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11770182 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 11770182 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 11770182 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1787142 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1787142 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1933396 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1933396 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 23327 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23327 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::0 3720538 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3720538 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3720538 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 3720538 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 38546414500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 57324684255 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 362132500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency 95871098755 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 95871098755 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 9332869 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9332869 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6157851 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157851 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 215419 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 215419 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 220108 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220108 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 15490720 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15490720 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 15490720 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15490720 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.191489 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.313973 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.108287 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::0 0.240179 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::0 0.240179 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::0 21568.747475 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22806.773244 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7478882 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7478882 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 38433270500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.192497 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1782854 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1782854 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 698012 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24741745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117132 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1084842 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904671500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 219886 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219886 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 24500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 21375 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 219882 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 219882 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 98000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000018 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 85500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000018 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6157400 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157400 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 29663.792257 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 29649.737692 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28277.245454 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 4231311 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4231311 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 57135103964 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.312809 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 1926089 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1926089 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1626424 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 8473700759 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048667 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 299665 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235406998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8946.248648 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.647226 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 99695 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 891896259 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 24000 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15419136 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15419136 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 25767.010834 # average overall miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15524.177991 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::0 25768.074068 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23990.811357 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 11710193 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11710193 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 95568374464 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.240542 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 3708943 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3708943 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2324436 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 33215446259 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.089791 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1384507 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 511.995879 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses::0 15419136 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15419136 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 25767.010834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 25768.074068 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23990.811357 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 11710193 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11710193 # number of overall hits -system.cpu.dcache.overall_miss_latency 95568374464 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.240542 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 3708943 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3708943 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2324436 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 33215446259 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.089791 # mshr miss rate for overall accesses +system.cpu.dcache.blocked_cycles::no_mshrs 901455332 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 264000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 100284 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8989.024490 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 835363 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 699045 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1634457 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 5750 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2333502 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2333502 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1088097 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 298939 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 17577 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1387036 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1387036 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 24799761000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8488468332 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207628000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 33288229332 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33288229332 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904499500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234765498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 2139264998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116588 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048546 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081594 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.089540 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.089540 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1384507 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2140078498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1401285 # number of replacements -system.cpu.dcache.sampled_refs 1401797 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22791.865983 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28395.319219 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11812.482221 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23999.542429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23999.542429 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.995879 # Cycle average of tags in use -system.cpu.dcache.total_refs 12121656 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 19670000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 833416 # number of writebacks -system.cpu.decode.BlockedCycles 36259760 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 44553 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 598925 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 70789187 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 37160222 # Number of cycles decode is idle -system.cpu.decode.RunCycles 12840041 # Number of cycles decode is running -system.cpu.decode.SquashCycles 1435065 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 134914 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 994706 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1263492 # DTB accesses -system.cpu.dtb.data_acv 894 # DTB access violations -system.cpu.dtb.data_hits 16635681 # DTB hits -system.cpu.dtb.data_misses 51508 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 928978 # DTB read accesses -system.cpu.dtb.read_acv 572 # DTB read access violations -system.cpu.dtb.read_hits 10041253 # DTB read hits -system.cpu.dtb.read_misses 41018 # DTB read misses -system.cpu.dtb.write_accesses 334514 # DTB write accesses -system.cpu.dtb.write_acv 322 # DTB write access violations -system.cpu.dtb.write_hits 6594428 # DTB write hits -system.cpu.dtb.write_misses 10490 # DTB write misses -system.cpu.fetch.Branches 14248722 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8770990 # Number of cache lines fetched -system.cpu.fetch.Cycles 14042166 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 446901 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 72221007 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 40836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 893682 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.116471 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8770984 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7597626 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.590342 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 88689795 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.814310 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.123238 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 74647629 84.17% 84.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1010703 1.14% 85.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1983506 2.24% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 916230 1.03% 88.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2985219 3.37% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 672792 0.76% 92.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 771901 0.87% 93.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1056160 1.19% 94.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4645655 5.24% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 88689795 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 166013 # number of floating regfile reads -system.cpu.fp_regfile_writes 166759 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses::0 8770990 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8770990 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 15000.124864 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11953.663532 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 7733870 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7733870 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15556929499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.118244 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 1037120 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1037120 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 43680 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11875247499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.113264 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 993440 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs 12654.527273 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.786451 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 695999 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 8770990 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8770990 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 15000.124864 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11953.663532 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 7733870 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7733870 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15556929499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.118244 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 1037120 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1037120 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 43680 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11875247499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.113264 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 993440 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 509.827441 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.995757 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses::0 8770990 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8770990 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 15000.124864 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11953.663532 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 7733870 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7733870 # number of overall hits -system.cpu.icache.overall_miss_latency 15556929499 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.118244 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 1037120 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1037120 # number of overall misses -system.cpu.icache.overall_mshr_hits 43680 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11875247499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.113264 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 993440 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 992736 # number of replacements -system.cpu.icache.sampled_refs 993247 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.827441 # Cycle average of tags in use -system.cpu.icache.total_refs 7733869 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 23815676000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 201 # number of writebacks -system.cpu.idleCycles 33647698 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 834392 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 9077931 # Number of branches executed -system.cpu.iew.exec_nop 3561617 # number of nop insts executed -system.cpu.iew.exec_rate 0.466022 # Inst execution rate -system.cpu.iew.exec_refs 16730349 # number of memory reference insts executed -system.cpu.iew.exec_stores 6619936 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 9479709 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 10494692 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1785178 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 890339 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 6849187 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 64447431 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10110413 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 516805 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57012019 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 106234 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 12252 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1435065 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 608300 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 167273 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 486953 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 6665 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 18985 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 17936 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 1381305 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 456751 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 18985 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 404859 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 429533 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 36206464 # num instructions consuming a value -system.cpu.iew.wb_count 56518708 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.749991 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 27154531 # num instructions producing a value -system.cpu.iew.wb_rate 0.461990 # insts written-back per cycle -system.cpu.iew.wb_sent 56632372 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 74751539 # number of integer regfile reads -system.cpu.int_regfile_writes 40782350 # number of integer regfile writes -system.cpu.ipc 0.433960 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.433960 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39349401 68.40% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62002 0.11% 68.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25611 0.04% 68.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10457735 18.18% 86.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6670425 11.59% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952735 1.66% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57528826 # Type of FU issued -system.cpu.iq.fp_alu_accesses 358048 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 686320 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 327228 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 333627 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 549270 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009548 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45293 8.25% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 291133 53.00% 61.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 212842 38.75% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 57712767 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 203646640 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 56191480 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 67929762 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 58856413 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 57528826 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2029401 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 7361535 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 36245 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1361667 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3591759 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 88689795 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.648652 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.255048 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 61727681 69.60% 69.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 12782826 14.41% 84.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5739308 6.47% 90.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3779668 4.26% 94.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2566031 2.89% 97.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1197199 1.35% 98.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 667320 0.75% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 163755 0.18% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 66007 0.07% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 88689795 # Number of insts issued each cycle -system.cpu.iq.rate 0.470247 # Inst issue rate -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1283361 # ITB accesses -system.cpu.itb.fetch_acv 948 # ITB acv -system.cpu.itb.fetch_hits 1244403 # ITB hits -system.cpu.itb.fetch_misses 38958 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175553 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6791 3.53% 96.92% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5221 2.71% 99.64% # number of callpals executed -system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192522 # number of callpals executed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211679 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6434 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 74901 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 243 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1887 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105871 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182902 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73534 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211631 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74888 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 243 0.13% 41.09% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1884 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105841 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182856 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73521 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1887 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73537 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149201 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1824267875500 97.88% 97.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 98431000 0.01% 97.89% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 391220000 0.02% 97.91% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38943770500 2.09% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1863701297000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1884 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73524 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149172 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1821901267000 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94071500 0.01% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 385060500 0.02% 97.94% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38261139000 2.06% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860641538000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694591 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1907 -system.cpu.kern.mode_good::user 1737 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch::kernel 5958 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.320074 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.400796 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29982299000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2910857500 0.16% 1.76% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1830808132500 98.24% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.ipl_used::31 0.694665 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -589,322 +869,36 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.memDep0.conflictingLoads 1611665 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1565492 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 10494692 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6849187 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 1995286 # number of misc regfile reads -system.cpu.misc_regfile_writes 949727 # number of misc regfile writes -system.cpu.numCycles 122337493 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 12932543 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 38258765 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 1039474 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 38708983 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 1241691 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 1519 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 81518808 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 66985432 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 44869849 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 12449033 # Number of cycles rename is running -system.cpu.rename.SquashCycles 1435065 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 4145083 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 6611082 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 474213 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 81044595 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 19019086 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 1691185 # count of serializing insts renamed -system.cpu.rename.skidInsts 11218533 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 244825 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 150193940 # The number of ROB reads -system.cpu.rob.rob_writes 130068170 # The number of ROB writes -system.cpu.timesIdled 1318957 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137723.402147 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85719.890306 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5722682806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3561832882 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6163.814415 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64565956 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137630.264925 # average overall miss latency -system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85626.767645 # average overall mshr miss latency -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5742622804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3572776880 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_blocks::1 1.289021 # Average occupied blocks per context -system.iocache.occ_percent::1 0.080564 # Average percentage of cache occupancy -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137630.264925 # average overall miss latency -system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85626.767645 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5742622804 # number of overall miss cycles -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3572776880 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 41685 # number of replacements -system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.289021 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1710301197000 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 300895 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300895 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52473.313718 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40319.645209 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 183981 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183981 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6134865000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.388554 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 116914 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116914 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4713931000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.388554 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 116914 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2094150 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2094150 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52039.282964 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40022.101207 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1786383 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1786383 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16015974000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.146965 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 307767 # number of ReadReq misses -system.l2c.ReadReq_misses::total 307767 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12317442000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146965 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307766 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 809986500 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_miss_rate::0 0.250000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 40000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 1 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 38 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 38 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 14960 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 42440 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 374000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.657895 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 25 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 25 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 1061000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.657895 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1116065498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 833617 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 833617 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 833617 # number of Writeback hits -system.l2c.Writeback_hits::total 833617 # number of Writeback hits -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.655777 # Average number of references to valid blocks. -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2395045 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2395045 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52158.770936 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency -system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40104.014788 # average overall mshr miss latency -system.l2c.demand_hits::0 1970364 # number of demand (read+write) hits -system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1970364 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22150839000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.177317 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses -system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 424681 # number of demand (read+write) misses -system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 424681 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17031373000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.177316 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 424680 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 12180.929780 # Average occupied blocks per context -system.l2c.occ_blocks::1 22532.084945 # Average occupied blocks per context -system.l2c.occ_percent::0 0.185866 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.343812 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 2395045 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2395045 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52158.770936 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency -system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40104.014788 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1970364 # number of overall hits -system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1970364 # number of overall hits -system.l2c.overall_miss_latency 22150839000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.177317 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses -system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 424681 # number of overall misses -system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 424681 # number of overall misses -system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17031373000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.177316 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 424680 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1926051998 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 390703 # number of replacements -system.l2c.sampled_refs 423923 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 34713.014726 # Cycle average of tags in use -system.l2c.total_refs 2397614 # Total number of references to valid blocks. -system.l2c.warmup_cycle 5626579000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 117022 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpipl 175513 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6789 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal::rti 5218 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed +system.cpu.kern.callpal::total 192477 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1737 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.320235 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.400957 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29480216500 1.58% 1.58% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2869428500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1828291885000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |