diff options
Diffstat (limited to 'tests/long/10.linux-boot/ref')
12 files changed, 2263 insertions, 2259 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 80aefb4cf..1b7aa47b5 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -10,12 +10,12 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/chips/pd/randd/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/chips/pd/randd/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -926,7 +926,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -946,7 +946,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1074,7 +1074,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 66e1dd01f..c0c960a9c 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,13 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 15 2011 18:10:57 -M5 revision ee89694ad8dc 8081 default ext/mem_block_transfer_O3_regressions.patch tip qtip -M5 started Mar 15 2011 18:10:59 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Mar 17 2011 22:48:41 +M5 started Mar 17 2011 22:50:14 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 118370500 -Exiting @ tick 1900831106500 because m5_exit instruction encountered +info: Launching CPU 1 @ 109002500 +Exiting @ tick 1901725056500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 6dbfe53f2..1aa5f5dbb 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,504 +1,504 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 185731 # Simulator instruction rate (inst/s) -host_mem_usage 330796 # Number of bytes of host memory used -host_seconds 306.85 # Real time elapsed on the host -host_tick_rate 6194726969 # Simulator tick rate (ticks/s) +host_inst_rate 127019 # Simulator instruction rate (inst/s) +host_mem_usage 296760 # Number of bytes of host memory used +host_seconds 449.39 # Real time elapsed on the host +host_tick_rate 4231820542 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56990828 # Number of instructions simulated -sim_seconds 1.900831 # Number of seconds simulated -sim_ticks 1900831106500 # Number of ticks simulated +sim_insts 57080594 # Number of instructions simulated +sim_seconds 1.901725 # Number of seconds simulated +sim_ticks 1901725056500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 5875746 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 11164335 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 27734 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 509345 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 10431005 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 12489231 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 879926 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 7522155 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 922955 # number cycles where commit BW limit reached +system.cpu0.BPredUnit.BTBHits 5478793 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 10568954 # Number of BTB lookups +system.cpu0.BPredUnit.RASInCorrect 28086 # Number of incorrect RAS predictions. +system.cpu0.BPredUnit.condIncorrect 455851 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 9912652 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 11764241 # Number of BP lookups +system.cpu0.BPredUnit.usedRAS 785162 # Number of times the RAS was used to get a target. +system.cpu0.commit.COM:branches 7026012 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 938799 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 78251630 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.636074 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 1.403101 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 72953049 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.644604 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 1.459058 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0 56997001 72.84% 72.84% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1 9309948 11.90% 84.74% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2 5423861 6.93% 91.67% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3 2443172 3.12% 94.79% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4 1857246 2.37% 97.16% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5 632479 0.81% 97.97% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6 343172 0.44% 98.41% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7 321796 0.41% 98.82% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 922955 1.18% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0 53597246 73.47% 73.47% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1 8417746 11.54% 85.01% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2 4840163 6.63% 91.64% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3 2111570 2.89% 94.54% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4 1587453 2.18% 96.71% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5 575078 0.79% 97.50% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6 337488 0.46% 97.96% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7 547506 0.75% 98.71% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 938799 1.29% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 78251630 # Number of insts commited each cycle -system.cpu0.commit.COM:count 49773809 # Number of instructions committed -system.cpu0.commit.COM:fp_insts 245595 # Number of committed floating point instructions. -system.cpu0.commit.COM:function_calls 636047 # Number of function calls committed. -system.cpu0.commit.COM:int_insts 46098602 # Number of committed integer instructions. -system.cpu0.commit.COM:loads 7894859 # Number of loads committed -system.cpu0.commit.COM:membars 191655 # Number of memory barriers committed -system.cpu0.commit.COM:refs 13318738 # Number of memory references committed +system.cpu0.commit.COM:committed_per_cycle::total 72953049 # Number of insts commited each cycle +system.cpu0.commit.COM:count 47025846 # Number of instructions committed +system.cpu0.commit.COM:fp_insts 287589 # Number of committed floating point instructions. +system.cpu0.commit.COM:function_calls 606692 # Number of function calls committed. +system.cpu0.commit.COM:int_insts 43528406 # Number of committed integer instructions. +system.cpu0.commit.COM:loads 7569996 # Number of loads committed +system.cpu0.commit.COM:membars 198353 # Number of memory barriers committed +system.cpu0.commit.COM:refs 12959088 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 652841 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 49773809 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 564763 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 7279602 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 46913237 # Number of Instructions Simulated -system.cpu0.committedInsts_total 46913237 # Number of Instructions Simulated -system.cpu0.cpi 2.403611 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.403611 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses::0 178261 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 178261 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14383.272201 # average LoadLockedReq miss latency +system.cpu0.commit.branchMispredicts 606344 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 47025846 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 585526 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 5969393 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 44336308 # Number of Instructions Simulated +system.cpu0.committedInsts_total 44336308 # Number of Instructions Simulated +system.cpu0.cpi 2.365714 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.365714 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses::0 187921 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 187921 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 13445.030972 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10560.425277 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 158904 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 158904 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 278417000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108588 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 19357 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19357 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 4355 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158427500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084157 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10250.543228 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::0 169356 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 169356 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 249607000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.098792 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 18565 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18565 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 3378 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 155675000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.080816 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 15002 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 8017759 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8017759 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 23757.902186 # average ReadReq miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses 15187 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::0 7569121 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7569121 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 24067.489407 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.503104 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 26547.034409 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 6640640 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6640640 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 32717458500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.171759 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 1377119 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1377119 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 391971 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 23413523000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122871 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits::0 6281230 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6281230 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 30996303000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::0 0.170151 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1287891 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1287891 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 494238 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 21069133500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.104854 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 985148 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920844000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 185114 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 185114 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13326.438356 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_mshr_misses 793653 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 636739500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses::0 196148 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 196148 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 12580.258745 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10323.150685 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 181464 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 181464 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 48641500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019718 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 3650 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3650 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37679500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019718 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 9578.581696 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits::0 191974 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191974 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 52510000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.021280 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 4174 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4174 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 39981000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.021280 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 3650 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 5223711 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5223711 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 32402.197389 # average WriteReq miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses 4174 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses::0 5179136 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5179136 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 31904.477186 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30590.574400 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30396.485851 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 3607020 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3607020 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 52384340899 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.309491 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 1616691 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1616691 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1353284 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 8057771431 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050425 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_hits::0 3600390 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3600390 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 50369065740 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::0 0.304828 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 1578746 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1578746 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1328268 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 7613650983 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.048363 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 263407 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320171998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8769.741125 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 8.499136 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 83743 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 734404431 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 150500 # number of cycles access was blocked +system.cpu0.dcache.WriteReq_mshr_misses 250478 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1111159498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8752.803276 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 9.840448 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 95418 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 835174983 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 13241470 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::0 12748257 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13241470 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 28425.918612 # average overall miss latency +system.cpu0.dcache.demand_accesses::total 12748257 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 28383.561902 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 25206.173882 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 10247660 # number of demand (read+write) hits +system.cpu0.dcache.demand_avg_mshr_miss_latency 27470.484530 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::0 9881620 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10247660 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 85101799399 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.226093 # miss rate for demand accesses +system.cpu0.dcache.demand_hits::total 9881620 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 81365368740 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::0 0.224865 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 2993810 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 2866637 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2993810 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1745255 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 31471294431 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.094291 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_misses::total 2866637 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1822506 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 28682784483 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0.081904 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1248555 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses 1044131 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.973190 # Average percentage of cache occupancy +system.cpu0.dcache.occ_%::0 0.956764 # Average percentage of cache occupancy system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 498.273055 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 489.863061 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses::0 13241470 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::0 12748257 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13241470 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 28425.918612 # average overall miss latency +system.cpu0.dcache.overall_accesses::total 12748257 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 28383.561902 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 25206.173882 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 27470.484530 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 10247660 # number of overall hits +system.cpu0.dcache.overall_hits::0 9881620 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 10247660 # number of overall hits -system.cpu0.dcache.overall_miss_latency 85101799399 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.226093 # miss rate for overall accesses +system.cpu0.dcache.overall_hits::total 9881620 # number of overall hits +system.cpu0.dcache.overall_miss_latency 81365368740 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate::0 0.224865 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 2993810 # number of overall misses +system.cpu0.dcache.overall_misses::0 2866637 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2993810 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1745255 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 31471294431 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.094291 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_misses::total 2866637 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1822506 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 28682784483 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate::0 0.081904 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1248555 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2241015998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_misses 1044131 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 1747898998 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 1246755 # number of replacements -system.cpu0.dcache.sampled_refs 1247267 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1041325 # number of replacements +system.cpu0.dcache.sampled_refs 1041715 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 497.273055 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10600692 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 488.863062 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10250942 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 721595 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 33789769 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 33336 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 520770 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 62593203 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 32176765 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 11304168 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1271210 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 100660 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 980927 # Number of cycles decode is unblocking -system.cpu0.dtb.data_accesses 794756 # DTB accesses -system.cpu0.dtb.data_acv 688 # DTB access violations -system.cpu0.dtb.data_hits 14240512 # DTB hits -system.cpu0.dtb.data_misses 32288 # DTB misses +system.cpu0.dcache.writebacks 532971 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 30335443 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 32433 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 467445 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 58302731 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 31236137 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 10506640 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1085015 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 96992 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 874828 # Number of cycles decode is unblocking +system.cpu0.dtb.data_accesses 755162 # DTB accesses +system.cpu0.dtb.data_acv 768 # DTB access violations +system.cpu0.dtb.data_hits 13777358 # DTB hits +system.cpu0.dtb.data_misses 33542 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 599054 # DTB read accesses -system.cpu0.dtb.read_acv 519 # DTB read access violations -system.cpu0.dtb.read_hits 8656143 # DTB read hits -system.cpu0.dtb.read_misses 26649 # DTB read misses -system.cpu0.dtb.write_accesses 195702 # DTB write accesses -system.cpu0.dtb.write_acv 169 # DTB write access violations -system.cpu0.dtb.write_hits 5584369 # DTB write hits -system.cpu0.dtb.write_misses 5639 # DTB write misses -system.cpu0.fetch.Branches 12489231 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 7790870 # Number of cache lines fetched -system.cpu0.fetch.Cycles 12447773 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 374462 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 63680808 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 30775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 745389 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.110758 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 7790867 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 6755672 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.564741 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 79522840 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.800786 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.103997 # Number of instructions fetched each cycle (Total) +system.cpu0.dtb.read_accesses 569569 # DTB read accesses +system.cpu0.dtb.read_acv 514 # DTB read access violations +system.cpu0.dtb.read_hits 8255195 # DTB read hits +system.cpu0.dtb.read_misses 26791 # DTB read misses +system.cpu0.dtb.write_accesses 185593 # DTB write accesses +system.cpu0.dtb.write_acv 254 # DTB write access violations +system.cpu0.dtb.write_hits 5522163 # DTB write hits +system.cpu0.dtb.write_misses 6751 # DTB write misses +system.cpu0.fetch.Branches 11764241 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 7276849 # Number of cache lines fetched +system.cpu0.fetch.Cycles 11546182 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 354114 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 59401999 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 28935 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 709322 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.112161 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 7276849 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 6263955 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.566343 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 74038064 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.802317 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.109343 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67075067 84.35% 84.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 894690 1.13% 85.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1774768 2.23% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 813051 1.02% 88.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2745482 3.45% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 583376 0.73% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 681368 0.86% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 829891 1.04% 94.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4125147 5.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 62491882 84.41% 84.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 859667 1.16% 85.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1580756 2.14% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 707840 0.96% 88.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2540715 3.43% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 543724 0.73% 92.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 599348 0.81% 93.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 933324 1.26% 94.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3780808 5.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79522840 # Number of instructions fetched each cycle (Total) -system.cpu0.fp_regfile_reads 120909 # number of floating regfile reads -system.cpu0.fp_regfile_writes 122710 # number of floating regfile writes -system.cpu0.icache.ReadReq_accesses::0 7790870 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7790870 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.877874 # average ReadReq miss latency +system.cpu0.fetch.rateDist::total 74038064 # Number of instructions fetched each cycle (Total) +system.cpu0.fp_regfile_reads 141418 # number of floating regfile reads +system.cpu0.fp_regfile_writes 143630 # number of floating regfile writes +system.cpu0.icache.ReadReq_accesses::0 7276849 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7276849 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 14969.786485 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12016.582299 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 6933419 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6933419 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 12919109500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.110058 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 857451 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 857451 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 36636 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 9863391000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.105356 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11880.005982 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits::0 6407354 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6407354 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 13016154500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate::0 0.119488 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 869495 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 869495 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 30374 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 9968762500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.115314 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 820815 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11214.285714 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_mshr_misses 839121 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11944.444444 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 8.448187 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 56 # number of cycles access was blocked +system.cpu0.icache.avg_refs 7.637231 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 36 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 628000 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 430000 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 7790870 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::0 7276849 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7790870 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 15066.877874 # average overall miss latency +system.cpu0.icache.demand_accesses::total 7276849 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 14969.786485 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12016.582299 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 6933419 # number of demand (read+write) hits +system.cpu0.icache.demand_avg_mshr_miss_latency 11880.005982 # average overall mshr miss latency +system.cpu0.icache.demand_hits::0 6407354 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6933419 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 12919109500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.110058 # miss rate for demand accesses +system.cpu0.icache.demand_hits::total 6407354 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 13016154500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::0 0.119488 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 857451 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::0 869495 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 857451 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 36636 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 9863391000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.105356 # mshr miss rate for demand accesses +system.cpu0.icache.demand_misses::total 869495 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 30374 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 9968762500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0.115314 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 820815 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses 839121 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.995823 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 509.861442 # Average occupied blocks per context -system.cpu0.icache.overall_accesses::0 7790870 # number of overall (read+write) accesses +system.cpu0.icache.occ_%::0 0.995851 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 509.875783 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 7276849 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7790870 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 15066.877874 # average overall miss latency +system.cpu0.icache.overall_accesses::total 7276849 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 14969.786485 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12016.582299 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11880.005982 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 6933419 # number of overall hits +system.cpu0.icache.overall_hits::0 6407354 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 6933419 # number of overall hits -system.cpu0.icache.overall_miss_latency 12919109500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.110058 # miss rate for overall accesses +system.cpu0.icache.overall_hits::total 6407354 # number of overall hits +system.cpu0.icache.overall_miss_latency 13016154500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::0 0.119488 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 857451 # number of overall misses +system.cpu0.icache.overall_misses::0 869495 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 857451 # number of overall misses -system.cpu0.icache.overall_mshr_hits 36636 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 9863391000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.105356 # mshr miss rate for overall accesses +system.cpu0.icache.overall_misses::total 869495 # number of overall misses +system.cpu0.icache.overall_mshr_hits 30374 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 9968762500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::0 0.115314 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 820815 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses 839121 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 820188 # number of replacements -system.cpu0.icache.sampled_refs 820699 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 838452 # number of replacements +system.cpu0.icache.sampled_refs 838963 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.861442 # Cycle average of tags in use -system.cpu0.icache.total_refs 6933419 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 24435382000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 160 # number of writebacks -system.cpu0.idleCycles 33238338 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 8088609 # Number of branches executed -system.cpu0.iew.EXEC:nop 3190653 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.446643 # Inst execution rate -system.cpu0.iew.EXEC:refs 14307346 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 5602769 # Number of stores executed +system.cpu0.icache.tagsinuse 509.875783 # Cycle average of tags in use +system.cpu0.icache.total_refs 6407354 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23816238000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 147 # number of writebacks +system.cpu0.idleCycles 30848962 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 7463719 # Number of branches executed +system.cpu0.iew.EXEC:nop 2952874 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.449724 # Inst execution rate +system.cpu0.iew.EXEC:refs 13848442 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 5542976 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 31606079 # num instructions consuming a value -system.cpu0.iew.WB:count 49988014 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.757991 # average fanout of values written-back +system.cpu0.iew.WB:consumers 29600256 # num instructions consuming a value +system.cpu0.iew.WB:count 46794498 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.755402 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 23957137 # num instructions producing a value -system.cpu0.iew.WB:rate 0.443309 # insts written-back per cycle -system.cpu0.iew.WB:sent 50069991 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 711883 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 9018658 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 9134985 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1511781 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 755973 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 5843371 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 57163675 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 8704577 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 462590 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 50363992 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 59575 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 22360092 # num instructions producing a value +system.cpu0.iew.WB:rate 0.446142 # insts written-back per cycle +system.cpu0.iew.WB:sent 46875004 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 654991 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 7417251 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 8574378 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1551984 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 727686 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 5707393 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 53103916 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 8305466 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 392048 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 47170169 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 90492 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 7002 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1271210 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 547356 # Number of cycles IEW is unblocking +system.cpu0.iew.iewLSQFullEvents 5675 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1085015 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 526785 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 122264 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 410769 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 10661 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.cacheBlocked 157871 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 427137 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 7542 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 38527 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 18607 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1240126 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 419492 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 38527 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 332123 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 379760 # Number of branches that were predicted taken incorrectly -system.cpu0.int_regfile_reads 66329017 # number of integer regfile reads -system.cpu0.int_regfile_writes 36275514 # number of integer regfile writes -system.cpu0.ipc 0.416041 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.416041 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35321880 69.49% 69.50% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 55711 0.11% 69.61% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15323 0.03% 69.64% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.64% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.64% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.64% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1880 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 9003030 17.71% 87.36% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645816 11.11% 98.47% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779182 1.53% 100.00% # Type of FU issued +system.cpu0.iew.lsq.thread.0.memOrderViolation 14768 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 12869 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1004382 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 318301 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 14768 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 331464 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 323527 # Number of branches that were predicted taken incorrectly +system.cpu0.int_regfile_reads 61873527 # number of integer regfile reads +system.cpu0.int_regfile_writes 33807346 # number of integer regfile writes +system.cpu0.ipc 0.422705 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.422705 # IPC: Total IPC of All Threads +system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3310 0.01% 0.01% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 32518161 68.37% 68.38% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 52150 0.11% 68.49% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.49% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15557 0.03% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1653 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 8591465 18.06% 86.59% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5582440 11.74% 98.32% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IprAccess 797481 1.68% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 50826584 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 382291 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.007521 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 47562217 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 465945 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.009797 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 40945 10.71% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 226304 59.20% 69.91% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 115042 30.09% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 32168 6.90% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 239318 51.36% 58.27% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 194459 41.73% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 79522840 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.639144 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.209964 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 74038064 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.642402 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.245120 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0 54765189 68.87% 68.87% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1 12085919 15.20% 84.07% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2 5449520 6.85% 90.92% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3 3416832 4.30% 95.21% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4 2223696 2.80% 98.01% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5 992162 1.25% 99.26% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6 434798 0.55% 99.81% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7 111045 0.14% 99.95% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 43679 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0 51535584 69.61% 69.61% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1 10789742 14.57% 84.18% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2 4855288 6.56% 90.74% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3 3076859 4.16% 94.89% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4 2068166 2.79% 97.69% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5 951116 1.28% 98.97% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6 576531 0.78% 99.75% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7 134332 0.18% 99.93% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 50446 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 79522840 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.450745 # Inst issue rate -system.cpu0.iq.fp_alu_accesses 260468 # Number of floating point alu accesses -system.cpu0.iq.fp_inst_queue_reads 508171 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_wakeup_accesses 246837 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_writes 251931 # Number of floating instruction queue writes -system.cpu0.iq.int_alu_accesses 50944645 # Number of integer alu accesses -system.cpu0.iq.int_inst_queue_reads 181074223 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_wakeup_accesses 49741177 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.int_inst_queue_writes 60494022 # Number of integer instruction queue writes -system.cpu0.iq.iqInstsAdded 52251057 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 50826584 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1721965 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 6740106 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 24097 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 1157202 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3425536 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.ISSUE:issued_per_cycle::total 74038064 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.453461 # Inst issue rate +system.cpu0.iq.fp_alu_accesses 318343 # Number of floating point alu accesses +system.cpu0.iq.fp_inst_queue_reads 608219 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_wakeup_accesses 289004 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_writes 292979 # Number of floating instruction queue writes +system.cpu0.iq.int_alu_accesses 47706509 # Number of integer alu accesses +system.cpu0.iq.int_inst_queue_reads 169046393 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_wakeup_accesses 46505494 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.int_inst_queue_writes 55364625 # Number of integer instruction queue writes +system.cpu0.iq.iqInstsAdded 48386629 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 47562217 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1764413 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 5493402 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 26169 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 1178887 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 2580822 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 951932 # ITB accesses -system.cpu0.itb.fetch_acv 733 # ITB acv -system.cpu0.itb.fetch_hits 923000 # ITB hits -system.cpu0.itb.fetch_misses 28932 # ITB misses +system.cpu0.itb.fetch_accesses 933233 # ITB accesses +system.cpu0.itb.fetch_acv 717 # ITB acv +system.cpu0.itb.fetch_hits 905545 # ITB hits +system.cpu0.itb.fetch_misses 27688 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_hits 0 # DTB read hits @@ -508,613 +508,613 @@ system.cpu0.itb.write_acv 0 # DT system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 351 0.22% 0.22% # number of callpals executed +system.cpu0.kern.callpal::wripir 371 0.22% 0.22% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.22% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.22% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.22% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3287 2.03% 2.25% # number of callpals executed -system.cpu0.kern.callpal::tbi 43 0.03% 2.27% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed -system.cpu0.kern.callpal::swpipl 147044 90.75% 93.03% # number of callpals executed -system.cpu0.kern.callpal::rdps 6369 3.93% 96.96% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.96% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 96.96% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed -system.cpu0.kern.callpal::rti 4450 2.75% 99.71% # number of callpals executed -system.cpu0.kern.callpal::callsys 330 0.20% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 162036 # number of callpals executed +system.cpu0.kern.callpal::swpctx 3671 2.19% 2.42% # number of callpals executed +system.cpu0.kern.callpal::tbi 42 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpipl 151594 90.58% 93.02% # number of callpals executed +system.cpu0.kern.callpal::rdps 6330 3.78% 96.81% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.81% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 96.81% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 96.81% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.81% # number of callpals executed +system.cpu0.kern.callpal::rti 4884 2.92% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 315 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 135 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 167365 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 176105 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6624 # number of quiesce instructions executed -system.cpu0.kern.ipl_count::0 62137 40.37% 40.37% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 238 0.15% 40.53% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.25% 41.78% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 254 0.17% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 89358 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 153912 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 61267 49.13% 49.13% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 238 0.19% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.54% 50.87% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 254 0.20% 51.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 61013 48.93% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 124697 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862707102000 97.99% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 96290500 0.01% 98.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 398437500 0.02% 98.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 103382500 0.01% 98.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 37525043500 1.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1900830256000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.985999 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 180838 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 5105 # number of quiesce instructions executed +system.cpu0.kern.ipl_count::0 63498 39.95% 39.95% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 238 0.15% 40.10% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.21% 41.31% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 288 0.18% 41.50% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 92981 58.50% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 158931 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 62140 49.14% 49.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 238 0.19% 49.33% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.52% 50.86% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 288 0.23% 51.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 61852 48.92% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 126444 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864722249000 98.07% 98.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 96095500 0.01% 98.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 397148000 0.02% 98.10% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 112025000 0.01% 98.10% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 36054288500 1.90% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1901381806000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.978613 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682793 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good::kernel 1171 -system.cpu0.kern.mode_good::user 1172 +system.cpu0.kern.ipl_used::31 0.665211 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1076 +system.cpu0.kern.mode_good::user 1076 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch::kernel 6890 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1172 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 7211 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1076 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.169956 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.149216 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1898861301500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1968946500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1899282367000 99.91% 99.91% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1748332500 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3288 # number of times the context was actually changed -system.cpu0.kern.syscall::2 6 2.99% 2.99% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.46% 11.44% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.49% 12.94% # number of syscalls executed -system.cpu0.kern.syscall::6 27 13.43% 26.37% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.50% 26.87% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.48% 31.34% # number of syscalls executed -system.cpu0.kern.syscall::19 6 2.99% 34.33% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.99% 36.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.50% 36.82% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.49% 38.31% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.48% 41.79% # number of syscalls executed -system.cpu0.kern.syscall::41 2 1.00% 42.79% # number of syscalls executed -system.cpu0.kern.syscall::45 36 17.91% 60.70% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.49% 62.19% # number of syscalls executed -system.cpu0.kern.syscall::48 7 3.48% 65.67% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.48% 70.15% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.50% 70.65% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.49% 73.13% # number of syscalls executed -system.cpu0.kern.syscall::71 27 13.43% 86.57% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.49% 88.06% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.48% 91.54% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.50% 92.04% # number of syscalls executed -system.cpu0.kern.syscall::90 1 0.50% 92.54% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.48% 96.02% # number of syscalls executed -system.cpu0.kern.syscall::97 2 1.00% 97.01% # number of syscalls executed -system.cpu0.kern.syscall::98 2 1.00% 98.01% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.50% 99.00% # number of syscalls executed -system.cpu0.kern.syscall::147 2 1.00% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 201 # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 2323915 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1919788 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 9134985 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5843371 # Number of stores inserted to the mem dependence unit. -system.cpu0.misc_regfile_reads 1626355 # number of misc regfile reads -system.cpu0.misc_regfile_writes 787160 # number of misc regfile writes -system.cpu0.numCycles 112761178 # number of cpu cycles simulated +system.cpu0.kern.swap_context 3672 # number of times the context was actually changed +system.cpu0.kern.syscall::2 6 3.17% 3.17% # number of syscalls executed +system.cpu0.kern.syscall::3 16 8.47% 11.64% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.59% 13.23% # number of syscalls executed +system.cpu0.kern.syscall::6 26 13.76% 26.98% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.53% 27.51% # number of syscalls executed +system.cpu0.kern.syscall::17 8 4.23% 31.75% # number of syscalls executed +system.cpu0.kern.syscall::19 6 3.17% 34.92% # number of syscalls executed +system.cpu0.kern.syscall::20 4 2.12% 37.04% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.53% 37.57% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.59% 39.15% # number of syscalls executed +system.cpu0.kern.syscall::33 6 3.17% 42.33% # number of syscalls executed +system.cpu0.kern.syscall::41 2 1.06% 43.39% # number of syscalls executed +system.cpu0.kern.syscall::45 33 17.46% 60.85% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.59% 62.43% # number of syscalls executed +system.cpu0.kern.syscall::48 7 3.70% 66.14% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.76% 70.90% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.53% 71.43% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.65% 74.07% # number of syscalls executed +system.cpu0.kern.syscall::71 23 12.17% 86.24% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.59% 87.83% # number of syscalls executed +system.cpu0.kern.syscall::74 6 3.17% 91.01% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.53% 91.53% # number of syscalls executed +system.cpu0.kern.syscall::90 1 0.53% 92.06% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.70% 95.77% # number of syscalls executed +system.cpu0.kern.syscall::97 2 1.06% 96.83% # number of syscalls executed +system.cpu0.kern.syscall::98 2 1.06% 97.88% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.53% 98.41% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.53% 98.94% # number of syscalls executed +system.cpu0.kern.syscall::147 2 1.06% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 189 # number of syscalls executed +system.cpu0.memDep0.conflictingLoads 1239149 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1190008 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 8574378 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5707393 # Number of stores inserted to the mem dependence unit. +system.cpu0.misc_regfile_reads 1734015 # number of misc regfile reads +system.cpu0.misc_regfile_writes 822223 # number of misc regfile writes +system.cpu0.numCycles 104887026 # number of cpu cycles simulated system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.rename.RENAME:BlockCycles 12784143 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 33979065 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 1006573 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 33581705 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1371242 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 43321 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 72539076 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 59327188 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 39979686 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 11035795 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1271210 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 3987790 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 6000619 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:fp_rename_lookups 358919 # Number of floating rename lookups -system.cpu0.rename.RENAME:int_rename_lookups 72180157 # Number of integer rename lookups -system.cpu0.rename.RENAME:serializeStallCycles 16862195 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1393628 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 10087517 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 207585 # count of temporary serializing insts renamed -system.cpu0.rob.rob_reads 134196797 # The number of ROB reads -system.cpu0.rob.rob_writes 115377386 # The number of ROB writes -system.cpu0.timesIdled 1187168 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.rename.RENAME:BlockCycles 10226952 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 32010277 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 742771 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 32554760 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1133948 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 1272 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 67011150 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 55116446 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 36911598 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 10340148 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1085015 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3374476 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 4901321 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:fp_rename_lookups 420638 # Number of floating rename lookups +system.cpu0.rename.RENAME:int_rename_lookups 66590512 # Number of integer rename lookups +system.cpu0.rename.RENAME:serializeStallCycles 16456711 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1432211 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 8924178 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 217463 # count of temporary serializing insts renamed +system.cpu0.rob.rob_reads 124831913 # The number of ROB reads +system.cpu0.rob.rob_writes 107074537 # The number of ROB writes +system.cpu0.timesIdled 1083848 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 1161804 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 2701483 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 8265 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 107435 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 2484023 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 2997822 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 209923 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 1520807 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 198341 # number cycles where commit BW limit reached +system.cpu1.BPredUnit.BTBHits 1509705 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 3127444 # Number of BTB lookups +system.cpu1.BPredUnit.RASInCorrect 7361 # Number of incorrect RAS predictions. +system.cpu1.BPredUnit.condIncorrect 156935 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 2982175 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 3622579 # Number of BP lookups +system.cpu1.BPredUnit.usedRAS 265553 # Number of times the RAS was used to get a target. +system.cpu1.commit.COM:branches 2030517 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 301379 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 17840200 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.594448 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.407345 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 21012360 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.640018 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.474919 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0 13454331 75.42% 75.42% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1 2070557 11.61% 87.02% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2 797281 4.47% 91.49% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3 568657 3.19% 94.68% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4 399402 2.24% 96.92% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5 150078 0.84% 97.76% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6 111624 0.63% 98.38% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7 89929 0.50% 98.89% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 198341 1.11% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0 15563519 74.07% 74.07% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1 2436778 11.60% 85.67% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2 1200178 5.71% 91.38% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3 640529 3.05% 94.43% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4 421093 2.00% 96.43% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5 209093 1.00% 97.42% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6 129842 0.62% 98.04% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7 109949 0.52% 98.57% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 301379 1.43% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 17840200 # Number of insts commited each cycle -system.cpu1.commit.COM:count 10605063 # Number of instructions committed -system.cpu1.commit.COM:fp_insts 116296 # Number of committed floating point instructions. -system.cpu1.commit.COM:function_calls 166623 # Number of function calls committed. -system.cpu1.commit.COM:int_insts 9814594 # Number of committed integer instructions. -system.cpu1.commit.COM:loads 1991971 # Number of loads committed -system.cpu1.commit.COM:membars 52733 # Number of memory barriers committed -system.cpu1.commit.COM:refs 3376356 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 21012360 # Number of insts commited each cycle +system.cpu1.commit.COM:count 13448285 # Number of instructions committed +system.cpu1.commit.COM:fp_insts 77652 # Number of committed floating point instructions. +system.cpu1.commit.COM:function_calls 196980 # Number of function calls committed. +system.cpu1.commit.COM:int_insts 12472477 # Number of committed integer instructions. +system.cpu1.commit.COM:loads 2329401 # Number of loads committed +system.cpu1.commit.COM:membars 46552 # Number of memory barriers committed +system.cpu1.commit.COM:refs 3759357 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 164474 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 10605063 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 163004 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 1721637 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 10077591 # Number of Instructions Simulated -system.cpu1.committedInsts_total 10077591 # Number of Instructions Simulated -system.cpu1.cpi 1.948947 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.948947 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses::0 46373 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 46373 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11076.917360 # average LoadLockedReq miss latency +system.cpu1.commit.branchMispredicts 207236 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 13448285 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 143621 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 2329974 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 12744286 # Number of Instructions Simulated +system.cpu1.committedInsts_total 12744286 # Number of Instructions Simulated +system.cpu1.cpi 1.922547 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.922547 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses::0 34084 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 34084 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 12032.319953 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7999.664711 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 39645 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 39645 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 74525500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145084 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 6728 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 6728 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 763 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47718000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128631 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7746.929907 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::0 27308 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 27308 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 81531000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.198803 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 6776 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 6776 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 1483 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 41004500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.155293 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 5965 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 2063020 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2063020 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15006.932779 # average ReadReq miss latency +system.cpu1.dcache.LoadLockedReq_mshr_misses 5293 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::0 2478047 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2478047 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15160.837325 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11671.409798 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12203.806584 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 1868365 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1868365 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 2921174500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.094354 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 194655 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 194655 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 99535 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 1110184500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046107 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits::0 2047581 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2047581 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 6526225000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::0 0.173712 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 430466 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 430466 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 150924 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 3411476500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.112807 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 95120 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 17677500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 43196 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 43196 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13132.452048 # average StoreCondReq miss latency +system.cpu1.dcache.ReadReq_mshr_misses 279542 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 299904000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses::0 32610 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 32610 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13453.081410 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10137.707469 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 39338 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 39338 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 50665000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089314 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 3858 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3858 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 39091000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089268 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10450.798884 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits::0 28667 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 28667 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 53045500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.120914 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 3943 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3943 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 41207500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.120914 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 3856 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 1334800 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1334800 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 21239.554449 # average WriteReq miss latency +system.cpu1.dcache.StoreCondReq_mshr_misses 3943 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses::0 1389552 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1389552 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 29195.465224 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18778.969096 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26358.387662 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 1085291 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1085291 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 5299459991 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.186926 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 249509 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 249509 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 201036 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 910272969 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.036315 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_hits::0 1086825 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1086825 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 8838255601 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::0 0.217859 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 302727 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 302727 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 250029 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 1389034313 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.037924 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 48473 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377656000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9801.734092 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 22.873773 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 5359 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 52527493 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.WriteReq_mshr_misses 52698 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 600087500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12134.424364 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 11000 # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 9.983135 # Average number of references to valid blocks. +system.cpu1.dcache.blocked::no_mshrs 9506 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 115349838 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 11000 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 3397820 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::0 3867599 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3397820 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 18508.106220 # average overall miss latency +system.cpu1.dcache.demand_accesses::total 3867599 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 20955.574591 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14070.723984 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 2953656 # number of demand (read+write) hits +system.cpu1.dcache.demand_avg_mshr_miss_latency 14448.924913 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::0 3134406 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2953656 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 8220634491 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.130720 # miss rate for demand accesses +system.cpu1.dcache.demand_hits::total 3134406 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 15364480601 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::0 0.189573 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 444164 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 733193 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 444164 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 300571 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 2020457469 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.042260 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_misses::total 733193 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 400953 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 4800510813 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0.085903 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 143593 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses 332240 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.933239 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 477.818308 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses::0 3397820 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.934780 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 478.607338 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 3867599 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3397820 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 18508.106220 # average overall miss latency +system.cpu1.dcache.overall_accesses::total 3867599 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 20955.574591 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14070.723984 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14448.924913 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 2953656 # number of overall hits +system.cpu1.dcache.overall_hits::0 3134406 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 2953656 # number of overall hits -system.cpu1.dcache.overall_miss_latency 8220634491 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.130720 # miss rate for overall accesses +system.cpu1.dcache.overall_hits::total 3134406 # number of overall hits +system.cpu1.dcache.overall_miss_latency 15364480601 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::0 0.189573 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 444164 # number of overall misses +system.cpu1.dcache.overall_misses::0 733193 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 444164 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 300571 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 2020457469 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.042260 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_misses::total 733193 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 400953 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 4800510813 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::0 0.085903 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 143593 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 395333500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_misses 332240 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 899991500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 132541 # number of replacements -system.cpu1.dcache.sampled_refs 132935 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 320146 # number of replacements +system.cpu1.dcache.sampled_refs 320658 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 477.818308 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3040725 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1877659429000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 88729 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 6964749 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:BranchMispred 7942 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 127908 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 13950494 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 8268833 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 2507185 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 305915 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 23718 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 99432 # Number of cycles decode is unblocking -system.cpu1.dtb.data_accesses 453938 # DTB accesses -system.cpu1.dtb.data_acv 180 # DTB access violations -system.cpu1.dtb.data_hits 3612649 # DTB hits -system.cpu1.dtb.data_misses 12920 # DTB misses +system.cpu1.dcache.tagsinuse 478.607338 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3201172 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 38945924000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 258747 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 8810954 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BranchMispred 10399 # Number of times decode detected a branch misprediction +system.cpu1.decode.DECODE:BranchResolved 165542 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 17654641 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 8825966 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 3267842 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 401676 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 25654 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 107597 # Number of cycles decode is unblocking +system.cpu1.dtb.data_accesses 513633 # DTB accesses +system.cpu1.dtb.data_acv 185 # DTB access violations +system.cpu1.dtb.data_hits 4112878 # DTB hits +system.cpu1.dtb.data_misses 16265 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 321913 # DTB read accesses -system.cpu1.dtb.read_acv 80 # DTB read access violations -system.cpu1.dtb.read_hits 2185375 # DTB read hits -system.cpu1.dtb.read_misses 10510 # DTB read misses -system.cpu1.dtb.write_accesses 132025 # DTB write accesses -system.cpu1.dtb.write_acv 100 # DTB write access violations -system.cpu1.dtb.write_hits 1427274 # DTB write hits -system.cpu1.dtb.write_misses 2410 # DTB write misses -system.cpu1.fetch.Branches 2997822 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 1676432 # Number of cache lines fetched -system.cpu1.fetch.Cycles 2639364 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 103824 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 14202816 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 9160 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 191448 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.152633 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 1676430 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 1371727 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.723132 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 18146115 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.782692 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.130549 # Number of instructions fetched each cycle (Total) +system.cpu1.dtb.read_accesses 363334 # DTB read accesses +system.cpu1.dtb.read_acv 74 # DTB read access violations +system.cpu1.dtb.read_hits 2619291 # DTB read hits +system.cpu1.dtb.read_misses 12612 # DTB read misses +system.cpu1.dtb.write_accesses 150299 # DTB write accesses +system.cpu1.dtb.write_acv 111 # DTB write access violations +system.cpu1.dtb.write_hits 1493587 # DTB write hits +system.cpu1.dtb.write_misses 3653 # DTB write misses +system.cpu1.fetch.Branches 3622579 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 2099932 # Number of cache lines fetched +system.cpu1.fetch.Cycles 3426887 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 116518 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 18019858 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 11061 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 232369 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.147851 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 2099931 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 1775258 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.735460 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 21414036 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.841498 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.178120 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 15506751 85.45% 85.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 211557 1.17% 86.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 323359 1.78% 88.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 200500 1.10% 89.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 379117 2.09% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 126850 0.70% 92.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 170740 0.94% 93.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 250045 1.38% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 977196 5.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 17987149 84.00% 84.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 213365 1.00% 84.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 513318 2.40% 87.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 281609 1.32% 88.71% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 570957 2.67% 91.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 173244 0.81% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 240049 1.12% 93.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 130072 0.61% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1304273 6.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 18146115 # Number of instructions fetched each cycle (Total) -system.cpu1.fp_regfile_reads 63126 # number of floating regfile reads -system.cpu1.fp_regfile_writes 63154 # number of floating regfile writes -system.cpu1.icache.ReadReq_accesses::0 1676432 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1676432 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.725411 # average ReadReq miss latency +system.cpu1.fetch.rateDist::total 21414036 # Number of instructions fetched each cycle (Total) +system.cpu1.fp_regfile_reads 44611 # number of floating regfile reads +system.cpu1.fp_regfile_writes 43862 # number of floating regfile writes +system.cpu1.icache.ReadReq_accesses::0 2099932 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2099932 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 15131.623612 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11629.810943 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 1412386 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1412386 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 3874538500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.157505 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 264046 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 264046 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 8197 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 2975475500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152615 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12110.189366 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits::0 1856598 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1856598 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 3682038500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::0 0.115877 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 243334 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 243334 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 9659 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 2829848500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.111277 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 255849 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs 5555.555556 # average number of cycles each access was blocked +system.cpu1.icache.ReadReq_mshr_misses 233675 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs 10681.818182 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 5.521576 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu1.icache.avg_refs 7.947119 # Average number of references to valid blocks. +system.cpu1.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_mshrs 50000 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 235000 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 1676432 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::0 2099932 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1676432 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 14673.725411 # average overall miss latency +system.cpu1.icache.demand_accesses::total 2099932 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 15131.623612 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11629.810943 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 1412386 # number of demand (read+write) hits +system.cpu1.icache.demand_avg_mshr_miss_latency 12110.189366 # average overall mshr miss latency +system.cpu1.icache.demand_hits::0 1856598 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1412386 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 3874538500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.157505 # miss rate for demand accesses +system.cpu1.icache.demand_hits::total 1856598 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 3682038500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::0 0.115877 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 264046 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::0 243334 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 264046 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 8197 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 2975475500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.152615 # mshr miss rate for demand accesses +system.cpu1.icache.demand_misses::total 243334 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 9659 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 2829848500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0.111277 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 255849 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses 233675 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.900434 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 461.022397 # Average occupied blocks per context -system.cpu1.icache.overall_accesses::0 1676432 # number of overall (read+write) accesses +system.cpu1.icache.occ_%::0 0.980042 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 501.781584 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 2099932 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1676432 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 14673.725411 # average overall miss latency +system.cpu1.icache.overall_accesses::total 2099932 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 15131.623612 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11629.810943 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 12110.189366 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 1412386 # number of overall hits +system.cpu1.icache.overall_hits::0 1856598 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 1412386 # number of overall hits -system.cpu1.icache.overall_miss_latency 3874538500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.157505 # miss rate for overall accesses +system.cpu1.icache.overall_hits::total 1856598 # number of overall hits +system.cpu1.icache.overall_miss_latency 3682038500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::0 0.115877 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 264046 # number of overall misses +system.cpu1.icache.overall_misses::0 243334 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 264046 # number of overall misses -system.cpu1.icache.overall_mshr_hits 8197 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 2975475500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.152615 # mshr miss rate for overall accesses +system.cpu1.icache.overall_misses::total 243334 # number of overall misses +system.cpu1.icache.overall_mshr_hits 9659 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 2829848500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::0 0.111277 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 255849 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses 233675 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 255282 # number of replacements -system.cpu1.icache.sampled_refs 255794 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 233107 # number of replacements +system.cpu1.icache.sampled_refs 233619 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 461.022397 # Cycle average of tags in use -system.cpu1.icache.total_refs 1412386 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1897915594000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.writebacks 23 # number of writebacks -system.cpu1.idleCycles 1494579 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 1630757 # Number of branches executed -system.cpu1.iew.EXEC:nop 601681 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.552014 # Inst execution rate -system.cpu1.iew.EXEC:refs 3642117 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 1436733 # Number of stores executed +system.cpu1.icache.tagsinuse 501.781584 # Cycle average of tags in use +system.cpu1.icache.total_refs 1856598 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1710247615000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 27 # number of writebacks +system.cpu1.idleCycles 3087450 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 2215124 # Number of branches executed +system.cpu1.iew.EXEC:nop 807214 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.568172 # Inst execution rate +system.cpu1.iew.EXEC:refs 4143059 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 1503378 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 6271876 # num instructions consuming a value -system.cpu1.iew.WB:count 10737023 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.735626 # average fanout of values written-back +system.cpu1.iew.WB:consumers 9185033 # num instructions consuming a value +system.cpu1.iew.WB:count 13765716 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.723664 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 4613753 # num instructions producing a value -system.cpu1.iew.WB:rate 0.546672 # insts written-back per cycle -system.cpu1.iew.WB:sent 10760010 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 178779 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 257448 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 2307630 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 500245 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 209270 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 1513195 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 12409620 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 2205384 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 107607 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 10841947 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 2515 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 6646874 # num instructions producing a value +system.cpu1.iew.WB:rate 0.561832 # insts written-back per cycle +system.cpu1.iew.WB:sent 13802747 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 229368 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 1971298 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 2745592 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 455487 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 238559 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 1578351 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 15868399 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 2639681 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 166261 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 13921060 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 10672 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 4902 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 305915 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 10123 # Number of cycles IEW is unblocking +system.cpu1.iew.iewLSQFullEvents 5665 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 401676 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 76714 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 20397 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 68108 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 2244 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.cacheBlocked 25188 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 88996 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 4435 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 10644 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 381 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 315659 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 128810 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 10644 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 104770 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 74009 # Number of branches that were predicted taken incorrectly -system.cpu1.int_regfile_reads 13934200 # number of integer regfile reads -system.cpu1.int_regfile_writes 7613029 # number of integer regfile writes -system.cpu1.ipc 0.513098 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.513098 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3524 0.03% 0.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6872542 62.77% 62.80% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 18152 0.17% 62.96% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.96% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11432 0.10% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 2280411 20.83% 83.91% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1453875 13.28% 97.19% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307856 2.81% 100.00% # Type of FU issued +system.cpu1.iew.lsq.thread.0.memOrderViolation 4299 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 5923 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 416191 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 148395 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 4299 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 105547 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 123821 # Number of branches that were predicted taken incorrectly +system.cpu1.int_regfile_reads 18282773 # number of integer regfile reads +system.cpu1.int_regfile_writes 9947337 # number of integer regfile writes +system.cpu1.ipc 0.520143 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.520143 # IPC: Total IPC of All Threads +system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3979 0.03% 0.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 9510353 67.51% 67.54% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 21826 0.15% 67.69% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.69% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11300 0.08% 67.77% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.77% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.77% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.77% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1989 0.01% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 2724274 19.34% 87.13% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1523321 10.81% 97.94% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IprAccess 290281 2.06% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 10949554 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 155065 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.014162 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 14087323 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 199599 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.014169 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 4030 2.60% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 91114 58.76% 61.36% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 59921 38.64% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 10735 5.38% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 110682 55.45% 60.83% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 78182 39.17% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 18146115 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.603410 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.208341 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 21414036 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.657855 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.314285 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0 12918859 71.19% 71.19% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1 2566374 14.14% 85.34% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2 1069941 5.90% 91.23% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3 687798 3.79% 95.02% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4 527186 2.91% 97.93% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5 238422 1.31% 99.24% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6 93189 0.51% 99.76% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7 34852 0.19% 99.95% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 9494 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0 15246065 71.20% 71.20% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1 2762432 12.90% 84.10% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2 1149877 5.37% 89.47% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3 942390 4.40% 93.87% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4 699267 3.27% 97.13% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5 379191 1.77% 98.90% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6 160390 0.75% 99.65% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7 52788 0.25% 99.90% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 21636 0.10% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 18146115 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.557493 # Inst issue rate -system.cpu1.iq.fp_alu_accesses 125187 # Number of floating point alu accesses -system.cpu1.iq.fp_inst_queue_reads 243060 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_wakeup_accesses 117556 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_writes 119680 # Number of floating instruction queue writes -system.cpu1.iq.int_alu_accesses 10975908 # Number of integer alu accesses -system.cpu1.iq.int_inst_queue_reads 39967405 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_wakeup_accesses 10619467 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.int_inst_queue_writes 13352100 # Number of integer instruction queue writes -system.cpu1.iq.iqInstsAdded 11252265 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 10949554 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 555674 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 1655179 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 10177 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 392670 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 852165 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.ISSUE:issued_per_cycle::total 21414036 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.574958 # Inst issue rate +system.cpu1.iq.fp_alu_accesses 84267 # Number of floating point alu accesses +system.cpu1.iq.fp_inst_queue_reads 163543 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_wakeup_accesses 78913 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_writes 80927 # Number of floating instruction queue writes +system.cpu1.iq.int_alu_accesses 14198676 # Number of integer alu accesses +system.cpu1.iq.int_inst_queue_reads 49640351 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_wakeup_accesses 13686803 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.int_inst_queue_writes 17182956 # Number of integer instruction queue writes +system.cpu1.iq.iqInstsAdded 14556864 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 14087323 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 504321 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 2199611 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 15615 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 360700 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 1165068 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 448608 # ITB accesses -system.cpu1.itb.fetch_acv 274 # ITB acv -system.cpu1.itb.fetch_hits 439933 # ITB hits -system.cpu1.itb.fetch_misses 8675 # ITB misses +system.cpu1.itb.fetch_accesses 456053 # ITB accesses +system.cpu1.itb.fetch_acv 249 # ITB acv +system.cpu1.itb.fetch_hits 445822 # ITB hits +system.cpu1.itb.fetch_misses 10231 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_hits 0 # DTB read hits @@ -1124,113 +1124,113 @@ system.cpu1.itb.write_acv 0 # DT system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 254 0.45% 0.45% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1450 2.54% 2.99% # number of callpals executed -system.cpu1.kern.callpal::tbi 12 0.02% 3.01% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.02% # number of callpals executed -system.cpu1.kern.callpal::swpipl 49364 86.50% 89.53% # number of callpals executed -system.cpu1.kern.callpal::rdps 2383 4.18% 93.70% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.71% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.71% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.00% 93.72% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.72% # number of callpals executed -system.cpu1.kern.callpal::rti 3352 5.87% 99.60% # number of callpals executed -system.cpu1.kern.callpal::callsys 187 0.33% 99.92% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 288 0.55% 0.56% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.56% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.56% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1111 2.14% 2.70% # number of callpals executed +system.cpu1.kern.callpal::tbi 11 0.02% 2.72% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.73% # number of callpals executed +system.cpu1.kern.callpal::swpipl 44860 86.39% 89.12% # number of callpals executed +system.cpu1.kern.callpal::rdps 2426 4.67% 93.79% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.79% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 93.80% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.00% 93.81% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.81% # number of callpals executed +system.cpu1.kern.callpal::rti 2967 5.71% 99.53% # number of callpals executed +system.cpu1.kern.callpal::callsys 200 0.39% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 45 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 57066 # number of callpals executed +system.cpu1.kern.callpal::total 51930 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 64904 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2510 # number of quiesce instructions executed -system.cpu1.kern.ipl_count::0 20664 37.58% 37.58% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1922 3.50% 41.07% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 351 0.64% 41.71% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 32053 58.29% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 54990 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 20157 47.72% 47.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1922 4.55% 52.28% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 351 0.83% 53.11% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 19806 46.89% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 42236 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870770905000 98.44% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 347965500 0.02% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 137591500 0.01% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29223562000 1.54% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900480024000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.975465 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 60321 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 4094 # number of quiesce instructions executed +system.cpu1.kern.ipl_count::0 19374 38.65% 38.65% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 3.84% 42.49% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 371 0.74% 43.23% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 28454 56.77% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 50123 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 19355 47.63% 47.63% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 4.73% 52.37% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 371 0.91% 53.28% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 18984 46.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 40634 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1871185338500 98.39% 98.39% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 350210000 0.02% 98.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 149885000 0.01% 98.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 30038792500 1.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1901724226000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999019 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.617914 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 849 -system.cpu1.kern.mode_good::user 573 -system.cpu1.kern.mode_good::idle 276 -system.cpu1.kern.mode_switch::kernel 1766 # number of protection mode switches -system.cpu1.kern.mode_switch::user 573 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2541 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.480747 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used::31 0.667182 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 994 +system.cpu1.kern.mode_good::user 661 +system.cpu1.kern.mode_good::idle 333 +system.cpu1.kern.mode_switch::kernel 1487 # number of protection mode switches +system.cpu1.kern.mode_switch::user 661 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2593 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.668460 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.108619 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.589366 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 6317215000 0.33% 0.33% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1021115000 0.05% 0.39% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893129227000 99.61% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1451 # number of times the context was actually changed -system.cpu1.kern.syscall::2 2 1.60% 1.60% # number of syscalls executed -system.cpu1.kern.syscall::3 13 10.40% 12.00% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.80% 12.80% # number of syscalls executed -system.cpu1.kern.syscall::6 15 12.00% 24.80% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.80% 25.60% # number of syscalls executed -system.cpu1.kern.syscall::17 6 4.80% 30.40% # number of syscalls executed -system.cpu1.kern.syscall::19 4 3.20% 33.60% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.60% 35.20% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.40% 37.60% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.40% 40.00% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.20% 43.20% # number of syscalls executed -system.cpu1.kern.syscall::45 18 14.40% 57.60% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.40% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::48 3 2.40% 62.40% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.80% 63.20% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.60% 64.80% # number of syscalls executed -system.cpu1.kern.syscall::71 27 21.60% 86.40% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.20% 93.60% # number of syscalls executed -system.cpu1.kern.syscall::90 2 1.60% 95.20% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.60% 96.80% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.40% 99.20% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.80% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 125 # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 495102 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 416651 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 2307630 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1513195 # Number of stores inserted to the mem dependence unit. -system.cpu1.misc_regfile_reads 594453 # number of misc regfile reads -system.cpu1.misc_regfile_writes 255211 # number of misc regfile writes -system.cpu1.numCycles 19640694 # number of cpu cycles simulated +system.cpu1.kern.mode_switch_good::idle 0.128423 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.796883 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 37276082000 1.96% 1.96% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1059454000 0.06% 2.02% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1863388682000 97.98% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1112 # number of times the context was actually changed +system.cpu1.kern.syscall::2 2 1.46% 1.46% # number of syscalls executed +system.cpu1.kern.syscall::3 14 10.22% 11.68% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.73% 12.41% # number of syscalls executed +system.cpu1.kern.syscall::6 16 11.68% 24.09% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.73% 24.82% # number of syscalls executed +system.cpu1.kern.syscall::17 7 5.11% 29.93% # number of syscalls executed +system.cpu1.kern.syscall::19 4 2.92% 32.85% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.46% 34.31% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.19% 36.50% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.19% 38.69% # number of syscalls executed +system.cpu1.kern.syscall::33 5 3.65% 42.34% # number of syscalls executed +system.cpu1.kern.syscall::45 21 15.33% 57.66% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.19% 59.85% # number of syscalls executed +system.cpu1.kern.syscall::48 3 2.19% 62.04% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.73% 62.77% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.46% 64.23% # number of syscalls executed +system.cpu1.kern.syscall::71 31 22.63% 86.86% # number of syscalls executed +system.cpu1.kern.syscall::74 10 7.30% 94.16% # number of syscalls executed +system.cpu1.kern.syscall::90 2 1.46% 95.62% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.46% 97.08% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.19% 99.27% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.73% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 137 # number of syscalls executed +system.cpu1.memDep0.conflictingLoads 315526 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 194379 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 2745592 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1578351 # Number of stores inserted to the mem dependence unit. +system.cpu1.misc_regfile_reads 493874 # number of misc regfile reads +system.cpu1.misc_regfile_writes 221749 # number of misc regfile writes +system.cpu1.numCycles 24501486 # number of cpu cycles simulated system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.rename.RENAME:BlockCycles 523712 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 7159591 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 32710 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 8501498 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 256763 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 15504 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 15470992 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 12928500 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 8487290 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 2361527 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 305915 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 801170 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 1327699 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:fp_rename_lookups 171482 # Number of floating rename lookups -system.cpu1.rename.RENAME:int_rename_lookups 15299510 # Number of integer rename lookups -system.cpu1.rename.RENAME:serializeStallCycles 5652291 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 515456 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 2302074 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 52719 # count of temporary serializing insts renamed -system.cpu1.rob.rob_reads 29864417 # The number of ROB reads -system.cpu1.rob.rob_writes 24957573 # The number of ROB writes -system.cpu1.timesIdled 194633 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.rename.RENAME:BlockCycles 2575160 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 9194083 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 253610 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 9125188 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 96900 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 103 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 20382349 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 16583054 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 11154403 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 2970670 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 401676 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 911632 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 1960318 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:fp_rename_lookups 113596 # Number of floating rename lookups +system.cpu1.rename.RENAME:int_rename_lookups 20268753 # Number of integer rename lookups +system.cpu1.rename.RENAME:serializeStallCycles 5429708 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 475094 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 2839642 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 40509 # count of temporary serializing insts renamed +system.cpu1.rob.rob_reads 36377887 # The number of ROB reads +system.cpu1.rob.rob_writes 31956605 # The number of ROB writes +system.cpu1.timesIdled 286877 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1243,291 +1243,291 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses::1 172 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::1 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115267.430233 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115257.131429 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63267.430233 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19825998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63257.131429 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20169998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 172 # number of ReadReq misses -system.iocache.ReadReq_misses::total 172 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10881998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_misses::1 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 11069998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 172 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137701.983202 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137655.487245 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85698.425972 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5721792806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85651.857817 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5719860806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3560940996 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3559005996 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6175.644708 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6179.103844 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64591068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64621068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41724 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137609.500623 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137561.550171 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85605.958058 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85557.935965 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5741618804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5740030804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41724 # number of demand (read+write) misses -system.iocache.demand_misses::total 41724 # number of demand (read+write) misses +system.iocache.demand_misses::1 41727 # number of demand (read+write) misses +system.iocache.demand_misses::total 41727 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3571822994 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3570075994 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41724 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.029206 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 0.467303 # Average occupied blocks per context +system.iocache.occ_%::1 0.012954 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.207263 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41724 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137609.500623 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137561.550171 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85605.958058 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85557.935965 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5741618804 # number of overall miss cycles +system.iocache.overall_miss_latency 5740030804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41724 # number of overall misses -system.iocache.overall_misses::total 41724 # number of overall misses +system.iocache.overall_misses::1 41727 # number of overall misses +system.iocache.overall_misses::total 41727 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3571822994 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3570075994 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41724 # number of overall MSHR misses +system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 41692 # number of replacements -system.iocache.sampled_refs 41708 # Sample count of references to valid blocks. +system.iocache.replacements 41695 # number of replacements +system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.467303 # Cycle average of tags in use +system.iocache.tagsinuse 0.207263 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1711286190000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1710304111000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses::0 257283 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 42295 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 299578 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 55985.536569 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 837818.012343 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 243081 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 47227 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 290308 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 61154.932642 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 368564.170526 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40324.759412 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 140886 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 34517 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 175403 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6516548500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.452408 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.183899 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 116397 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 7778 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124175 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5007327000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.482640 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 2.935926 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40302.705557 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 135076 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 29306 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 164382 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 6605038500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.444317 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.379465 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 108005 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 17921 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 125926 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 5075158500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.518041 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 2.666398 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 124175 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1807428 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 343680 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2151108 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52801.503186 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 3683358.780376 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 125926 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 1634357 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 503467 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2137824 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 53314.961165 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 2119707.492415 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40018.194749 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40003.636264 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1503141 # number of ReadReq hits -system.l2c.ReadReq_hits::1 339318 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1842459 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16066811000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.168354 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.012692 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 304287 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4362 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308649 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12350935500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.170758 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.898024 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_hits::0 1332950 # number of ReadReq hits +system.l2c.ReadReq_hits::1 495886 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1828836 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16069502500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.184419 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.015058 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 301407 # number of ReadReq misses +system.l2c.ReadReq_misses::1 7581 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308988 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12359963500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.189047 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.613687 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 308633 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 840464000 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 609 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 601 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1210 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 4879.928315 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 4727.430556 # average SCUpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 308971 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 838535000 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 620 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 656 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1276 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 18379.965458 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 17109.324759 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40008.377425 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_hits::0 51 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 25 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 76 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_miss_latency 2723000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_rate::0 0.916256 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.958403 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 558 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 576 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1134 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 45369500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.862069 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.886855 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40002.081599 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_hits::0 41 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 34 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_miss_latency 10642000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 0.933871 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.948171 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 579 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 622 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1201 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 48042500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.937097 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.830793 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 1134 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 2883 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 1622 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4505 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 5855.677656 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 12567.610063 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 1201 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 3788 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 897 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4685 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 1321.100917 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 5809.290954 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.991504 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 153 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 350 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 503 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 15986000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.946930 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.784217 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 2730 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 1272 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4002 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 160148000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.388137 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.467324 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency 40001.698754 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 191 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 79 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 270 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 4752000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.949578 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.911929 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 3597 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 818 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4415 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 176607500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.165523 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4.921962 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 4002 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 4415 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1532817998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 810507 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 810507 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 810507 # number of Writeback hits -system.l2c.Writeback_hits::total 810507 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1545168498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 791892 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 791892 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 791892 # number of Writeback hits +system.l2c.Writeback_hits::total 791892 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.658014 # Average number of references to valid blocks. +system.l2c.avg_refs 5.551399 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2064711 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 385975 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 1877438 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 550694 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2450686 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 53682.477822 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1860243.780890 # average overall miss latency +system.l2c.demand_accesses::total 2428132 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 55383.186130 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 889127.950749 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40106.149840 # average overall mshr miss latency -system.l2c.demand_hits::0 1644027 # number of demand (read+write) hits -system.l2c.demand_hits::1 373835 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40090.232860 # average overall mshr miss latency +system.l2c.demand_hits::0 1468026 # number of demand (read+write) hits +system.l2c.demand_hits::1 525192 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2017862 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22583359500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.203750 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.031453 # miss rate for demand accesses +system.l2c.demand_hits::total 1993218 # number of demand (read+write) hits +system.l2c.demand_miss_latency 22674541000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.218070 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.046309 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 420684 # number of demand (read+write) misses -system.l2c.demand_misses::1 12140 # number of demand (read+write) misses +system.l2c.demand_misses::0 409412 # number of demand (read+write) misses +system.l2c.demand_misses::1 25502 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 432824 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17358262500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.209622 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.121337 # mshr miss rate for demand accesses +system.l2c.demand_misses::total 434914 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 17435122000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.231644 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0.789725 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 432808 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 434897 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.187716 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.005740 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.351851 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 12302.143800 # Average occupied blocks per context -system.l2c.occ_blocks::1 376.171509 # Average occupied blocks per context -system.l2c.occ_blocks::2 23058.900248 # Average occupied blocks per context -system.l2c.overall_accesses::0 2064711 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 385975 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.158827 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.036596 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.351892 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 10408.866153 # Average occupied blocks per context +system.l2c.occ_blocks::1 2398.359333 # Average occupied blocks per context +system.l2c.occ_blocks::2 23061.577659 # Average occupied blocks per context +system.l2c.overall_accesses::0 1877438 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 550694 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2450686 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 53682.477822 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1860243.780890 # average overall miss latency +system.l2c.overall_accesses::total 2428132 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 55383.186130 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 889127.950749 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40106.149840 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40090.232860 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1644027 # number of overall hits -system.l2c.overall_hits::1 373835 # number of overall hits +system.l2c.overall_hits::0 1468026 # number of overall hits +system.l2c.overall_hits::1 525192 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2017862 # number of overall hits -system.l2c.overall_miss_latency 22583359500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.203750 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.031453 # miss rate for overall accesses +system.l2c.overall_hits::total 1993218 # number of overall hits +system.l2c.overall_miss_latency 22674541000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.218070 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.046309 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 420684 # number of overall misses -system.l2c.overall_misses::1 12140 # number of overall misses +system.l2c.overall_misses::0 409412 # number of overall misses +system.l2c.overall_misses::1 25502 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 432824 # number of overall misses -system.l2c.overall_mshr_hits 16 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17358262500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.209622 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.121337 # mshr miss rate for overall accesses +system.l2c.overall_misses::total 434914 # number of overall misses +system.l2c.overall_mshr_hits 17 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 17435122000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.231644 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0.789725 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 432808 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2373281998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 434897 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2383703498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 395559 # number of replacements -system.l2c.sampled_refs 431638 # Sample count of references to valid blocks. +system.l2c.replacements 397174 # number of replacements +system.l2c.sampled_refs 433601 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 35737.215556 # Cycle average of tags in use -system.l2c.total_refs 2442214 # Total number of references to valid blocks. -system.l2c.warmup_cycle 9270445000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 121360 # number of writebacks +system.l2c.tagsinuse 35868.803144 # Cycle average of tags in use +system.l2c.total_refs 2407092 # Total number of references to valid blocks. +system.l2c.warmup_cycle 9258990000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 122449 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index a3d5d3586..3773b1a35 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -10,12 +10,12 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/chips/pd/randd/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/chips/pd/randd/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -493,7 +493,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -513,7 +513,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -641,7 +641,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 9021122e3..b2f6462f2 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 15 2011 18:10:57 -M5 revision ee89694ad8dc 8081 default ext/mem_block_transfer_O3_regressions.patch tip qtip -M5 started Mar 15 2011 18:10:59 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Mar 17 2011 22:48:41 +M5 started Mar 17 2011 22:50:11 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1865724648500 because m5_exit instruction encountered +Exiting @ tick 1863702170500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 2e169bdbb..dddaa888b 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,502 +1,502 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 180508 # Simulator instruction rate (inst/s) -host_mem_usage 328492 # Number of bytes of host memory used -host_seconds 293.90 # Real time elapsed on the host -host_tick_rate 6348189027 # Simulator tick rate (ticks/s) +host_inst_rate 125213 # Simulator instruction rate (inst/s) +host_mem_usage 294244 # Number of bytes of host memory used +host_seconds 424.00 # Real time elapsed on the host +host_tick_rate 4395569700 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53051011 # Number of instructions simulated -sim_seconds 1.865725 # Number of seconds simulated -sim_ticks 1865724648500 # Number of ticks simulated +sim_insts 53089625 # Number of instructions simulated +sim_seconds 1.863702 # Number of seconds simulated +sim_ticks 1863702170500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6620966 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 12786893 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 40572 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 600914 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11937031 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14338397 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1014681 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8457274 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 1008616 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 6622434 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 12800990 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 39895 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 599479 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11925971 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14248722 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 975192 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8461745 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 1125976 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 89227396 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.630345 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.393343 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 87254730 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.645057 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.459520 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 65107231 72.97% 72.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 10642774 11.93% 84.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 6057714 6.79% 91.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 2842201 3.19% 94.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2098462 2.35% 97.22% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 700908 0.79% 98.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 394479 0.44% 98.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 375011 0.42% 98.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 1008616 1.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 64129239 73.50% 73.50% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 10001511 11.46% 84.96% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 5794569 6.64% 91.60% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 2584226 2.96% 94.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 1856466 2.13% 96.69% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 706744 0.81% 97.50% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 418456 0.48% 97.98% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 637543 0.73% 98.71% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 1125976 1.29% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 89227396 # Number of insts commited each cycle -system.cpu.commit.COM:count 56244072 # Number of instructions committed -system.cpu.commit.COM:fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 744089 # Number of function calls committed. -system.cpu.commit.COM:int_insts 52084090 # Number of committed integer instructions. -system.cpu.commit.COM:loads 9107066 # Number of loads committed -system.cpu.commit.COM:membars 227958 # Number of memory barriers committed -system.cpu.commit.COM:refs 15496059 # Number of memory references committed +system.cpu.commit.COM:committed_per_cycle::total 87254730 # Number of insts commited each cycle +system.cpu.commit.COM:count 56284256 # Number of instructions committed +system.cpu.commit.COM:fp_insts 324451 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 744594 # Number of function calls committed. +system.cpu.commit.COM:int_insts 52122555 # Number of committed integer instructions. +system.cpu.commit.COM:loads 9113387 # Number of loads committed +system.cpu.commit.COM:membars 227959 # Number of memory barriers committed +system.cpu.commit.COM:refs 15505823 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 771395 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56244072 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8698928 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53051011 # Number of Instructions Simulated -system.cpu.committedInsts_total 53051011 # Number of Instructions Simulated -system.cpu.cpi 2.358035 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.358035 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 215741 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 215741 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14722.823889 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 769874 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56284256 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667734 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 8032073 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53089625 # Number of Instructions Simulated +system.cpu.committedInsts_total 53089625 # Number of Instructions Simulated +system.cpu.cpi 2.304358 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.304358 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 213395 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 213395 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14731.007611 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11882.359679 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 193488 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 193488 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 327627000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103147 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 22253 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22253 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4793 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207466000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.080930 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11798.670030 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 191452 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 191452 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 323242500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.102828 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 21943 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 21943 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4499 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 205816000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081745 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17460 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9298482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9298482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 22717.267883 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 17444 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9261736 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9261736 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 21557.160878 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22779.415740 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22806.773244 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7724340 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7724340 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 35760205500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.169290 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1574142 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1574142 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 490275 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24689857000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116564 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7478882 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7478882 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 38433270500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.192497 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1782854 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1782854 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 698012 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24741745500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117132 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1083867 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 905506500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 219687 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219687 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14000 # average StoreCondReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 1084842 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904671500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 219886 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219886 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 24500 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 219684 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 219684 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 42000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000014 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 3 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 33000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000014 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 21375 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::0 219882 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 219882 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 98000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000018 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 4 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 85500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000018 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 3 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6154158 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6154158 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 29745.716858 # average WriteReq miss latency +system.cpu.dcache.StoreCondReq_mshr_misses 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses::0 6157400 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157400 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 29663.792257 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28090.291333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28277.245454 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 4298986 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4298986 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 55183421035 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.301450 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 1855172 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1855172 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1555560 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 8416188367 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048684 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 4231311 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4231311 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 57135103964 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.312809 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 1926089 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1926089 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1626424 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 8473700759 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048667 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 299612 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235453998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8964.775985 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.878146 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 83356 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 747267867 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 299665 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235406998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8946.248648 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.647226 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 99695 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 891896259 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 24000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15452640 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15419136 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15452640 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26519.480729 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15419136 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 25767.010834 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23929.561177 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 12023326 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23990.811357 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 11710193 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12023326 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 90943626535 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.221924 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 11710193 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 95568374464 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.240542 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 3429314 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3708943 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3429314 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2045835 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 33106045367 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.089530 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 3708943 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2324436 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 33215446259 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.089791 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1383479 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1384507 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.995488 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15452640 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::0 0.999992 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.995879 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15419136 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15452640 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26519.480729 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15419136 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 25767.010834 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23929.561177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23990.811357 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 12023326 # number of overall hits +system.cpu.dcache.overall_hits::0 11710193 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 12023326 # number of overall hits -system.cpu.dcache.overall_miss_latency 90943626535 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.221924 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 11710193 # number of overall hits +system.cpu.dcache.overall_miss_latency 95568374464 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.240542 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 3429314 # number of overall misses +system.cpu.dcache.overall_misses::0 3708943 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3429314 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2045835 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 33106045367 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.089530 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 3708943 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2324436 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 33215446259 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.089791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1383479 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2140960498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1384507 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2140078498 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1400295 # number of replacements -system.cpu.dcache.sampled_refs 1400807 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1401285 # number of replacements +system.cpu.dcache.sampled_refs 1401797 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.995488 # Cycle average of tags in use -system.cpu.dcache.total_refs 12436569 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21271000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 832735 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 37803322 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42125 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 613661 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 71395902 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37491497 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 12847985 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1515320 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 134367 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1084591 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1236212 # DTB accesses -system.cpu.dtb.data_acv 809 # DTB access violations -system.cpu.dtb.data_hits 16593947 # DTB hits -system.cpu.dtb.data_misses 46903 # DTB misses +system.cpu.dcache.tagsinuse 511.995879 # Cycle average of tags in use +system.cpu.dcache.total_refs 12121656 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 19670000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 833416 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 36259760 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 44553 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 598925 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 70789187 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37160222 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 12840041 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1435065 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 134914 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 994706 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1263492 # DTB accesses +system.cpu.dtb.data_acv 894 # DTB access violations +system.cpu.dtb.data_hits 16635681 # DTB hits +system.cpu.dtb.data_misses 51508 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 911157 # DTB read accesses -system.cpu.dtb.read_acv 576 # DTB read access violations -system.cpu.dtb.read_hits 10006781 # DTB read hits -system.cpu.dtb.read_misses 38661 # DTB read misses -system.cpu.dtb.write_accesses 325055 # DTB write accesses -system.cpu.dtb.write_acv 233 # DTB write access violations -system.cpu.dtb.write_hits 6587166 # DTB write hits -system.cpu.dtb.write_misses 8242 # DTB write misses -system.cpu.fetch.Branches 14338397 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8855922 # Number of cache lines fetched -system.cpu.fetch.Cycles 14113501 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 454413 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 72660960 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 42720 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 884189 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.114619 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8855919 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7635647 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.580841 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 90742716 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.800736 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.110037 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_accesses 928978 # DTB read accesses +system.cpu.dtb.read_acv 572 # DTB read access violations +system.cpu.dtb.read_hits 10041253 # DTB read hits +system.cpu.dtb.read_misses 41018 # DTB read misses +system.cpu.dtb.write_accesses 334514 # DTB write accesses +system.cpu.dtb.write_acv 322 # DTB write access violations +system.cpu.dtb.write_hits 6594428 # DTB write hits +system.cpu.dtb.write_misses 10490 # DTB write misses +system.cpu.fetch.Branches 14248722 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8770990 # Number of cache lines fetched +system.cpu.fetch.Cycles 14042166 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 446901 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 72221007 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 40836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 893682 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.116471 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8770984 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7597626 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.590342 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 88689795 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.814310 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.123238 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 76629215 84.45% 84.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1044484 1.15% 85.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1968851 2.17% 87.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 922109 1.02% 88.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2984062 3.29% 92.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 649093 0.72% 92.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 777227 0.86% 93.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1074028 1.18% 94.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4693647 5.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 74647629 84.17% 84.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1010703 1.14% 85.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1983506 2.24% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 916230 1.03% 88.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2985219 3.37% 91.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 672792 0.76% 92.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 771901 0.87% 93.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1056160 1.19% 94.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4645655 5.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 90742716 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 164464 # number of floating regfile reads -system.cpu.fp_regfile_writes 166718 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses::0 8855922 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8855922 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14953.893584 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 88689795 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 166013 # number of floating regfile reads +system.cpu.fp_regfile_writes 166759 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses::0 8770990 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8770990 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 15000.124864 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.313504 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 7815698 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7815698 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15555399000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.117461 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 1040224 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1040224 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 47681 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11849289500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.112077 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11953.663532 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 7733870 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7733870 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15556929499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.118244 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 1037120 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1037120 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 43680 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11875247499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.113264 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 992543 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs 12554.545455 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses 993440 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs 12654.527273 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.875900 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 7.786451 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 690500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 695999 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 8855922 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 8770990 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8855922 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14953.893584 # average overall miss latency +system.cpu.icache.demand_accesses::total 8770990 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 15000.124864 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11938.313504 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 7815698 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11953.663532 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 7733870 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7815698 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15555399000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.117461 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 7733870 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15556929499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.118244 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 1040224 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 1037120 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1040224 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 47681 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11849289500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.112077 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 1037120 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 43680 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11875247499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.113264 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 992543 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 993440 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.995724 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 509.810451 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 8855922 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.995757 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 509.827441 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 8770990 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8855922 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14953.893584 # average overall miss latency +system.cpu.icache.overall_accesses::total 8770990 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 15000.124864 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11938.313504 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11953.663532 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 7815698 # number of overall hits +system.cpu.icache.overall_hits::0 7733870 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7815698 # number of overall hits -system.cpu.icache.overall_miss_latency 15555399000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.117461 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 7733870 # number of overall hits +system.cpu.icache.overall_miss_latency 15556929499 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.118244 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 1040224 # number of overall misses +system.cpu.icache.overall_misses::0 1037120 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1040224 # number of overall misses -system.cpu.icache.overall_mshr_hits 47681 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11849289500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.112077 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 1037120 # number of overall misses +system.cpu.icache.overall_mshr_hits 43680 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11875247499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.113264 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 992543 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 993440 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 991845 # number of replacements -system.cpu.icache.sampled_refs 992356 # Sample count of references to valid blocks. +system.cpu.icache.replacements 992736 # number of replacements +system.cpu.icache.sampled_refs 993247 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.810451 # Cycle average of tags in use -system.cpu.icache.total_refs 7815697 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 24432989000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 176 # number of writebacks -system.cpu.idleCycles 34353421 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9120660 # Number of branches executed -system.cpu.iew.EXEC:nop 3587020 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.456799 # Inst execution rate -system.cpu.iew.EXEC:refs 16683854 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6610322 # Number of stores executed +system.cpu.icache.tagsinuse 509.827441 # Cycle average of tags in use +system.cpu.icache.total_refs 7733869 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 23815676000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 201 # number of writebacks +system.cpu.idleCycles 33647698 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9077931 # Number of branches executed +system.cpu.iew.EXEC:nop 3561617 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.466022 # Inst execution rate +system.cpu.iew.EXEC:refs 16730349 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6619936 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 35263910 # num instructions consuming a value -system.cpu.iew.WB:count 56698677 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.757187 # average fanout of values written-back +system.cpu.iew.WB:consumers 36206464 # num instructions consuming a value +system.cpu.iew.WB:count 56518708 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.749991 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26701367 # num instructions producing a value -system.cpu.iew.WB:rate 0.453241 # insts written-back per cycle -system.cpu.iew.WB:sent 56800727 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 837733 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9250224 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 10628233 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1789856 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 887489 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 6943615 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65074740 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10073532 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 521272 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57143754 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 61252 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 27154531 # num instructions producing a value +system.cpu.iew.WB:rate 0.461990 # insts written-back per cycle +system.cpu.iew.WB:sent 56632372 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 834392 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9479709 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 10494692 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1785178 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 890339 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 6849187 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 64447431 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10110413 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 516805 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57012019 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 106234 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 11749 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1515320 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 557849 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 12252 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1435065 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 608300 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 132030 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 438592 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 9600 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 167273 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 486953 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 6665 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 42579 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 17615 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1521167 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 554622 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 42579 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 406353 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 431380 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 74888686 # number of integer regfile reads -system.cpu.int_regfile_writes 40930439 # number of integer regfile writes -system.cpu.ipc 0.424082 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.424082 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 18985 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 17936 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1381305 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 456751 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 18985 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 404859 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 429533 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 74751539 # number of integer regfile reads +system.cpu.int_regfile_writes 40782350 # number of integer regfile writes +system.cpu.ipc 0.433960 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.433960 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 39529083 68.55% 68.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 62345 0.11% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 10424979 18.08% 86.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 6659276 11.55% 98.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 952821 1.65% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 39349401 68.40% 68.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 62002 0.11% 68.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25611 0.04% 68.56% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 10457735 18.18% 86.75% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 6670425 11.59% 98.34% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 952735 1.66% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 57665028 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 432817 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007506 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 57528826 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 549270 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009548 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 49052 11.33% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 267357 61.77% 73.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 116408 26.90% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 45293 8.25% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 2 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 291133 53.00% 61.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 212842 38.75% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 90742716 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.635478 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200410 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 88689795 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.648652 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.255048 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 62361590 68.72% 68.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 14062254 15.50% 84.22% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 6225923 6.86% 91.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 3822183 4.21% 95.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 2538846 2.80% 98.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1090826 1.20% 99.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 462139 0.51% 99.80% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 129609 0.14% 99.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 49346 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 61727681 69.60% 69.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 12782826 14.41% 84.01% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 5739308 6.47% 90.48% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 3779668 4.26% 94.75% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 2566031 2.89% 97.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 1197199 1.35% 98.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 667320 0.75% 99.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 163755 0.18% 99.93% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 66007 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 90742716 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.460966 # Inst issue rate -system.cpu.iq.fp_alu_accesses 341264 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 667947 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 325705 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 334327 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 57749300 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 205866504 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 56372972 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 69249578 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 59448335 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 57665028 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2039385 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8059661 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 28864 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1371832 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4166065 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 88689795 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.470247 # Inst issue rate +system.cpu.iq.fp_alu_accesses 358048 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 686320 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 327228 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 333627 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 57712767 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 203646640 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 56191480 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 67929762 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 58856413 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 57528826 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2029401 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 7361535 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 36245 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1361667 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 3591759 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1294620 # ITB accesses -system.cpu.itb.fetch_acv 913 # ITB acv -system.cpu.itb.fetch_hits 1255661 # ITB hits -system.cpu.itb.fetch_misses 38959 # ITB misses +system.cpu.itb.fetch_accesses 1283361 # ITB accesses +system.cpu.itb.fetch_acv 948 # ITB acv +system.cpu.itb.fetch_hits 1244403 # ITB hits +system.cpu.itb.fetch_misses 38958 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -509,11 +509,11 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175578 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175553 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6791 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed @@ -521,43 +521,43 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5221 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192547 # number of callpals executed +system.cpu.kern.callpal::total 192522 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211704 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6424 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 74914 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 239 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1889 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105885 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182927 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73547 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 239 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73548 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149223 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1826194216500 97.88% 97.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 97924500 0.01% 97.89% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 391796500 0.02% 97.91% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 39039837500 2.09% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1865723775000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 211679 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6434 # number of quiesce instructions executed +system.cpu.kern.ipl_count::0 74901 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 243 0.13% 41.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1887 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105871 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182902 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73534 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1887 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73537 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149201 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1824267875500 97.88% 97.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 98431000 0.01% 97.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 391220000 0.02% 97.91% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38943770500 2.09% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1863701297000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694603 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1906 -system.cpu.kern.mode_good::user 1736 +system.cpu.kern.ipl_used::31 0.694591 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch::kernel 5959 # number of protection mode switches -system.cpu.kern.mode_switch::user 1736 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2104 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.319852 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::kernel 5958 # number of protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320074 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080798 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.400651 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 30091122000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 3014546000 0.16% 1.77% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832618099000 98.23% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.400796 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29982299000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2910857500 0.16% 1.76% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1830808132500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -589,37 +589,37 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.memDep0.conflictingLoads 3018997 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2591949 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 10628233 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6943615 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 1993395 # number of misc regfile reads -system.cpu.misc_regfile_writes 949366 # number of misc regfile writes -system.cpu.numCycles 125096137 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 1611665 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1565492 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 10494692 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6849187 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1995286 # number of misc regfile reads +system.cpu.misc_regfile_writes 949727 # number of misc regfile writes +system.cpu.numCycles 122337493 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 13296621 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38227330 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1065712 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39057588 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1661249 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 58583 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 82211156 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 67570562 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 45292482 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12512523 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1515320 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 4654421 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7065150 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 475144 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 81736012 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 19706241 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1694164 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 11744747 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 247277 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 152910637 # The number of ROB reads -system.cpu.rob.rob_writes 131402179 # The number of ROB writes -system.cpu.timesIdled 1310794 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 12932543 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38258765 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1039474 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 38708983 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1241691 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 1519 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 81518808 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 66985432 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 44869849 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12449033 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1435065 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 4145083 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 6611082 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 474213 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 81044595 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 19019086 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1691185 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 11218533 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 244825 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 150193940 # The number of ROB reads +system.cpu.rob.rob_writes 130068170 # The number of ROB writes +system.cpu.timesIdled 1318957 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -635,14 +635,14 @@ system.disk2.dma_write_txs 1 # Nu system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses::1 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses @@ -650,37 +650,37 @@ system.iocache.ReadReq_mshr_misses 173 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137705.665335 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137723.402147 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85702.060021 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5721945806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85719.890306 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5722682806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3561091998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561832882 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6170.968690 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6163.814415 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64647068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64565956 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137612.553721 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137630.264925 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85608.963355 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85626.767645 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5741883804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5742622804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -688,7 +688,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3572033996 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3572776880 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -696,20 +696,20 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.081046 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.296738 # Average occupied blocks per context +system.iocache.occ_%::1 0.080564 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.289021 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137612.553721 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137630.264925 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85608.963355 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85626.767645 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5741883804 # number of overall miss cycles +system.iocache.overall_miss_latency 5742622804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -717,7 +717,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3572033996 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3572776880 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -727,145 +727,154 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.296738 # Cycle average of tags in use +system.iocache.tagsinuse 1.289021 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1711281262000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1710301197000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 300822 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300822 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52489.461538 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 300895 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300895 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52473.313718 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40340.521368 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 183822 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183822 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6141267000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.388934 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 117000 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 117000 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4719841000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.388934 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40319.645209 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 183981 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183981 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 6134865000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.388554 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 116914 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116914 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4713931000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.388554 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 117000 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2092337 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2092337 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52046.096131 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 116914 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2094150 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2094150 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52039.282964 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40015.012554 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40022.101207 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1784860 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1784860 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16002977500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.146954 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 307477 # number of ReadReq misses -system.l2c.ReadReq_misses::total 307477 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1786383 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1786383 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16015974000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.146965 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 307767 # number of ReadReq misses +system.l2c.ReadReq_misses::total 307767 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12303656000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146953 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12317442000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146965 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307476 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 810924000 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadReq_mshr_misses 307766 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 809986500 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.UpgradeReq_accesses::0 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 22928.571429 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_miss_rate::0 0.250000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 40000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_misses 1 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 38 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 38 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 14960 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 44285.714286 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 8 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 321000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.636364 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 14 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 14 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 620000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.636364 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency 42440 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 374000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.657895 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 25 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 25 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 1061000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.657895 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1115890498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 832911 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 832911 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 832911 # number of Writeback hits -system.l2c.Writeback_hits::total 832911 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1116065498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 833617 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 833617 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 833617 # number of Writeback hits +system.l2c.Writeback_hits::total 833617 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.628523 # Average number of references to valid blocks. +system.l2c.avg_refs 5.655777 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2393159 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2395045 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2393159 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52168.302405 # average overall miss latency +system.l2c.demand_accesses::total 2395045 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52158.770936 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40104.733837 # average overall mshr miss latency -system.l2c.demand_hits::0 1968682 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40104.014788 # average overall mshr miss latency +system.l2c.demand_hits::0 1970364 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1968682 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22144244500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.177371 # miss rate for demand accesses +system.l2c.demand_hits::total 1970364 # number of demand (read+write) hits +system.l2c.demand_miss_latency 22150839000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.177317 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 424477 # number of demand (read+write) misses +system.l2c.demand_misses::0 424681 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 424477 # number of demand (read+write) misses +system.l2c.demand_misses::total 424681 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17023497000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.177371 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 17031373000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.177316 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 424476 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 424680 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.186906 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.344678 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 12249.050591 # Average occupied blocks per context -system.l2c.occ_blocks::1 22588.829074 # Average occupied blocks per context -system.l2c.overall_accesses::0 2393159 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.185866 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.343812 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 12180.929780 # Average occupied blocks per context +system.l2c.occ_blocks::1 22532.084945 # Average occupied blocks per context +system.l2c.overall_accesses::0 2395045 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2393159 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52168.302405 # average overall miss latency +system.l2c.overall_accesses::total 2395045 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52158.770936 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40104.733837 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40104.014788 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1968682 # number of overall hits +system.l2c.overall_hits::0 1970364 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1968682 # number of overall hits -system.l2c.overall_miss_latency 22144244500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.177371 # miss rate for overall accesses +system.l2c.overall_hits::total 1970364 # number of overall hits +system.l2c.overall_miss_latency 22150839000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.177317 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 424477 # number of overall misses +system.l2c.overall_misses::0 424681 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 424477 # number of overall misses +system.l2c.overall_misses::total 424681 # number of overall misses system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17023497000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.177371 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 17031373000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.177316 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 424476 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1926814498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 424680 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1926051998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 390976 # number of replacements -system.l2c.sampled_refs 423725 # Sample count of references to valid blocks. +system.l2c.replacements 390703 # number of replacements +system.l2c.sampled_refs 423923 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 34837.879666 # Cycle average of tags in use -system.l2c.total_refs 2384946 # Total number of references to valid blocks. -system.l2c.warmup_cycle 5637119000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 117616 # number of writebacks +system.l2c.tagsinuse 34713.014726 # Cycle average of tags in use +system.l2c.total_refs 2397614 # Total number of references to valid blocks. +system.l2c.warmup_cycle 5626579000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 117022 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini index c2ce6a46c..55f3d08fb 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -11,7 +11,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t boot_cpu_frequency=500 boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux.arm +kernel=/dist/m5/system/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -493,7 +493,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/chips/pd/randd/dist/disks/ael-arm.ext2 +file=/dist/m5/system/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr index 701e9297b..63ac398c9 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -26,8 +26,6 @@ warn: instruction 'mcr icimvau' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -For more information see: http://www.m5sim.org/warn/7998f2ea warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index b92737e2d..03f27ae2f 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:37 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:12:00 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Mar 18 2011 02:37:41 +M5 started Mar 18 2011 02:38:20 +M5 executing on zizzer command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 84388283500 because m5_exit instruction encountered +Exiting @ tick 83363125500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 2142ffa48..2371efa42 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,506 +1,506 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 136897 # Simulator instruction rate (inst/s) -host_mem_usage 384172 # Number of bytes of host memory used -host_seconds 379.57 # Real time elapsed on the host -host_tick_rate 222327398 # Simulator tick rate (ticks/s) +host_inst_rate 136397 # Simulator instruction rate (inst/s) +host_mem_usage 350148 # Number of bytes of host memory used +host_seconds 380.99 # Real time elapsed on the host +host_tick_rate 218804000 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 51961461 # Number of instructions simulated -sim_seconds 0.084388 # Number of seconds simulated -sim_ticks 84388283500 # Number of ticks simulated +sim_insts 51966326 # Number of instructions simulated +sim_seconds 0.083363 # Number of seconds simulated +sim_ticks 83363125500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 9710586 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 12489985 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 157419 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 644152 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11960647 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14006556 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 818238 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8358835 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 766788 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 9109525 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 11661597 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 155432 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 643707 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11148181 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 13121145 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 795550 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8359370 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 811751 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 96225527 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.541277 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.325518 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 94793091 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.549507 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.345543 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 74314309 77.23% 77.23% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 10868177 11.29% 88.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 3539344 3.68% 92.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 1575243 1.64% 93.84% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 3605097 3.75% 97.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 765856 0.80% 98.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 506916 0.53% 98.91% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 283797 0.29% 99.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 766788 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 73158899 77.18% 77.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 10643869 11.23% 88.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 3426640 3.61% 92.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 1618432 1.71% 93.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 3558653 3.75% 97.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 736107 0.78% 98.26% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 543274 0.57% 98.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 295466 0.31% 99.14% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 811751 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 96225527 # Number of insts commited each cycle -system.cpu.commit.COM:count 52084641 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 94793091 # Number of insts commited each cycle +system.cpu.commit.COM:count 52089506 # Number of instructions committed system.cpu.commit.COM:fp_insts 6017 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 529465 # Number of function calls committed. -system.cpu.commit.COM:int_insts 42494142 # Number of committed integer instructions. -system.cpu.commit.COM:loads 9208604 # Number of loads committed +system.cpu.commit.COM:function_calls 529550 # Number of function calls committed. +system.cpu.commit.COM:int_insts 42498657 # Number of committed integer instructions. +system.cpu.commit.COM:loads 9209715 # Number of loads committed system.cpu.commit.COM:membars 3 # Number of memory barriers committed -system.cpu.commit.COM:refs 16292498 # Number of memory references committed +system.cpu.commit.COM:refs 16294715 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 712712 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 52084641 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 2962577 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 21317023 # The number of squashed insts skipped by commit -system.cpu.committedInsts 51961461 # Number of Instructions Simulated -system.cpu.committedInsts_total 51961461 # Number of Instructions Simulated -system.cpu.cpi 3.248111 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.248111 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 110709 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 110709 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15013.262803 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 710936 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 52089506 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 2963004 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 16584310 # The number of squashed insts skipped by commit +system.cpu.committedInsts 51966326 # Number of Instructions Simulated +system.cpu.committedInsts_total 51966326 # Number of Instructions Simulated +system.cpu.cpi 3.208352 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.208352 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 110398 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 110398 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14987.700535 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11890.992284 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11878.197102 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.cpu.dcache.LoadLockedReq_hits::0 104187 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 104187 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 97916500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058911 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 6522 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6522 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 949 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66268500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050339 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_hits::0 103853 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 103853 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 98094500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.059285 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 6545 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6545 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 954 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66411000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050644 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5573 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 312424000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_accesses::0 10044139 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 10044139 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 14270.972361 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 5591 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 312483000 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_accesses::0 9405887 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9405887 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 14818.902196 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13253.335400 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13268.493454 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 9552480 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 9552480 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 7016452000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.048950 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 491659 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 491659 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 243263 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3292075500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.024730 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 8919589 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8919589 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 7206402500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.051701 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 486298 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 486298 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 238048 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3293903500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026393 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 248396 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38191881500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 104612 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 104612 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 104612 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 104612 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6670215 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6670215 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 39957.308282 # average WriteReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 248250 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38193579000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 105006 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 105006 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 105006 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 105006 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6670914 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6670914 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 39947.948992 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38553.884427 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38533.384242 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 4625539 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4625539 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 81699749268 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.306538 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 2044676 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2044676 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1874256 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 6570352984 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025549 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 4625272 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4625272 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 81719202272 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.306651 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 2045642 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2045642 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1875083 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 6572215483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025568 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 170420 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 939854183 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7310.688742 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21687.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.045188 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 906 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 24 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 6623484 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 520500 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 170559 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 939908183 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7476.302863 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21020 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 32.546615 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 908 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 25 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 6788483 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 525500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 16714354 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 16076801 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 16714354 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 34978.108676 # average overall miss latency +system.cpu.dcache.demand_accesses::total 16076801 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 35121.529251 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23548.356519 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 14178019 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23557.561998 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 13544861 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 14178019 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 88716201268 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.151746 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 13544861 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 88925604772 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.157490 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 2536335 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 2531940 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2536335 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2117519 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9862428484 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.025057 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 2531940 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2113131 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 9866118983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.026051 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 418816 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 418809 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999523 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.755643 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 16714354 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::0 0.999517 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.752645 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 16076801 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 16714354 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 34978.108676 # average overall miss latency +system.cpu.dcache.overall_accesses::total 16076801 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 35121.529251 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23548.356519 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23557.561998 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 14178019 # number of overall hits +system.cpu.dcache.overall_hits::0 13544861 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 14178019 # number of overall hits -system.cpu.dcache.overall_miss_latency 88716201268 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.151746 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 13544861 # number of overall hits +system.cpu.dcache.overall_miss_latency 88925604772 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.157490 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 2536335 # number of overall misses +system.cpu.dcache.overall_misses::0 2531940 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2536335 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2117519 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9862428484 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.025057 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 2531940 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2113131 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 9866118983 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.026051 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 418816 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 39131735683 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 418809 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 39133487183 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 422122 # number of replacements -system.cpu.dcache.sampled_refs 422634 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 422131 # number of replacements +system.cpu.dcache.sampled_refs 422643 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.755643 # Cycle average of tags in use -system.cpu.dcache.total_refs 14388654 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 48260000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 390579 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 54500037 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 71855 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 1270879 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 84249767 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 24736930 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 15841745 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 3334409 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 234983 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1146787 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 36041317 # DTB accesses -system.cpu.dtb.align_faults 1606 # Number of TLB faults due to alignment restrictions +system.cpu.dcache.tagsinuse 511.752645 # Cycle average of tags in use +system.cpu.dcache.total_refs 13755599 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 48259000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 390426 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 54881827 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 71596 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 1214700 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 77864847 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 24077327 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 14646912 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2655366 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 235100 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1186997 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 35220915 # DTB accesses +system.cpu.dtb.align_faults 1535 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2757 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2767 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 35961278 # DTB hits +system.cpu.dtb.hits 35140303 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 80039 # DTB misses -system.cpu.dtb.perms_faults 987 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 1022 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 28355137 # DTB read accesses -system.cpu.dtb.read_hits 28285868 # DTB read hits -system.cpu.dtb.read_misses 69269 # DTB read misses -system.cpu.dtb.write_accesses 7686180 # DTB write accesses -system.cpu.dtb.write_hits 7675410 # DTB write hits -system.cpu.dtb.write_misses 10770 # DTB write misses -system.cpu.fetch.Branches 14006556 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 6998275 # Number of cache lines fetched -system.cpu.fetch.Cycles 17468426 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 310113 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 71954338 # Number of instructions fetch has processed -system.cpu.fetch.ItlbSquashes 4839 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.MiscStallCycles 24771 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 1293063 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 7917 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.branchRate 0.082989 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 6996896 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 10528824 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.426329 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 99559908 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.876249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150340 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.misses 80612 # DTB misses +system.cpu.dtb.perms_faults 1012 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 1019 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 27731873 # DTB read accesses +system.cpu.dtb.read_hits 27661932 # DTB read hits +system.cpu.dtb.read_misses 69941 # DTB read misses +system.cpu.dtb.write_accesses 7489042 # DTB write accesses +system.cpu.dtb.write_hits 7478371 # DTB write hits +system.cpu.dtb.write_misses 10671 # DTB write misses +system.cpu.fetch.Branches 13121145 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 6614824 # Number of cache lines fetched +system.cpu.fetch.Cycles 16225603 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 267333 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 65526878 # Number of instructions fetch has processed +system.cpu.fetch.ItlbSquashes 4933 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.MiscStallCycles 21202 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1110741 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 8007 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.branchRate 0.078699 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 6613458 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9905075 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.393021 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 97448429 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.824712 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.089384 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 82110011 82.47% 82.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1333573 1.34% 83.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1775516 1.78% 85.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1526454 1.53% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4859277 4.88% 92.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 919627 0.92% 92.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 887823 0.89% 93.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 767860 0.77% 94.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5379767 5.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 81239523 83.37% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1275012 1.31% 84.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1734122 1.78% 86.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1277387 1.31% 87.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4689721 4.81% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 799978 0.82% 93.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 845081 0.87% 94.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 738625 0.76% 95.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4848980 4.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 99559908 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 5295 # number of floating regfile reads -system.cpu.fp_regfile_writes 1908 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses::0 6998182 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6998182 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14604.698564 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 97448429 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 5433 # number of floating regfile reads +system.cpu.fp_regfile_writes 1933 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses::0 6614731 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6614731 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14762.027587 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12005.361734 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12010.787096 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 6432138 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6432138 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8266901994 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.080884 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 566044 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 566044 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 56788 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6113802495 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.072770 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 6061711 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6061711 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8163696496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.083604 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 553020 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 553020 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 43430 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 6120576996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.077039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 509256 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 509590 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable_latency 4968000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.avg_blocked_cycles::no_mshrs 6198.435115 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6801.619835 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 12.630486 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 131 # number of cycles access was blocked +system.cpu.icache.avg_refs 11.895551 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 811995 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 822996 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 6998182 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 6614731 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6998182 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14604.698564 # average overall miss latency +system.cpu.icache.demand_accesses::total 6614731 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14762.027587 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12005.361734 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 6432138 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 12010.787096 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 6061711 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6432138 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8266901994 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.080884 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 6061711 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8163696496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.083604 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 566044 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 553020 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 566044 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 56788 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6113802495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.072770 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 553020 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 43430 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 6120576996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.077039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 509256 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 509590 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.968631 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 495.939326 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 6998182 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.969182 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 496.221044 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 6614731 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6998182 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14604.698564 # average overall miss latency +system.cpu.icache.overall_accesses::total 6614731 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14762.027587 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12005.361734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12010.787096 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 6432138 # number of overall hits +system.cpu.icache.overall_hits::0 6061711 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 6432138 # number of overall hits -system.cpu.icache.overall_miss_latency 8266901994 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.080884 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 6061711 # number of overall hits +system.cpu.icache.overall_miss_latency 8163696496 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.083604 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 566044 # number of overall misses +system.cpu.icache.overall_misses::0 553020 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 566044 # number of overall misses -system.cpu.icache.overall_mshr_hits 56788 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6113802495 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.072770 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 553020 # number of overall misses +system.cpu.icache.overall_mshr_hits 43430 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 6120576996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.077039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 509256 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 509590 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 4968000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 508743 # number of replacements -system.cpu.icache.sampled_refs 509255 # Sample count of references to valid blocks. +system.cpu.icache.replacements 509066 # number of replacements +system.cpu.icache.sampled_refs 509578 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 495.939326 # Cycle average of tags in use -system.cpu.icache.total_refs 6432138 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 6683845000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 41856 # number of writebacks -system.cpu.idleCycles 69216660 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 10300528 # Number of branches executed -system.cpu.iew.EXEC:nop 233998 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.477549 # Inst execution rate -system.cpu.iew.EXEC:refs 36776263 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7992235 # Number of stores executed +system.cpu.icache.tagsinuse 496.221044 # Cycle average of tags in use +system.cpu.icache.total_refs 6061711 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 6357615000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 41956 # number of writebacks +system.cpu.idleCycles 69277823 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 10103883 # Number of branches executed +system.cpu.iew.EXEC:nop 231467 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.472681 # Inst execution rate +system.cpu.iew.EXEC:refs 35943577 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7792930 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 64109547 # num instructions consuming a value -system.cpu.iew.WB:count 62439853 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.508921 # average fanout of values written-back +system.cpu.iew.WB:consumers 62506487 # num instructions consuming a value +system.cpu.iew.WB:count 60999387 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.509822 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32626666 # num instructions producing a value -system.cpu.iew.WB:rate 0.369956 # insts written-back per cycle -system.cpu.iew.WB:sent 79765366 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 803947 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 21361717 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 14069931 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4021819 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 473480 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 9383175 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 75615816 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 28784028 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1481918 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 80599112 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 30204 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 31867154 # num instructions producing a value +system.cpu.iew.WB:rate 0.365866 # insts written-back per cycle +system.cpu.iew.WB:sent 78280633 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 793572 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 21409899 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 12831645 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4013649 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 440829 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 8731029 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 70887049 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 28150647 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1185759 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 78808302 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 28695 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 45946 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 3334409 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 259259 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 45726 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2655366 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 263937 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 8096 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 314225 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 20180 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 8278 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 328988 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 7892 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 524894 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 17006252 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 4861327 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 2299281 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 524894 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 291334 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 512613 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 187216676 # number of integer regfile reads -system.cpu.int_regfile_writes 45171594 # number of integer regfile writes -system.cpu.ipc 0.307871 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.307871 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2392951 2.92% 2.92% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 42044414 51.22% 54.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 91848 0.11% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 12 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 7 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 869 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 54.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 29326853 35.73% 89.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 8224069 10.02% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 280623 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 17006286 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 3621930 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1646029 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 280623 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 286587 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 506985 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 183036764 # number of integer regfile reads +system.cpu.int_regfile_writes 44051569 # number of integer regfile writes +system.cpu.ipc 0.311687 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.311687 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2392951 2.99% 2.99% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 41025492 51.29% 54.28% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 89631 0.11% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 14 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 1 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 9 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 1 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 1 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 1 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 882 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 10 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 54.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 28522924 35.66% 90.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 7962144 9.95% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 82081030 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4843845 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.059013 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 79994061 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 4819476 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.060248 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 4773 0.10% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 1 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 4516251 93.24% 93.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 322820 6.66% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 5122 0.11% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 4502393 93.42% 93.53% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 311961 6.47% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 99559908 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.824439 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.384503 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 97448429 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.820886 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.375646 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 62623940 62.90% 62.90% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 16850481 16.92% 79.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 7354837 7.39% 87.21% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 4227768 4.25% 91.46% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 6061654 6.09% 97.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1452072 1.46% 99.01% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 668981 0.67% 99.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 244691 0.25% 99.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 75484 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 61152445 62.75% 62.75% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 16744626 17.18% 79.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 7216759 7.41% 87.34% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 4112834 4.22% 91.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 5964384 6.12% 97.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 1312092 1.35% 99.03% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 631511 0.65% 99.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 239871 0.25% 99.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 73907 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 99559908 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.486330 # Inst issue rate -system.cpu.iq.fp_alu_accesses 8335 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 15849 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 6220 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 8867 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 84523589 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 268809983 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 62433633 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 98520423 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 71330415 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 82081030 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4051403 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 22670381 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 180259 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1088826 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 31630143 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 7013299 # DTB accesses +system.cpu.iq.ISSUE:issued_per_cycle::total 97448429 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.479793 # Inst issue rate +system.cpu.iq.fp_alu_accesses 8478 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 16113 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 6290 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 9126 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 82412108 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 262450164 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 60993097 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 88832185 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 66612352 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 79994061 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4043230 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 17919898 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 129886 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1080226 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 22542223 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 6629825 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 1597 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 1593 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 7005382 # DTB hits -system.cpu.itb.inst_accesses 7013299 # ITB inst accesses -system.cpu.itb.inst_hits 7005382 # ITB inst hits -system.cpu.itb.inst_misses 7917 # ITB inst misses -system.cpu.itb.misses 7917 # DTB misses -system.cpu.itb.perms_faults 6664 # Number of TLB faults due to permissions restrictions +system.cpu.itb.hits 6621818 # DTB hits +system.cpu.itb.inst_accesses 6629825 # ITB inst accesses +system.cpu.itb.inst_hits 6621818 # ITB inst hits +system.cpu.itb.inst_misses 8007 # ITB inst misses +system.cpu.itb.misses 8007 # DTB misses +system.cpu.itb.perms_faults 6553 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits @@ -510,37 +510,37 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.memDep0.conflictingLoads 10842 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21645 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 14069931 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9383175 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 92602547 # number of misc regfile reads -system.cpu.misc_regfile_writes 661893 # number of misc regfile writes -system.cpu.numCycles 168776568 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 3412 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10055 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 12831645 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8731029 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 85580617 # number of misc regfile reads +system.cpu.misc_regfile_writes 661928 # number of misc regfile writes +system.cpu.numCycles 166726252 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 32961979 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 36893255 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 568385 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 26505270 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2459966 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 448573 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 208179443 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 80158855 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 58599384 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 14253451 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 3334409 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5274094 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 21706128 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 46818 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 208132625 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 17230705 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 870043 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 14712923 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 727497 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 167920116 # The number of ROB reads -system.cpu.rob.rob_writes 150187680 # The number of ROB writes -system.cpu.timesIdled 1086772 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 33115020 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 36897186 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 774970 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 25771675 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2462995 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 448472 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 192653284 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 74465658 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 54282132 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 13171967 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2655366 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5478763 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 17384945 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 47581 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 192605703 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 17255638 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 861623 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 14920123 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 719344 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 161714856 # The number of ROB reads +system.cpu.rob.rob_writes 140047516 # The number of ROB writes +system.cpu.timesIdled 1095909 # Number of times that the entire CPU went into an idle state and unscheduled itself system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -609,142 +609,142 @@ system.iocache.total_refs 0 # To system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.l2c.LoadLockedReq_mshr_uncacheable_latency 234163500 # number of LoadLockedReq MSHR uncacheable cycles -system.l2c.ReadExReq_accesses::0 168750 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 168750 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52449.907829 # average ReadExReq miss latency +system.l2c.LoadLockedReq_mshr_uncacheable_latency 234200000 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.ReadExReq_accesses::0 168831 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 168831 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52452.308619 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40012.010079 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 60799 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 60799 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 5662020000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.639710 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 107951 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107951 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4319336500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.639710 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40012.249340 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 60866 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 60866 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 5663013500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.639486 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 107965 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107965 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4319922500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.639486 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 107951 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 760723 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 115478 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 876201 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52673.934298 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 6776716.981132 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 6829390.915430 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40041.287971 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 107965 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 760970 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 118352 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 879322 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52680.502591 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 6692714.285714 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 6745394.788305 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40041.751725 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 740267 # number of ReadReq hits -system.l2c.ReadReq_hits::1 115319 # number of ReadReq hits -system.l2c.ReadReq_hits::total 855586 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 1077498000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.026890 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.001377 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028267 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 20456 # number of ReadReq misses -system.l2c.ReadReq_misses::1 159 # number of ReadReq misses +system.l2c.ReadReq_hits::0 740516 # number of ReadReq hits +system.l2c.ReadReq_hits::1 118191 # number of ReadReq hits +system.l2c.ReadReq_hits::total 858707 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 1077527000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.026879 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.001360 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028239 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 20454 # number of ReadReq misses +system.l2c.ReadReq_misses::1 161 # number of ReadReq misses system.l2c.ReadReq_misses::total 20615 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 823849500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027047 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.178172 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.205219 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 20575 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 28940574500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1755 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1755 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 785.423926 # average UpgradeReq miss latency +system.l2c.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 823819000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027037 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.173837 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.200874 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 20574 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 28941133500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1757 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1757 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 817.335660 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.580720 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 33 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 1352500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.981197 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1722 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1722 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 68881000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.981197 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.581734 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 38 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 1405000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.978372 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1719 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1719 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 68761000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.978372 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1722 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1719 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 746022447 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 432435 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 432435 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 432435 # number of Writeback hits -system.l2c.Writeback_hits::total 432435 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 746054947 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 432382 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 432382 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 432382 # number of Writeback hits +system.l2c.Writeback_hits::total 432382 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 8.330108 # Average number of references to valid blocks. +system.l2c.avg_refs 8.321857 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 929473 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 115478 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1044951 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52485.596580 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 42386905.660377 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 42439391.256957 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40016.697011 # average overall mshr miss latency -system.l2c.demand_hits::0 801066 # number of demand (read+write) hits -system.l2c.demand_hits::1 115319 # number of demand (read+write) hits -system.l2c.demand_hits::total 916385 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6739518000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.138150 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.001377 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.139527 # miss rate for demand accesses -system.l2c.demand_misses::0 128407 # number of demand (read+write) misses -system.l2c.demand_misses::1 159 # number of demand (read+write) misses -system.l2c.demand_misses::total 128566 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 40 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5143186000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.138278 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.112991 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.251270 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 128526 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses::0 929801 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 118352 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1048153 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52488.654327 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 41866711.180124 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 41919199.834451 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40016.971503 # average overall mshr miss latency +system.l2c.demand_hits::0 801382 # number of demand (read+write) hits +system.l2c.demand_hits::1 118191 # number of demand (read+write) hits +system.l2c.demand_hits::total 919573 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6740540500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.138114 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.001360 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.139475 # miss rate for demand accesses +system.l2c.demand_misses::0 128419 # number of demand (read+write) misses +system.l2c.demand_misses::1 161 # number of demand (read+write) misses +system.l2c.demand_misses::total 128580 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 41 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 5143741500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.138244 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.086074 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.224317 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 128539 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.099103 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.480856 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 6494.821877 # Average occupied blocks per context -system.l2c.occ_blocks::1 31513.354871 # Average occupied blocks per context -system.l2c.overall_accesses::0 929473 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 115478 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1044951 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52485.596580 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 42386905.660377 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 42439391.256957 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40016.697011 # average overall mshr miss latency +system.l2c.occ_%::0 0.099437 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.480717 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 6516.698147 # Average occupied blocks per context +system.l2c.occ_blocks::1 31504.278077 # Average occupied blocks per context +system.l2c.overall_accesses::0 929801 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 118352 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1048153 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52488.654327 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 41866711.180124 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 41919199.834451 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40016.971503 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 801066 # number of overall hits -system.l2c.overall_hits::1 115319 # number of overall hits -system.l2c.overall_hits::total 916385 # number of overall hits -system.l2c.overall_miss_latency 6739518000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.138150 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.001377 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.139527 # miss rate for overall accesses -system.l2c.overall_misses::0 128407 # number of overall misses -system.l2c.overall_misses::1 159 # number of overall misses -system.l2c.overall_misses::total 128566 # number of overall misses -system.l2c.overall_mshr_hits 40 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5143186000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.138278 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.112991 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.251270 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 128526 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 29686596947 # number of overall MSHR uncacheable cycles +system.l2c.overall_hits::0 801382 # number of overall hits +system.l2c.overall_hits::1 118191 # number of overall hits +system.l2c.overall_hits::total 919573 # number of overall hits +system.l2c.overall_miss_latency 6740540500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.138114 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.001360 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.139475 # miss rate for overall accesses +system.l2c.overall_misses::0 128419 # number of overall misses +system.l2c.overall_misses::1 161 # number of overall misses +system.l2c.overall_misses::total 128580 # number of overall misses +system.l2c.overall_mshr_hits 41 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 5143741500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.138244 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.086074 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.224317 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 128539 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 29687188447 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 94872 # number of replacements -system.l2c.sampled_refs 127034 # Sample count of references to valid blocks. +system.l2c.replacements 94739 # number of replacements +system.l2c.sampled_refs 127041 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 38008.176748 # Cycle average of tags in use -system.l2c.total_refs 1058207 # Total number of references to valid blocks. +system.l2c.tagsinuse 38020.976224 # Cycle average of tags in use +system.l2c.total_refs 1057217 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87774 # number of writebacks +system.l2c.writebacks 87634 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status index 9541cca97..f27ebe211 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status @@ -1 +1 @@ -build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 passed. +build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 FAILED! diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal Binary files differindex 2766f586d..5219ab85a 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal |