diff options
Diffstat (limited to 'tests/long/10.linux-boot/ref')
6 files changed, 1547 insertions, 1526 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 460e84f55..1430c935e 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -8,11 +8,12 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux +load_addr_mask=1099511627775 mem_mode=timing -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -660,7 +661,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -680,7 +681,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -806,7 +807,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 9cd052175..592fcc28f 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout +Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 3 2010 18:29:42 -M5 revision 75205c286109 7549 default qtip tip ext/memorderviolation_uncached.patch -M5 started Aug 3 2010 18:34:19 -M5 executing on harpertown2 -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual +M5 compiled Aug 26 2010 12:51:14 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:51:16 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /root/ali/dist/system/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 125751000 -Exiting @ tick 1908681362500 because m5_exit instruction encountered +info: Launching CPU 1 @ 125480500 +Exiting @ tick 1906675009500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index e9f6d4b39..a77677815 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,449 +1,449 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 149891 # Simulator instruction rate (inst/s) -host_mem_usage 287008 # Number of bytes of host memory used -host_seconds 374.37 # Real time elapsed on the host -host_tick_rate 5098345411 # Simulator tick rate (ticks/s) +host_inst_rate 96877 # Simulator instruction rate (inst/s) +host_mem_usage 294552 # Number of bytes of host memory used +host_seconds 589.85 # Real time elapsed on the host +host_tick_rate 3232468675 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56115151 # Number of instructions simulated -sim_seconds 1.908681 # Number of seconds simulated -sim_ticks 1908681362500 # Number of ticks simulated +sim_insts 57142904 # Number of instructions simulated +sim_seconds 1.906675 # Number of seconds simulated +sim_ticks 1906675009500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 6470772 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 12459992 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 36652 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 761921 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 11628226 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 13936368 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 988790 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 8127927 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 948928 # number cycles where commit BW limit reached +system.cpu0.BPredUnit.BTBHits 6037320 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 11351967 # Number of BTB lookups +system.cpu0.BPredUnit.RASInCorrect 27838 # Number of incorrect RAS predictions. +system.cpu0.BPredUnit.condIncorrect 689824 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 10583458 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 12665096 # Number of BP lookups +system.cpu0.BPredUnit.usedRAS 889173 # Number of times the RAS was used to get a target. +system.cpu0.commit.COM:branches 7532122 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 868474 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 96210525 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.559994 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 1.324793 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 85531488 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.582160 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 1.346009 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0 73079830 75.96% 75.96% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1 10159186 10.56% 86.52% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2 5793964 6.02% 92.54% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3 2862156 2.97% 95.51% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4 1992019 2.07% 97.59% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5 630403 0.66% 98.24% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6 376031 0.39% 98.63% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7 368008 0.38% 99.01% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 948928 0.99% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0 64118131 74.96% 74.96% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1 9419985 11.01% 85.98% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2 5464530 6.39% 92.37% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3 2511151 2.94% 95.30% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4 1836761 2.15% 97.45% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5 609168 0.71% 98.16% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6 353146 0.41% 98.58% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7 350142 0.41% 98.98% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 868474 1.02% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 96210525 # Number of insts commited each cycle -system.cpu0.commit.COM:count 53877339 # Number of instructions committed -system.cpu0.commit.COM:loads 8834098 # Number of loads committed -system.cpu0.commit.COM:membars 219262 # Number of memory barriers committed -system.cpu0.commit.COM:refs 14863142 # Number of memory references committed +system.cpu0.commit.COM:committed_per_cycle::total 85531488 # Number of insts commited each cycle +system.cpu0.commit.COM:count 49793044 # Number of instructions committed +system.cpu0.commit.COM:loads 8087035 # Number of loads committed +system.cpu0.commit.COM:membars 188923 # Number of memory barriers committed +system.cpu0.commit.COM:refs 13499415 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 723488 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 53877339 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 642718 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 8676299 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 50753913 # Number of Instructions Simulated -system.cpu0.committedInsts_total 50753913 # Number of Instructions Simulated -system.cpu0.cpi 2.598475 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.598475 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses::0 205122 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 205122 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15332.515478 # average LoadLockedReq miss latency +system.cpu0.commit.branchMispredicts 656667 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 49793044 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 558254 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 7909295 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 46950766 # Number of Instructions Simulated +system.cpu0.committedInsts_total 46950766 # Number of Instructions Simulated +system.cpu0.cpi 2.557983 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.557983 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses::0 175325 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 175325 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 13891.838160 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11584.904538 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 183317 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 183317 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 334325500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106303 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 21805 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21805 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 4992 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 194777000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.081966 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10378.791946 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::0 156714 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156714 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 258541000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106151 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 18611 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18611 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 3711 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 154644000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084985 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16813 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 8824783 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8824783 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 24295.121423 # average ReadReq miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses 14900 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::0 8024582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8024582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 24823.193475 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23079.908159 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23777.445948 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 7389262 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7389262 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 34876157000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.162669 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 1435521 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1435521 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 389370 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 24145069000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.118547 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits::0 6693712 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6693712 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 33036443500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::0 0.165849 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1330870 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1330870 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 349277 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 23339774500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122323 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 1046151 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 922902000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 210601 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 210601 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 55488.433658 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_mshr_misses 981593 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 922661000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses::0 183239 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 183239 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 47093.631014 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52488.433658 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 182459 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 182459 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 1561555500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.133627 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 28142 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 28142 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1477129500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.133627 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 44096.203773 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits::0 165905 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 165905 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 816321000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.094598 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 17334 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 17334 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 764319500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.094592 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 28142 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 5803460 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5803460 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 48954.080777 # average WriteReq miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses 17333 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses::0 5213801 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5213801 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 48517.051427 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 54100.546465 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53069.050136 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 3719396 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3719396 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 102023437400 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.359107 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 2084064 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2084064 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1707487 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 20373021486 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.064888 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_hits::0 3350446 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3350446 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 90404490361 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::0 0.357389 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 1863355 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1863355 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1547991 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 16736067927 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.060486 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 376577 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1266172497 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9947.496514 # average number of cycles each access was blocked +system.cpu0.dcache.WriteReq_mshr_misses 315364 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1337193497 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9713.605174 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 8.716740 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 127068 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 1264008487 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 150500 # number of cycles access was blocked +system.cpu0.dcache.avg_refs 8.464502 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 124903 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 1213258427 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 129000 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 14628243 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::0 13238383 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14628243 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 38896.516038 # average overall miss latency +system.cpu0.dcache.demand_accesses::total 13238383 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 38645.034041 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 31290.654634 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 11108658 # number of demand (read+write) hits +system.cpu0.dcache.demand_avg_mshr_miss_latency 30899.900634 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::0 10044158 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11108658 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 136899594400 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.240602 # miss rate for demand accesses +system.cpu0.dcache.demand_hits::total 10044158 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 123440933861 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::0 0.241285 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 3519585 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 3194225 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3519585 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 2096857 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 44518090486 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.097259 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_misses::total 3194225 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1897268 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 40075842427 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0.097969 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1422728 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses 1296957 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.984997 # Average percentage of cache occupancy -system.cpu0.dcache.occ_%::1 -0.015306 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 504.318463 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -7.836780 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses::0 14628243 # number of overall (read+write) accesses +system.cpu0.dcache.occ_%::0 0.975170 # Average percentage of cache occupancy +system.cpu0.dcache.occ_%::1 -0.005787 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 499.286946 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -2.962988 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses::0 13238383 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14628243 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 38896.516038 # average overall miss latency +system.cpu0.dcache.overall_accesses::total 13238383 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 38645.034041 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 31290.654634 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 30899.900634 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 11108658 # number of overall hits +system.cpu0.dcache.overall_hits::0 10044158 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 11108658 # number of overall hits -system.cpu0.dcache.overall_miss_latency 136899594400 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.240602 # miss rate for overall accesses +system.cpu0.dcache.overall_hits::total 10044158 # number of overall hits +system.cpu0.dcache.overall_miss_latency 123440933861 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate::0 0.241285 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 3519585 # number of overall misses +system.cpu0.dcache.overall_misses::0 3194225 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 3519585 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 2096857 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 44518090486 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.097259 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_misses::total 3194225 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1897268 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 40075842427 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate::0 0.097969 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1422728 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2189074497 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_misses 1296957 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2259854497 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 1343392 # number of replacements -system.cpu0.dcache.sampled_refs 1343785 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1243005 # number of replacements +system.cpu0.dcache.sampled_refs 1243517 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 500.400077 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11713425 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 404610 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 46313195 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 39259 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 576703 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 69095576 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 36458125 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 12314815 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1498947 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 124799 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 1124389 # Number of cycles decode is unblocking -system.cpu0.dtb.data_accesses 818221 # DTB accesses -system.cpu0.dtb.data_acv 799 # DTB access violations -system.cpu0.dtb.data_hits 15815368 # DTB hits -system.cpu0.dtb.data_misses 34536 # DTB misses +system.cpu0.dcache.tagsinuse 497.305455 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10525752 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 379678 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 40702182 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 33733 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 526303 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 63705520 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 32342676 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 11446881 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1370864 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 100557 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 1039748 # Number of cycles decode is unblocking +system.cpu0.dtb.data_accesses 867376 # DTB accesses +system.cpu0.dtb.data_acv 796 # DTB access violations +system.cpu0.dtb.data_hits 14352894 # DTB hits +system.cpu0.dtb.data_misses 32526 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 609919 # DTB read accesses -system.cpu0.dtb.read_acv 595 # DTB read access violations -system.cpu0.dtb.read_hits 9601809 # DTB read hits -system.cpu0.dtb.read_misses 28742 # DTB read misses -system.cpu0.dtb.write_accesses 208302 # DTB write accesses -system.cpu0.dtb.write_acv 204 # DTB write access violations -system.cpu0.dtb.write_hits 6213559 # DTB write hits -system.cpu0.dtb.write_misses 5794 # DTB write misses -system.cpu0.fetch.Branches 13936368 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 8499965 # Number of cache lines fetched -system.cpu0.fetch.Cycles 22177505 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 429825 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 70536565 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 1947 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 890409 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.105672 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 8499965 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 7459562 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.534843 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 97709472 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.721901 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.017707 # Number of instructions fetched each cycle (Total) +system.cpu0.dtb.read_accesses 645773 # DTB read accesses +system.cpu0.dtb.read_acv 589 # DTB read access violations +system.cpu0.dtb.read_hits 8766713 # DTB read hits +system.cpu0.dtb.read_misses 26860 # DTB read misses +system.cpu0.dtb.write_accesses 221603 # DTB write accesses +system.cpu0.dtb.write_acv 207 # DTB write access violations +system.cpu0.dtb.write_hits 5586181 # DTB write hits +system.cpu0.dtb.write_misses 5666 # DTB write misses +system.cpu0.fetch.Branches 12665096 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 7900913 # Number of cache lines fetched +system.cpu0.fetch.Cycles 20614864 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 378846 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 65028610 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 1156 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 811969 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.105455 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 7900913 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 6926493 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.541457 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 86902352 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.748295 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.044395 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 84062445 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 970614 0.99% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1876169 1.92% 88.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 899130 0.92% 89.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2879231 2.95% 92.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 630716 0.65% 93.46% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 762992 0.78% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1157633 1.18% 95.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4470542 4.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 74220009 85.41% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 901339 1.04% 86.44% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1804427 2.08% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 827724 0.95% 89.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2764395 3.18% 92.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 592140 0.68% 93.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 693087 0.80% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 935405 1.08% 95.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4163826 4.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 97709472 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses::0 8499965 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8499965 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 14903.591508 # average ReadReq miss latency +system.cpu0.fetch.rateDist::total 86902352 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses::0 7900913 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7900913 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 15047.285683 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11868.979380 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 7487466 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7487466 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 15089871498 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.119118 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 1012499 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1012499 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 44617 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 11487771500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.113869 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12005.143233 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits::0 7053204 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7053204 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 12755719499 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate::0 0.107293 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 847709 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 847709 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 37907 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 9721789000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.102495 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 967882 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11795.081967 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_mshr_misses 809802 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11235.849057 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 7.736856 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 61 # number of cycles access was blocked +system.cpu0.icache.avg_refs 8.711370 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 53 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 719500 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 595500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 8499965 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::0 7900913 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8499965 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 14903.591508 # average overall miss latency +system.cpu0.icache.demand_accesses::total 7900913 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 15047.285683 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11868.979380 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 7487466 # number of demand (read+write) hits +system.cpu0.icache.demand_avg_mshr_miss_latency 12005.143233 # average overall mshr miss latency +system.cpu0.icache.demand_hits::0 7053204 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7487466 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 15089871498 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.119118 # miss rate for demand accesses +system.cpu0.icache.demand_hits::total 7053204 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 12755719499 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::0 0.107293 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 1012499 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::0 847709 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1012499 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 44617 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 11487771500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.113869 # mshr miss rate for demand accesses +system.cpu0.icache.demand_misses::total 847709 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 37907 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 9721789000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0.102495 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 967882 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses 809802 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.995784 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 509.841410 # Average occupied blocks per context -system.cpu0.icache.overall_accesses::0 8499965 # number of overall (read+write) accesses +system.cpu0.icache.occ_%::0 0.995703 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 509.799701 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 7900913 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8499965 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 14903.591508 # average overall miss latency +system.cpu0.icache.overall_accesses::total 7900913 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 15047.285683 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11868.979380 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12005.143233 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 7487466 # number of overall hits +system.cpu0.icache.overall_hits::0 7053204 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 7487466 # number of overall hits -system.cpu0.icache.overall_miss_latency 15089871498 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.119118 # miss rate for overall accesses +system.cpu0.icache.overall_hits::total 7053204 # number of overall hits +system.cpu0.icache.overall_miss_latency 12755719499 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::0 0.107293 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 1012499 # number of overall misses +system.cpu0.icache.overall_misses::0 847709 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 1012499 # number of overall misses -system.cpu0.icache.overall_mshr_hits 44617 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 11487771500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.113869 # mshr miss rate for overall accesses +system.cpu0.icache.overall_misses::total 847709 # number of overall misses +system.cpu0.icache.overall_mshr_hits 37907 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 9721789000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::0 0.102495 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 967882 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses 809802 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 967254 # number of replacements -system.cpu0.icache.sampled_refs 967766 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 809144 # number of replacements +system.cpu0.icache.sampled_refs 809655 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.841410 # Cycle average of tags in use -system.cpu0.icache.total_refs 7487466 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 25290449000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 34173281 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 8768783 # Number of branches executed -system.cpu0.iew.EXEC:nop 3557044 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.415997 # Inst execution rate -system.cpu0.iew.EXEC:refs 16085074 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 6233455 # Number of stores executed +system.cpu0.icache.tagsinuse 509.799701 # Cycle average of tags in use +system.cpu0.icache.total_refs 7053204 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 25253244000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 2 # number of writebacks +system.cpu0.idleCycles 33196891 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 8125364 # Number of branches executed +system.cpu0.iew.EXEC:nop 3226641 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.422366 # Inst execution rate +system.cpu0.iew.EXEC:refs 14615271 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 5604883 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 32865773 # num instructions consuming a value -system.cpu0.iew.WB:count 54347309 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.764091 # average fanout of values written-back +system.cpu0.iew.WB:consumers 31032245 # num instructions consuming a value +system.cpu0.iew.WB:count 50227097 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.763961 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 25112440 # num instructions producing a value -system.cpu0.iew.WB:rate 0.412088 # insts written-back per cycle -system.cpu0.iew.WB:sent 54432899 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 782239 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 9442019 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 10379600 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1744642 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 949306 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 6581023 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 62660146 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 9851619 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 507857 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 54862889 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 45824 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 23707433 # num instructions producing a value +system.cpu0.iew.WB:rate 0.418213 # insts written-back per cycle +system.cpu0.iew.WB:sent 50304093 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 713455 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 9315247 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 9510497 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1499135 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 880070 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 5918886 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 57821470 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 9010388 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 501816 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 50725864 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 38579 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 5354 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1498947 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 539585 # Number of cycles IEW is unblocking +system.cpu0.iew.iewLSQFullEvents 5036 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1370864 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 530507 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 260747 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 417328 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 12574 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.cacheBlocked 262065 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 407910 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 13281 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 44391 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 18291 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1545502 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 551979 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 44391 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 381079 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 401160 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.384841 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.384841 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3316 0.01% 0.01% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 37941800 68.52% 68.53% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 60296 0.11% 68.64% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15720 0.03% 68.67% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1656 0.00% 68.67% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 10184712 18.39% 87.06% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 6276896 11.34% 98.40% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IprAccess 886350 1.60% 100.00% # Type of FU issued +system.cpu0.iew.lsq.thread.0.memOrderViolation 40793 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 18036 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1423462 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 506506 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 40793 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 332881 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 380574 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.390933 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.390933 # IPC: Total IPC of All Threads +system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35394718 69.09% 69.10% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 55798 0.11% 69.21% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15086 0.03% 69.24% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.24% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.24% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.24% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1884 0.00% 69.24% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.24% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 9327899 18.21% 87.45% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645566 11.02% 98.47% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IprAccess 782961 1.53% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 55370746 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 397277 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.007175 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 51227682 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 363911 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007104 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 49080 12.35% 12.35% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 12.35% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.35% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.35% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.35% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.35% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.35% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.35% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.35% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 256090 64.46% 76.82% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 92107 23.18% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 39751 10.92% 10.92% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.92% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.92% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.92% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.92% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.92% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.92% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.92% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.92% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 236746 65.06% 75.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 87414 24.02% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 97709472 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.566688 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.134817 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 86902352 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.589486 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.157706 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0 70054320 71.70% 71.70% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1 13865334 14.19% 85.89% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2 6040088 6.18% 92.07% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3 3813933 3.90% 95.97% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4 2397035 2.45% 98.43% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5 977877 1.00% 99.43% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6 439666 0.45% 99.88% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7 101836 0.10% 99.98% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 19383 0.02% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0 61545337 70.82% 70.82% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1 12554046 14.45% 85.27% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2 5586431 6.43% 91.70% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3 3486187 4.01% 95.71% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4 2264793 2.61% 98.31% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5 945170 1.09% 99.40% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6 407098 0.47% 99.87% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7 91717 0.11% 99.98% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 21573 0.02% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 97709472 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.419848 # Inst issue rate -system.cpu0.iq.iqInstsAdded 57116410 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 55370746 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1986692 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 7999373 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 32356 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 1343974 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 4128104 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.ISSUE:issued_per_cycle::total 86902352 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.426545 # Inst issue rate +system.cpu0.iq.iqInstsAdded 52886391 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 51227682 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1708438 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 7322246 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 33660 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 1150184 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3910877 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 1054719 # ITB accesses -system.cpu0.itb.fetch_acv 886 # ITB acv -system.cpu0.itb.fetch_hits 1025087 # ITB hits -system.cpu0.itb.fetch_misses 29632 # ITB misses +system.cpu0.itb.fetch_accesses 999568 # ITB accesses +system.cpu0.itb.fetch_acv 893 # ITB acv +system.cpu0.itb.fetch_hits 968847 # ITB hits +system.cpu0.itb.fetch_misses 30721 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_hits 0 # DTB read hits @@ -453,550 +453,550 @@ system.cpu0.itb.write_acv 0 # DT system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 98 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3879 2.08% 2.14% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.16% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal::swpipl 170561 91.53% 93.70% # number of callpals executed -system.cpu0.kern.callpal::rdps 6398 3.43% 97.13% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.13% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.13% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.14% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.14% # number of callpals executed -system.cpu0.kern.callpal::rti 4815 2.58% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 186345 # number of callpals executed +system.cpu0.kern.callpal::wripir 393 0.25% 0.25% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.25% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.25% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.25% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3319 2.08% 2.33% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.36% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.36% # number of callpals executed +system.cpu0.kern.callpal::swpipl 144424 90.42% 92.78% # number of callpals executed +system.cpu0.kern.callpal::rdps 6390 4.00% 96.78% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.79% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.79% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.79% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.79% # number of callpals executed +system.cpu0.kern.callpal::rti 4592 2.87% 99.67% # number of callpals executed +system.cpu0.kern.callpal::callsys 391 0.24% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 159723 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 201175 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6392 # number of quiesce instructions executed -system.cpu0.kern.ipl_count::0 72147 40.63% 40.63% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 239 0.13% 40.77% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1932 1.09% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 7 0.00% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 103229 58.14% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 177554 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 70781 49.24% 49.24% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 239 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1932 1.34% 50.75% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 7 0.00% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 70775 49.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 143734 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1865669134000 97.77% 97.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 102063500 0.01% 97.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 400489500 0.02% 97.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4470500 0.00% 97.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 42089413000 2.21% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1908265570500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981066 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 175260 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6689 # number of quiesce instructions executed +system.cpu0.kern.ipl_count::0 61186 40.39% 40.39% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 239 0.16% 40.55% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1930 1.27% 41.82% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 300 0.20% 42.02% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 87830 57.98% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 151485 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 60407 49.12% 49.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 239 0.19% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1930 1.57% 50.88% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 300 0.24% 51.13% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 60108 48.87% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 122984 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1866417310500 97.89% 97.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 97564500 0.01% 97.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 399841000 0.02% 97.91% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 136212500 0.01% 97.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 39623165500 2.08% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1906674094000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.987268 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685612 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good::kernel 1283 -system.cpu0.kern.mode_good::user 1283 +system.cpu0.kern.ipl_used::31 0.684368 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1353 +system.cpu0.kern.mode_good::user 1354 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch::kernel 7354 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 7157 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1354 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.174463 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.189046 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1906087309000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2155018500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1904400738500 99.88% 99.88% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2273347500 0.12% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3880 # number of times the context was actually changed -system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 222 # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 2868331 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2616560 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 10379600 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6581023 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 131882753 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 13878265 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 36623956 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 1040563 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 38000902 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 2220107 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 18213 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 79075810 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 65194392 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 43691484 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 11998481 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1498947 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 5027996 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 7067528 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 27304879 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1597966 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 12274299 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 247715 # count of temporary serializing insts renamed -system.cpu0.timesIdled 1299056 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.kern.swap_context 3320 # number of times the context was actually changed +system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed +system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 232 # number of syscalls executed +system.cpu0.memDep0.conflictingLoads 2539862 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2208172 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 9510497 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5918886 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 120099243 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 13446049 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 34012953 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 1022261 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 33782009 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1807708 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 16757 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 73652966 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 60220724 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 40595001 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 11156910 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1370864 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 4406747 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 6582046 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 22739771 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1403717 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 10900390 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 213877 # count of temporary serializing insts renamed +system.cpu0.timesIdled 1182515 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 641418 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 1453120 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 4656 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 99987 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 1369738 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 1655319 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 114912 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 786729 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 111651 # number cycles where commit BW limit reached +system.cpu1.BPredUnit.BTBHits 1168869 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 2724358 # Number of BTB lookups +system.cpu1.BPredUnit.RASInCorrect 8216 # Number of incorrect RAS predictions. +system.cpu1.BPredUnit.condIncorrect 170435 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 2536443 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 3058879 # Number of BP lookups +system.cpu1.BPredUnit.usedRAS 214059 # Number of times the RAS was used to get a target. +system.cpu1.commit.COM:branches 1536055 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 205800 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 9662936 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.576830 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.391062 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 19921603 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.539460 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.350836 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0 7270313 75.24% 75.24% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1 1222307 12.65% 87.89% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2 443469 4.59% 92.48% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3 257393 2.66% 95.14% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4 152904 1.58% 96.72% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5 87632 0.91% 97.63% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6 71404 0.74% 98.37% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7 45863 0.47% 98.84% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 111651 1.16% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0 15476427 77.69% 77.69% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1 2094576 10.51% 88.20% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2 801789 4.02% 92.23% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3 588293 2.95% 95.18% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4 417407 2.10% 97.27% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5 144338 0.72% 98.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6 104661 0.53% 98.52% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7 88312 0.44% 98.97% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 205800 1.03% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 9662936 # Number of insts commited each cycle -system.cpu1.commit.COM:count 5573873 # Number of instructions committed -system.cpu1.commit.COM:loads 1110708 # Number of loads committed -system.cpu1.commit.COM:membars 18999 # Number of memory barriers committed -system.cpu1.commit.COM:refs 1809440 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 19921603 # Number of insts commited each cycle +system.cpu1.commit.COM:count 10746901 # Number of instructions committed +system.cpu1.commit.COM:loads 2021572 # Number of loads committed +system.cpu1.commit.COM:membars 56653 # Number of memory barriers committed +system.cpu1.commit.COM:refs 3430255 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 95993 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 5573873 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 71139 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 1244666 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 5361238 # Number of Instructions Simulated -system.cpu1.committedInsts_total 5361238 # Number of Instructions Simulated -system.cpu1.cpi 2.006382 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.006382 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses::0 15265 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 15265 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14429.127726 # average LoadLockedReq miss latency +system.cpu1.commit.branchMispredicts 163240 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 10746901 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 172585 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 1766208 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 10192138 # Number of Instructions Simulated +system.cpu1.committedInsts_total 10192138 # Number of Instructions Simulated +system.cpu1.cpi 2.158157 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.158157 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses::0 48648 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 48648 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 10962.569444 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10666.666667 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 13981 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 13981 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 18527000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.084114 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 1284 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1284 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 240 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11136000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.068392 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7807.164404 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::0 41448 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 41448 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 78930500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.148002 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 7200 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 7200 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 570 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 51761500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.136285 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 1044 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 1203979 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1203979 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 18427.853599 # average ReadReq miss latency +system.cpu1.dcache.LoadLockedReq_mshr_misses 6630 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::0 2081061 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2081061 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 16526.110109 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13573.416201 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11960.136769 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 1110045 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1110045 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 1731002000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.078020 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 93934 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 93934 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 53146 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 553632500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.033878 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits::0 1891958 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1891958 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 3125137000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::0 0.090869 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 189103 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 189103 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 93175 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 1147312000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046096 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 40788 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 15686000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 14051 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 14051 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 45874.534161 # average StoreCondReq miss latency +system.cpu1.dcache.ReadReq_mshr_misses 95928 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 16183000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses::0 45890 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 45890 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 35468.138068 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 42893.537697 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 11636 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 11636 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 110787000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.171874 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 2415 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2415 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 103545000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.171803 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 32471.951759 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits::0 36851 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 36851 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 320596500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.196971 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 9039 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9039 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 293481500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.196949 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 2414 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 679686 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 679686 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 48846.469056 # average WriteReq miss latency +system.cpu1.dcache.StoreCondReq_mshr_misses 9038 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses::0 1356401 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1356401 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 48468.442060 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 52388.154254 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 50000.550136 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 517989 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 517989 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 7898327507 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.237900 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 161697 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 161697 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 135111 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 1392791469 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.039115 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_hits::0 1038709 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1038709 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 15398036295 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::0 0.234217 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 317692 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 317692 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 255162 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 3126534400 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.046100 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 26586 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 309596000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12811.786863 # average number of cycles each access was blocked +system.cpu1.dcache.WriteReq_mshr_misses 62530 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 383884000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11747.407108 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 28.408620 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 11875 # number of cycles access was blocked +system.cpu1.dcache.avg_refs 23.303685 # Average number of references to valid blocks. +system.cpu1.dcache.blocked::no_mshrs 12380 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 152139969 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 145432900 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 1883665 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::0 3437462 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1883665 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 37668.864523 # average overall miss latency +system.cpu1.dcache.demand_accesses::total 3437462 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 36549.637023 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 28889.838350 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 1628034 # number of demand (read+write) hits +system.cpu1.dcache.demand_avg_mshr_miss_latency 26971.477616 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::0 2930667 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1628034 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 9629329507 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.135709 # miss rate for demand accesses +system.cpu1.dcache.demand_hits::total 2930667 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 18523173295 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::0 0.147433 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 255631 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 506795 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 255631 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 188257 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 1946423969 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.035768 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_misses::total 506795 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 348337 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 4273846400 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0.046097 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 67374 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses 158458 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.773778 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 396.174503 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses::0 1883665 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.929332 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 475.817757 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 3437462 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1883665 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 37668.864523 # average overall miss latency +system.cpu1.dcache.overall_accesses::total 3437462 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 36549.637023 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 28889.838350 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 26971.477616 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 1628034 # number of overall hits +system.cpu1.dcache.overall_hits::0 2930667 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 1628034 # number of overall hits -system.cpu1.dcache.overall_miss_latency 9629329507 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.135709 # miss rate for overall accesses +system.cpu1.dcache.overall_hits::total 2930667 # number of overall hits +system.cpu1.dcache.overall_miss_latency 18523173295 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::0 0.147433 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 255631 # number of overall misses +system.cpu1.dcache.overall_misses::0 506795 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 255631 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 188257 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 1946423969 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.035768 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_misses::total 506795 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 348337 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 4273846400 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::0 0.046097 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 67374 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 325282000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_misses 158458 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 400067000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 58281 # number of replacements -system.cpu1.dcache.sampled_refs 58793 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 131481 # number of replacements +system.cpu1.dcache.sampled_refs 131801 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 396.174503 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1670228 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1884260206000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 26579 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 4231249 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:BranchMispred 4060 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 70345 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 7846841 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 3945555 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 1457789 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 213951 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 12437 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 28342 # Number of cycles decode is unblocking -system.cpu1.dtb.data_accesses 436826 # DTB accesses -system.cpu1.dtb.data_acv 92 # DTB access violations -system.cpu1.dtb.data_hits 2033744 # DTB hits -system.cpu1.dtb.data_misses 11106 # DTB misses +system.cpu1.dcache.tagsinuse 475.817757 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3071449 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1882597271000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 66520 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 8690485 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BranchMispred 7262 # Number of times decode detected a branch misprediction +system.cpu1.decode.DECODE:BranchResolved 129460 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 14175016 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 8601755 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 2517670 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 311026 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 21330 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 111692 # Number of cycles decode is unblocking +system.cpu1.dtb.data_accesses 379731 # DTB accesses +system.cpu1.dtb.data_acv 79 # DTB access violations +system.cpu1.dtb.data_hits 3682802 # DTB hits +system.cpu1.dtb.data_misses 10764 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 315884 # DTB read accesses -system.cpu1.dtb.read_acv 16 # DTB read access violations -system.cpu1.dtb.read_hits 1299460 # DTB read hits -system.cpu1.dtb.read_misses 8720 # DTB read misses -system.cpu1.dtb.write_accesses 120942 # DTB write accesses -system.cpu1.dtb.write_acv 76 # DTB write access violations -system.cpu1.dtb.write_hits 734284 # DTB write hits -system.cpu1.dtb.write_misses 2386 # DTB write misses -system.cpu1.fetch.Branches 1655319 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 983571 # Number of cache lines fetched -system.cpu1.fetch.Cycles 2495244 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 54744 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 8005120 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 119648 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.153887 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 983571 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 756330 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.744199 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 9876887 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.810490 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.152603 # Number of instructions fetched each cycle (Total) +system.cpu1.dtb.read_accesses 273464 # DTB read accesses +system.cpu1.dtb.read_acv 11 # DTB read access violations +system.cpu1.dtb.read_hits 2232523 # DTB read hits +system.cpu1.dtb.read_misses 8601 # DTB read misses +system.cpu1.dtb.write_accesses 106267 # DTB write accesses +system.cpu1.dtb.write_acv 68 # DTB write access violations +system.cpu1.dtb.write_hits 1450279 # DTB write hits +system.cpu1.dtb.write_misses 2163 # DTB write misses +system.cpu1.fetch.Branches 3058879 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 1688815 # Number of cache lines fetched +system.cpu1.fetch.Cycles 4357354 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 105751 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 14416907 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 179 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 193553 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.139064 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 1688815 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 1382928 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.655426 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 20232629 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.712557 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.050166 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 8372049 84.76% 84.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 99748 1.01% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 205638 2.08% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 130058 1.32% 89.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 234183 2.37% 91.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 78658 0.80% 92.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 103423 1.05% 93.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 71678 0.73% 94.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 581452 5.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 17569535 86.84% 86.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 215879 1.07% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 322874 1.60% 89.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 192834 0.95% 90.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 374265 1.85% 92.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 129017 0.64% 92.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 159403 0.79% 93.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 272361 1.35% 95.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 996461 4.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 9876887 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses::0 983571 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 983571 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 14895.250407 # average ReadReq miss latency +system.cpu1.fetch.rateDist::total 20232629 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses::0 1688815 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1688815 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14598.075134 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11864.081295 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 879141 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 879141 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 1555511000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.106174 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 104430 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 104430 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 4006 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 1191438500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.102101 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11541.965319 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits::0 1410406 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1410406 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 4064235500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::0 0.164855 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 278409 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 278409 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 7888 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 3122344000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.160184 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 100424 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6636.363636 # average number of cycles each access was blocked +system.cpu1.icache.ReadReq_mshr_misses 270521 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs 8125 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 8.759351 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu1.icache.avg_refs 5.214764 # Average number of references to valid blocks. +system.cpu1.icache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_mshrs 73000 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 65000 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 983571 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::0 1688815 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 983571 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 14895.250407 # average overall miss latency +system.cpu1.icache.demand_accesses::total 1688815 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14598.075134 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11864.081295 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 879141 # number of demand (read+write) hits +system.cpu1.icache.demand_avg_mshr_miss_latency 11541.965319 # average overall mshr miss latency +system.cpu1.icache.demand_hits::0 1410406 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 879141 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 1555511000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.106174 # miss rate for demand accesses +system.cpu1.icache.demand_hits::total 1410406 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 4064235500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::0 0.164855 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 104430 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::0 278409 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 104430 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 4006 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 1191438500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.102101 # mshr miss rate for demand accesses +system.cpu1.icache.demand_misses::total 278409 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 7888 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 3122344000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0.160184 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 100424 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses 270521 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.866895 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 443.850090 # Average occupied blocks per context -system.cpu1.icache.overall_accesses::0 983571 # number of overall (read+write) accesses +system.cpu1.icache.occ_%::0 0.900098 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 460.849961 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 1688815 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 983571 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 14895.250407 # average overall miss latency +system.cpu1.icache.overall_accesses::total 1688815 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14598.075134 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11864.081295 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11541.965319 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 879141 # number of overall hits +system.cpu1.icache.overall_hits::0 1410406 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 879141 # number of overall hits -system.cpu1.icache.overall_miss_latency 1555511000 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.106174 # miss rate for overall accesses +system.cpu1.icache.overall_hits::total 1410406 # number of overall hits +system.cpu1.icache.overall_miss_latency 4064235500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::0 0.164855 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 104430 # number of overall misses +system.cpu1.icache.overall_misses::0 278409 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 104430 # number of overall misses -system.cpu1.icache.overall_mshr_hits 4006 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 1191438500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.102101 # mshr miss rate for overall accesses +system.cpu1.icache.overall_misses::total 278409 # number of overall misses +system.cpu1.icache.overall_mshr_hits 7888 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 3122344000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::0 0.160184 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 100424 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses 270521 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 99855 # number of replacements -system.cpu1.icache.sampled_refs 100366 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 269955 # number of replacements +system.cpu1.icache.sampled_refs 270464 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 443.850090 # Cycle average of tags in use -system.cpu1.icache.total_refs 879141 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1897353320500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 460.849961 # Cycle average of tags in use +system.cpu1.icache.total_refs 1410406 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1902950008000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 879803 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 868251 # Number of branches executed -system.cpu1.iew.EXEC:nop 253715 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.554813 # Inst execution rate -system.cpu1.iew.EXEC:refs 2051713 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 739910 # Number of stores executed +system.cpu1.idleCycles 1763601 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 1647161 # Number of branches executed +system.cpu1.iew.EXEC:nop 633873 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.498846 # Inst execution rate +system.cpu1.iew.EXEC:refs 3712298 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 1459673 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 3750224 # num instructions consuming a value -system.cpu1.iew.WB:count 5855863 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.732329 # average fanout of values written-back +system.cpu1.iew.WB:consumers 6255206 # num instructions consuming a value +system.cpu1.iew.WB:count 10847139 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.739229 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 2746396 # num instructions producing a value -system.cpu1.iew.WB:rate 0.544393 # insts written-back per cycle -system.cpu1.iew.WB:sent 5874071 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 104878 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 312048 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 1391930 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 267781 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 126811 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 802099 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 6897856 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 1311803 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 68901 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 5967953 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 3132 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 4624029 # num instructions producing a value +system.cpu1.iew.WB:rate 0.493136 # insts written-back per cycle +system.cpu1.iew.WB:sent 10867556 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 177268 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 332920 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 2358529 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 525453 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 201798 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 1538474 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 12592629 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 2252625 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 104488 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 10972727 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 3148 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 1266 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 213951 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 8244 # Number of cycles IEW is unblocking +system.cpu1.iew.iewLSQFullEvents 1572 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 311026 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 9766 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 56759 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 34660 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 1926 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.cacheBlocked 50281 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 68629 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 4124 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 7014 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 360 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 281222 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 103367 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 7014 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 58993 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 45885 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.498410 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.498410 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3973 0.07% 0.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 3726705 61.73% 61.80% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 10086 0.17% 61.97% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.97% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 10031 0.17% 62.13% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1986 0.03% 62.16% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.16% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 1347365 22.32% 84.48% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 752050 12.46% 96.94% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IprAccess 184660 3.06% 100.00% # Type of FU issued +system.cpu1.iew.lsq.thread.0.memOrderViolation 9401 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 371 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 336957 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 129791 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 9401 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 104860 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 72408 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.463358 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.463358 # IPC: Total IPC of All Threads +system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3519 0.03% 0.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6926354 62.53% 62.56% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 18692 0.17% 62.73% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.73% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11838 0.11% 62.84% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1759 0.02% 62.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 2331483 21.05% 83.90% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1476157 13.33% 97.22% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307413 2.78% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 6036856 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 101607 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.016831 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 11077215 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 158215 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.014283 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 3728 3.67% 3.67% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 3.67% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.67% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.67% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.67% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.67% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.67% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 63305 62.30% 65.97% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 34574 34.03% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 4066 2.57% 2.57% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.57% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.57% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.57% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.57% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.57% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.57% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.57% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.57% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 92866 58.70% 61.27% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 61283 38.73% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 9876887 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.611210 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.231461 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 20232629 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.547493 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.152304 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0 7028128 71.16% 71.16% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1 1406586 14.24% 85.40% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2 558070 5.65% 91.05% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3 375734 3.80% 94.85% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4 282352 2.86% 97.71% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5 133259 1.35% 99.06% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6 62266 0.63% 99.69% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7 26307 0.27% 99.96% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 4185 0.04% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0 14868449 73.49% 73.49% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1 2672522 13.21% 86.70% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2 1102181 5.45% 92.14% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3 699877 3.46% 95.60% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4 518299 2.56% 98.16% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5 241576 1.19% 99.36% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6 93786 0.46% 99.82% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7 30604 0.15% 99.97% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 5335 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 9876887 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.561219 # Inst issue rate -system.cpu1.iq.iqInstsAdded 6356285 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 6036856 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 287856 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 1234181 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 8959 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 216717 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 734853 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.ISSUE:issued_per_cycle::total 20232629 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.503596 # Inst issue rate +system.cpu1.iq.iqInstsAdded 11373839 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 11077215 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 584917 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 1698901 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 10384 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 412332 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 877867 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 347409 # ITB accesses -system.cpu1.itb.fetch_acv 92 # ITB acv -system.cpu1.itb.fetch_hits 340665 # ITB hits -system.cpu1.itb.fetch_misses 6744 # ITB misses +system.cpu1.itb.fetch_accesses 413824 # ITB accesses +system.cpu1.itb.fetch_acv 100 # ITB acv +system.cpu1.itb.fetch_hits 408478 # ITB hits +system.cpu1.itb.fetch_misses 5346 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_hits 0 # DTB read hits @@ -1006,95 +1006,95 @@ system.cpu1.itb.write_acv 0 # DT system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 7 0.02% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 357 1.17% 1.20% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed -system.cpu1.kern.callpal::swpipl 25115 82.21% 83.44% # number of callpals executed -system.cpu1.kern.callpal::rdps 2369 7.75% 91.20% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.20% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 91.21% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.22% # number of callpals executed -system.cpu1.kern.callpal::rti 2501 8.19% 99.41% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.45% 99.85% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.14% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 300 0.50% 0.50% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.50% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.50% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1497 2.49% 3.00% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.00% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.02% # number of callpals executed +system.cpu1.kern.callpal::swpipl 52375 87.24% 90.26% # number of callpals executed +system.cpu1.kern.callpal::rdps 2373 3.95% 94.21% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.21% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.22% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.22% # number of callpals executed +system.cpu1.kern.callpal::rti 3300 5.50% 99.72% # number of callpals executed +system.cpu1.kern.callpal::callsys 124 0.21% 99.93% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 30551 # number of callpals executed +system.cpu1.kern.callpal::total 60033 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 37164 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2263 # number of quiesce instructions executed -system.cpu1.kern.ipl_count::0 9735 32.84% 32.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1929 6.51% 39.35% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 98 0.33% 39.68% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17882 60.32% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 29644 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 9724 45.49% 45.49% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1929 9.02% 54.51% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 98 0.46% 54.97% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 9626 45.03% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 21377 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1880211308500 98.51% 98.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 349210000 0.02% 98.53% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 40269500 0.00% 98.53% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28079728000 1.47% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1908680516000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998870 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 66427 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2553 # number of quiesce instructions executed +system.cpu1.kern.ipl_count::0 21855 37.68% 37.68% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1927 3.32% 41.01% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 393 0.68% 41.68% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 33821 58.32% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 57996 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 21257 47.83% 47.83% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1927 4.34% 52.17% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 393 0.88% 53.05% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 20864 46.95% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 44441 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874788065000 98.35% 98.35% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 349524500 0.02% 98.37% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 166729500 0.01% 98.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 30954744500 1.62% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1906259063500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.972638 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.538307 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 485 -system.cpu1.kern.mode_good::user 463 -system.cpu1.kern.mode_good::idle 22 -system.cpu1.kern.mode_switch::kernel 814 # number of protection mode switches -system.cpu1.kern.mode_switch::user 463 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.595823 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used::31 0.616895 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 700 +system.cpu1.kern.mode_good::user 383 +system.cpu1.kern.mode_good::idle 317 +system.cpu1.kern.mode_switch::kernel 1588 # number of protection mode switches +system.cpu1.kern.mode_switch::user 383 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2627 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.440806 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.010753 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.606576 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2177635500 0.11% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 994853500 0.05% 0.17% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1905508019000 99.83% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 358 # number of times the context was actually changed -system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed -system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 104 # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 249198 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 232138 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 1391930 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 802099 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 10756690 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 465609 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 3852724 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 44260 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 4077020 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 64277 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 71 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 8954426 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 7268297 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 4874919 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 1341579 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 213951 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 396189 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 1022193 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 3382537 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 292831 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 1228786 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 20447 # count of temporary serializing insts renamed -system.cpu1.timesIdled 85032 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.kern.mode_switch_good::idle 0.120670 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.561476 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 7544739000 0.40% 0.40% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 853569500 0.04% 0.44% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1897425262500 99.56% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1498 # number of times the context was actually changed +system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed +system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed +system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed +system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed +system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 94 # number of syscalls executed +system.cpu1.memDep0.conflictingLoads 510972 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 447437 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 2358529 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1538474 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 21996230 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 659886 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 7238905 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 29431 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 8848928 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 376341 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 2702 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 15628999 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 13115251 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 8582665 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 2365502 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 311026 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 913464 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 1343760 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 7133821 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 521569 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 2485864 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 55479 # count of temporary serializing insts renamed +system.cpu1.timesIdled 207727 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1107,282 +1107,291 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses::1 177 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::1 172 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115209.028249 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115273.244186 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63209.028249 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 20391998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63273.244186 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19826998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 177 # number of ReadReq misses -system.iocache.ReadReq_misses::total 177 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 11187998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_misses::1 172 # number of ReadReq misses +system.iocache.ReadReq_misses::total 172 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 10882998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 172 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137839.112582 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137834.973190 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85835.459039 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5727490806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85831.529120 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5727318806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3566634994 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3566471698 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6168.251363 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6167.680658 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10455 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64489068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64507772 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41729 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41724 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137743.123583 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137741.966350 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85739.485538 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85738.536478 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5747882804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5747145804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41729 # number of demand (read+write) misses -system.iocache.demand_misses::total 41729 # number of demand (read+write) misses +system.iocache.demand_misses::1 41724 # number of demand (read+write) misses +system.iocache.demand_misses::total 41724 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3577822992 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3577354696 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41729 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses 41724 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.029808 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 0.476933 # Average occupied blocks per context +system.iocache.occ_%::1 0.029720 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.475524 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41729 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41724 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137743.123583 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137741.966350 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85739.485538 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85738.536478 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5747882804 # number of overall miss cycles +system.iocache.overall_miss_latency 5747145804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41729 # number of overall misses -system.iocache.overall_misses::total 41729 # number of overall misses +system.iocache.overall_misses::1 41724 # number of overall misses +system.iocache.overall_misses::total 41724 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3577822992 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3577354696 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41729 # number of overall MSHR misses +system.iocache.overall_mshr_misses 41724 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 41697 # number of replacements -system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.replacements 41692 # number of replacements +system.iocache.sampled_refs 41708 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.476933 # Cycle average of tags in use +system.iocache.tagsinuse 0.475524 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1716189422000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1715203940000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses::0 284402 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 21091 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305493 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 56244.064064 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 758424.176568 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 257631 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 41153 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298784 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 60735.824013 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 380275.607871 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40208.821305 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15995924308 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 284402 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 21091 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 305493 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12283513447 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 1.074159 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 14.484519 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40207.175331 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 1663 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 271 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1934 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 15546427401 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.993545 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.993415 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 255968 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 40882 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 296850 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 11935499997 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 1.152229 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 7.213326 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 305493 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2026908 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 138381 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2165289 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52781.333033 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 3774241.528394 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 296850 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 1795093 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 360112 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2155205 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52872.781104 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3365794.496366 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40018.812855 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40019.494912 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1720929 # number of ReadReq hits -system.l2c.ReadReq_hits::1 134102 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1855031 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16149979500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.150959 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.030922 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 305979 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4279 # number of ReadReq misses -system.l2c.ReadReq_misses::total 310258 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1488578 # number of ReadReq hits +system.l2c.ReadReq_hits::1 355297 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1843875 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16206300500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.170752 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.013371 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 306515 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4815 # number of ReadReq misses +system.l2c.ReadReq_misses::total 311330 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12415436500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.153061 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.241926 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12458549000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.173424 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.864487 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 310240 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 840591500 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 27679 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 1917 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29596 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 55685.899057 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 804032.342201 # average SCUpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 311312 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 840831000 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 14188 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 5331 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 19519 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 67372.602257 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 179272.565209 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40005.270983 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_miss_latency 1541330000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 27679 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 1917 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 29596 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 1183996000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.069258 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 15.438706 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40011.251217 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_hits::0 8 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_miss_latency 955343500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 0.999436 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.999625 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 14180 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 5329 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 19509 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 780579500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.375035 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 3.659539 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 29596 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 95047 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 4764 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 99811 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 53254.442497 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 1062484.256087 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 19509 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 55251 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 16863 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 72114 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 64253.326605 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 210525.121307 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40129.945597 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 5061674996 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 95047 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 4764 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 99811 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 4005410000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.050123 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 20.951092 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency 40021.687237 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 5 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 21 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 3549032495 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.999710 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.999703 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 55235 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 16858 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 72093 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 2885283498 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.304827 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4.275218 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 99811 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 72093 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1422860998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 431189 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 431189 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 431189 # number of Writeback hits -system.l2c.Writeback_hits::total 431189 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1554057498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 446200 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 446200 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 446200 # number of Writeback hits +system.l2c.Writeback_hits::total 446200 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.720550 # Average number of references to valid blocks. +system.l2c.avg_refs 4.752489 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2311310 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 159472 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2052724 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 401265 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2470782 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 54449.421319 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1267083.319196 # average overall miss latency +system.l2c.demand_accesses::total 2453989 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 56451.000121 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 694853.664376 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40113.084644 # average overall mshr miss latency -system.l2c.demand_hits::0 1720929 # number of demand (read+write) hits -system.l2c.demand_hits::1 134102 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40111.103615 # average overall mshr miss latency +system.l2c.demand_hits::0 1490241 # number of demand (read+write) hits +system.l2c.demand_hits::1 355568 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1855031 # number of demand (read+write) hits -system.l2c.demand_miss_latency 32145903808 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.255431 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.159087 # miss rate for demand accesses +system.l2c.demand_hits::total 1845809 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31752727901 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.274018 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.113882 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 590381 # number of demand (read+write) misses -system.l2c.demand_misses::1 25370 # number of demand (read+write) misses +system.l2c.demand_misses::0 562483 # number of demand (read+write) misses +system.l2c.demand_misses::1 45697 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 615751 # number of demand (read+write) misses +system.l2c.demand_misses::total 608180 # number of demand (read+write) misses system.l2c.demand_mshr_hits 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24698949947 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.266400 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 3.861073 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 24394048997 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.296271 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.515612 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 615733 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 608162 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.092624 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.002915 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.372149 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 6070.232669 # Average occupied blocks per context -system.l2c.occ_blocks::1 191.043265 # Average occupied blocks per context -system.l2c.occ_blocks::2 24389.134195 # Average occupied blocks per context -system.l2c.overall_accesses::0 2311310 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 159472 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.174396 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.005052 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.332288 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 11429.229058 # Average occupied blocks per context +system.l2c.occ_blocks::1 331.081192 # Average occupied blocks per context +system.l2c.occ_blocks::2 21776.825321 # Average occupied blocks per context +system.l2c.overall_accesses::0 2052724 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 401265 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2470782 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 54449.421319 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1267083.319196 # average overall miss latency +system.l2c.overall_accesses::total 2453989 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 56451.000121 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 694853.664376 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40113.084644 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40111.103615 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1720929 # number of overall hits -system.l2c.overall_hits::1 134102 # number of overall hits +system.l2c.overall_hits::0 1490241 # number of overall hits +system.l2c.overall_hits::1 355568 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 1855031 # number of overall hits -system.l2c.overall_miss_latency 32145903808 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.255431 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.159087 # miss rate for overall accesses +system.l2c.overall_hits::total 1845809 # number of overall hits +system.l2c.overall_miss_latency 31752727901 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.274018 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.113882 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 590381 # number of overall misses -system.l2c.overall_misses::1 25370 # number of overall misses +system.l2c.overall_misses::0 562483 # number of overall misses +system.l2c.overall_misses::1 45697 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 615751 # number of overall misses +system.l2c.overall_misses::total 608180 # number of overall misses system.l2c.overall_mshr_hits 18 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24698949947 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.266400 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 3.861073 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 24394048997 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.296271 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.515612 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 615733 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2263452498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 608162 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2394888498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 399449 # number of replacements -system.l2c.sampled_refs 433881 # Sample count of references to valid blocks. +system.l2c.replacements 399060 # number of replacements +system.l2c.sampled_refs 435274 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30650.410129 # Cycle average of tags in use -system.l2c.total_refs 2048157 # Total number of references to valid blocks. -system.l2c.warmup_cycle 9278771000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 122161 # number of writebacks +system.l2c.tagsinuse 33537.135570 # Cycle average of tags in use +system.l2c.total_refs 2068635 # Total number of references to valid blocks. +system.l2c.warmup_cycle 9277782000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 122307 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 025857566..208609d63 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -8,11 +8,12 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux +load_addr_mask=1099511627775 mem_mode=timing -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -355,7 +356,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -375,7 +376,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -501,7 +502,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index adcdc6213..f8d53b80a 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simout +Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 3 2010 18:29:42 -M5 revision 75205c286109 7549 default qtip tip ext/memorderviolation_uncached.patch -M5 started Aug 3 2010 18:34:19 -M5 executing on harpertown2 -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 +M5 compiled Aug 26 2010 12:51:14 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:51:33 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /root/ali/dist/system/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1866391592500 because m5_exit instruction encountered +Exiting @ tick 1865288389500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index c77305609..df900ba3a 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,449 +1,449 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 152752 # Simulator instruction rate (inst/s) -host_mem_usage 285144 # Number of bytes of host memory used -host_seconds 347.60 # Real time elapsed on the host -host_tick_rate 5369308609 # Simulator tick rate (ticks/s) +host_inst_rate 83534 # Simulator instruction rate (inst/s) +host_mem_usage 292436 # Number of bytes of host memory used +host_seconds 635.06 # Real time elapsed on the host +host_tick_rate 2937207030 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53097060 # Number of instructions simulated -sim_seconds 1.866392 # Number of seconds simulated -sim_ticks 1866391592500 # Number of ticks simulated +sim_insts 53048754 # Number of instructions simulated +sim_seconds 1.865288 # Number of seconds simulated +sim_ticks 1865288389500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6779171 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 13000438 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 41604 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 815663 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 12121236 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14552347 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1031270 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8463090 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 978521 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 6766434 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 12986969 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 41472 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 813466 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 12097848 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14524578 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1028567 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8457223 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 1009026 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 100404039 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.560651 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.326562 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 98617953 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.570296 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.335991 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 76245214 75.94% 75.94% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 10678082 10.64% 86.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 5963966 5.94% 92.51% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 2979105 2.97% 95.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2071048 2.06% 97.54% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 686360 0.68% 98.23% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 408066 0.41% 98.63% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 393677 0.39% 99.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 978521 0.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 74454640 75.50% 75.50% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 10711227 10.86% 86.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 5970777 6.05% 92.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 2911969 2.95% 95.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2119464 2.15% 97.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 692478 0.70% 98.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 398357 0.40% 98.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 350015 0.35% 98.98% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 1009026 1.02% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 100404039 # Number of insts commited each cycle -system.cpu.commit.COM:count 56291624 # Number of instructions committed -system.cpu.commit.COM:loads 9309237 # Number of loads committed -system.cpu.commit.COM:membars 227993 # Number of memory barriers committed -system.cpu.commit.COM:refs 15703046 # Number of memory references committed +system.cpu.commit.COM:committed_per_cycle::total 98617953 # Number of insts commited each cycle +system.cpu.commit.COM:count 56241389 # Number of instructions committed +system.cpu.commit.COM:loads 9301917 # Number of loads committed +system.cpu.commit.COM:membars 227986 # Number of memory barriers committed +system.cpu.commit.COM:refs 15690474 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 774037 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56291624 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667808 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9441068 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53097060 # Number of Instructions Simulated -system.cpu.committedInsts_total 53097060 # Number of Instructions Simulated -system.cpu.cpi 2.576227 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.576227 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 214868 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 214868 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15521.971818 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 771977 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56241389 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667741 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 9346936 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53048754 # Number of Instructions Simulated +system.cpu.committedInsts_total 53048754 # Number of Instructions Simulated +system.cpu.cpi 2.541919 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.541919 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 214829 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214829 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15450.383219 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11812.528617 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 192726 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192726 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 343687500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103049 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 22142 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22142 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4670 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206388500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081315 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11789.484229 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 192518 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192518 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 344713500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103855 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 22311 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22311 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4842 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 205950500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081316 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17472 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9342824 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9342824 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 23958.883948 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 17469 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9301988 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9301988 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 23801.813261 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22784.089495 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22758.438856 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7810369 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7810369 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36715911500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.164025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1532455 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1532455 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 447788 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24713150000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116096 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7781909 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7781909 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 36180636500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.163414 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1520079 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1520079 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 436579 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24658768500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116480 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1084667 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904940500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 219839 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219839 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56332.793292 # average StoreCondReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 1083500 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904975000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 219792 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219792 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56335.990566 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53332.793292 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 189903 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 189903 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1686378500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate::0 0.136172 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 29936 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 29936 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1596570500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136172 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53335.990566 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::0 198592 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198592 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1194323000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate::0 0.096455 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 21200 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 21200 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1130723000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.096455 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 29936 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6158819 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6158819 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 48967.756734 # average WriteReq miss latency +system.cpu.dcache.StoreCondReq_mshr_misses 21200 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses::0 6153614 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6153614 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 48733.687858 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54205.115025 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53794.875061 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 3929838 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 3929838 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 109148199373 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.361917 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 2228981 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2228981 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1831921 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 21522682972 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 3986142 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 3986142 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 105628903889 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.352227 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 2167472 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2167472 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1799517 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 19794093253 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.059795 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 397060 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235704997 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9948.209554 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 34000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.830631 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 138723 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 1380045474 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 102000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 367955 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235122997 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9816.976394 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17750 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.810921 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 136746 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1342432254 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 35500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15501643 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15455602 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15501643 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 38778.836294 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15455602 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 38456.292642 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31204.015971 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 11740207 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 30626.414014 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 11768051 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11740207 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 145864110873 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.242648 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 11768051 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 141809540389 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.238590 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 3761436 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3687551 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3761436 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2279709 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 46235832972 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.095585 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 3687551 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2236096 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 44452861753 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.093911 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1481727 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1451455 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_%::1 -0.015267 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.995427 # Average occupied blocks per context -system.cpu.dcache.occ_blocks::1 -7.816935 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15501643 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::1 -0.007635 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.995459 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::1 -3.909039 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15455602 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15501643 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 38778.836294 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15455602 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 38456.292642 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31204.015971 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30626.414014 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 11740207 # number of overall hits +system.cpu.dcache.overall_hits::0 11768051 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11740207 # number of overall hits -system.cpu.dcache.overall_miss_latency 145864110873 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.242648 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 11768051 # number of overall hits +system.cpu.dcache.overall_miss_latency 141809540389 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.238590 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 3761436 # number of overall misses +system.cpu.dcache.overall_misses::0 3687551 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3761436 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2279709 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 46235832972 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.095585 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 3687551 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2236096 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 44452861753 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.093911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1481727 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2140645497 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1451455 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2140097997 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1401867 # number of replacements -system.cpu.dcache.sampled_refs 1402379 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1400442 # number of replacements +system.cpu.dcache.sampled_refs 1400954 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 508.086965 # Cycle average of tags in use -system.cpu.dcache.total_refs 12383892 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430752 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 48365906 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42626 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 618516 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 72644608 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37897287 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 12992433 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1631262 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 135583 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1148412 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1233977 # DTB accesses -system.cpu.dtb.data_acv 814 # DTB access violations -system.cpu.dtb.data_hits 16773992 # DTB hits -system.cpu.dtb.data_misses 45116 # DTB misses +system.cpu.dcache.tagsinuse 510.040943 # Cycle average of tags in use +system.cpu.dcache.total_refs 12343695 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21271000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 455265 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 46660710 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42482 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 616847 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 72473028 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37849528 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 12958836 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1616629 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 135444 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1148878 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1239402 # DTB accesses +system.cpu.dtb.data_acv 830 # DTB access violations +system.cpu.dtb.data_hits 16737953 # DTB hits +system.cpu.dtb.data_misses 44771 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 912580 # DTB read accesses -system.cpu.dtb.read_acv 580 # DTB read access violations -system.cpu.dtb.read_hits 10175278 # DTB read hits -system.cpu.dtb.read_misses 36864 # DTB read misses -system.cpu.dtb.write_accesses 321397 # DTB write accesses -system.cpu.dtb.write_acv 234 # DTB write access violations -system.cpu.dtb.write_hits 6598714 # DTB write hits -system.cpu.dtb.write_misses 8252 # DTB write misses -system.cpu.fetch.Branches 14552347 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8974775 # Number of cache lines fetched -system.cpu.fetch.Cycles 23368319 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 459035 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 74152954 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 1764 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 956539 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.106385 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8974775 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7810441 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.542093 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 102035301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.726738 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.024554 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_accesses 913549 # DTB read accesses +system.cpu.dtb.read_acv 594 # DTB read access violations +system.cpu.dtb.read_hits 10142643 # DTB read hits +system.cpu.dtb.read_misses 36670 # DTB read misses +system.cpu.dtb.write_accesses 325853 # DTB write accesses +system.cpu.dtb.write_acv 236 # DTB write access violations +system.cpu.dtb.write_hits 6595310 # DTB write hits +system.cpu.dtb.write_misses 8101 # DTB write misses +system.cpu.fetch.Branches 14524578 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8948260 # Number of cache lines fetched +system.cpu.fetch.Cycles 23311047 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 456775 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 73989590 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2537 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 952530 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.107713 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8948260 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7795001 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.548698 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 100234582 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.738164 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.038365 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 87682148 85.93% 85.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1045613 1.02% 86.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1977723 1.94% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 941704 0.92% 89.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2994515 2.93% 92.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 665574 0.65% 93.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 793530 0.78% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1216279 1.19% 95.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4718215 4.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 85912196 85.71% 85.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1042441 1.04% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1978378 1.97% 88.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 936363 0.93% 89.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2989129 2.98% 92.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 664727 0.66% 93.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 787515 0.79% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1214601 1.21% 95.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4709232 4.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 102035301 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses::0 8974775 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8974775 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14904.774114 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 100234582 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses::0 8948260 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8948260 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14907.888251 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11909.268781 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 7927523 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7927523 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15609054500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.116688 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 1047252 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1047252 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 51900 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11853914500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110906 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11902.318660 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 7903415 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7903415 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15576432500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.116765 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 1044845 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1044845 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 50305 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11837332000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111143 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 995352 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs 11612.068966 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses 994540 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs 12104.838710 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.966054 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked +system.cpu.icache.avg_refs 7.948315 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 62 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 673500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 750500 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 8974775 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 8948260 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8974775 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14904.774114 # average overall miss latency +system.cpu.icache.demand_accesses::total 8948260 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14907.888251 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11909.268781 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 7927523 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11902.318660 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 7903415 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7927523 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15609054500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.116688 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 7903415 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15576432500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.116765 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 1047252 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 1044845 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1047252 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 51900 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11853914500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.110906 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 1044845 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 50305 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11837332000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.111143 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 995352 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 994540 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.995668 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 509.782027 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 8974775 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.995598 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 509.746088 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 8948260 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8974775 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14904.774114 # average overall miss latency +system.cpu.icache.overall_accesses::total 8948260 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14907.888251 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11909.268781 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11902.318660 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 7927523 # number of overall hits +system.cpu.icache.overall_hits::0 7903415 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7927523 # number of overall hits -system.cpu.icache.overall_miss_latency 15609054500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.116688 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 7903415 # number of overall hits +system.cpu.icache.overall_miss_latency 15576432500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.116765 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 1047252 # number of overall misses +system.cpu.icache.overall_misses::0 1044845 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1047252 # number of overall misses -system.cpu.icache.overall_mshr_hits 51900 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11853914500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.110906 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 1044845 # number of overall misses +system.cpu.icache.overall_mshr_hits 50305 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11837332000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.111143 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 995352 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 994540 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 994652 # number of replacements -system.cpu.icache.sampled_refs 995163 # Sample count of references to valid blocks. +system.cpu.icache.replacements 993840 # number of replacements +system.cpu.icache.sampled_refs 994351 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.782027 # Cycle average of tags in use -system.cpu.icache.total_refs 7927522 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 25287688000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 34754768 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9169930 # Number of branches executed -system.cpu.iew.EXEC:nop 3653116 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.421040 # Inst execution rate -system.cpu.iew.EXEC:refs 17057862 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6621868 # Number of stores executed +system.cpu.icache.tagsinuse 509.746088 # Cycle average of tags in use +system.cpu.icache.total_refs 7903415 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 25251004000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 5 # number of writebacks +system.cpu.idleCycles 34611048 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9149461 # Number of branches executed +system.cpu.iew.EXEC:nop 3645494 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.426187 # Inst execution rate +system.cpu.iew.EXEC:refs 17021543 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6618330 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 34608006 # num instructions consuming a value -system.cpu.iew.WB:count 57003958 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.763082 # average fanout of values written-back +system.cpu.iew.WB:consumers 34491432 # num instructions consuming a value +system.cpu.iew.WB:count 56873596 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.763558 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26408756 # num instructions producing a value -system.cpu.iew.WB:rate 0.416726 # insts written-back per cycle -system.cpu.iew.WB:sent 57103806 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 838722 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9720732 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 11045282 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1800818 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1012071 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 7016985 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65863384 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10435994 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 546687 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57594091 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 49608 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 26336207 # num instructions producing a value +system.cpu.iew.WB:rate 0.421768 # insts written-back per cycle +system.cpu.iew.WB:sent 56969504 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 835772 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9640204 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 11032857 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1798988 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1002562 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 7014115 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65718389 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10403213 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 554442 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57469408 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 44506 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6610 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1631262 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 548180 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6661 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1616629 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 544895 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 312153 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 424842 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 8566 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 306779 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 434666 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 11993 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 45938 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15913 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1736045 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 623176 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 45938 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 406349 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 432373 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.388165 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.388165 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7290 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 39624499 68.15% 68.17% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 62169 0.11% 68.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25611 0.04% 68.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3637 0.01% 68.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 10788203 18.56% 86.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 6676137 11.48% 98.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 953234 1.64% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 45591 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 18153 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1730940 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 625558 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 45591 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 404736 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 431036 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.393404 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.393404 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7283 0.01% 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 39532589 68.13% 68.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 62065 0.11% 68.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25614 0.04% 68.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3637 0.01% 68.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 10774153 18.57% 86.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 6665338 11.49% 98.36% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 953173 1.64% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 58140780 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 443526 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007628 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 58023852 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 434401 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007487 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 49984 11.27% 11.27% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 286610 64.62% 75.89% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 106932 24.11% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 47887 11.02% 11.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 281518 64.81% 75.83% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 104996 24.17% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 102035301 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.569810 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.137806 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 100234582 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.578881 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.146223 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 72990338 71.53% 71.53% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 14544721 14.25% 85.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 6428267 6.30% 92.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 3926151 3.85% 95.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 2521969 2.47% 98.41% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1036804 1.02% 99.42% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 448412 0.44% 99.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 110408 0.11% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 28231 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 71270288 71.10% 71.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 14553068 14.52% 85.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 6335877 6.32% 91.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 3893576 3.88% 95.83% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 2543708 2.54% 98.37% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 1056426 1.05% 99.42% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 441326 0.44% 99.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 109120 0.11% 99.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 31193 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 102035301 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.425037 # Inst issue rate -system.cpu.iq.iqInstsAdded 60158404 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 58140780 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2051864 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8719443 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 37043 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1384056 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4669750 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 100234582 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.430298 # Inst issue rate +system.cpu.iq.iqInstsAdded 60022452 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 58023852 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2050443 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8631662 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 41705 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1382702 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4647656 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1303496 # ITB accesses -system.cpu.itb.fetch_acv 936 # ITB acv -system.cpu.itb.fetch_hits 1264039 # ITB hits -system.cpu.itb.fetch_misses 39457 # ITB misses +system.cpu.itb.fetch_accesses 1304111 # ITB accesses +system.cpu.itb.fetch_acv 934 # ITB acv +system.cpu.itb.fetch_hits 1264639 # ITB hits +system.cpu.itb.fetch_misses 39472 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -456,55 +456,55 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175675 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6793 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175665 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5220 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5219 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192644 # number of callpals executed +system.cpu.kern.callpal::total 192634 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211803 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211790 # number of hwrei instructions executed system.cpu.kern.inst.quiesce 6385 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 74956 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 237 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1889 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105940 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183022 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73589 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::0 74955 40.96% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 237 0.13% 41.09% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1888 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105930 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183010 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73588 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73589 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149304 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1823811543000 97.72% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 102514500 0.01% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 392104500 0.02% 97.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 42084556500 2.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1866390718500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981763 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1888 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73588 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149301 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1823061244500 97.74% 97.74% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 98162000 0.01% 97.74% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 391950000 0.02% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41736158500 2.24% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1865287515000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981762 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694629 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.ipl_used::31 0.694685 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch::kernel 5969 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::kernel 5970 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.319987 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.319765 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.401132 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 31305722000 1.68% 1.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 3191321000 0.17% 1.85% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1831893667500 98.15% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::total 1.400911 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 31031458000 1.66% 1.66% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 3177312000 0.17% 1.83% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1831078737000 98.17% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4179 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -536,29 +536,29 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.memDep0.conflictingLoads 3074116 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2796142 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 11045282 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7016985 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 136790069 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14275602 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38263165 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1103259 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39498573 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2244862 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 15668 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 83383655 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 68588182 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 45977130 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12625374 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1631262 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5234920 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7713963 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 28769568 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1705106 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 12848723 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 257016 # count of temporary serializing insts renamed -system.cpu.timesIdled 1324942 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.memDep0.conflictingLoads 3098880 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2694658 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 11032857 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7014115 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 134845630 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14093810 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38225332 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1080811 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39441227 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2214917 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 14670 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 83145881 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 68419430 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 45844130 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12603060 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1616629 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5180630 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7618796 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 27299224 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1703562 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 12710348 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 255623 # count of temporary serializing insts renamed +system.cpu.timesIdled 1320206 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -574,14 +574,14 @@ system.disk2.dma_write_txs 1 # Nu system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115277.445087 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63277.445087 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19942998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses::1 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10946998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses @@ -589,37 +589,37 @@ system.iocache.ReadReq_mshr_misses 173 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137775.337072 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137804.625674 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85771.897333 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5724840806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85801.092270 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5726057806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3563993878 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3565206986 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6162.366934 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6169.984712 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10466 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64556956 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64575060 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137682.056417 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137711.103751 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85678.630941 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85707.584997 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5744783804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5745995804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -627,7 +627,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3574940876 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3576148984 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -635,20 +635,20 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.078734 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.259751 # Average occupied blocks per context +system.iocache.occ_%::1 0.078725 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.259600 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137682.056417 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137711.103751 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85678.630941 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85707.584997 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5744783804 # number of overall miss cycles +system.iocache.overall_miss_latency 5745995804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -656,7 +656,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3574940876 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3576148984 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -666,152 +666,156 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.259751 # Cycle average of tags in use +system.iocache.tagsinuse 1.259600 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1716179733000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1715198512000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 301983 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 301983 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52369.131153 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 300711 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300711 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52369.611662 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40216.934384 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15814587333 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 301983 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 301983 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12144830496 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40214.373242 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 2213 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 2213 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 15632224342 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.992641 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 298498 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 298498 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12003909984 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.992641 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 301983 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2095788 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2095788 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52047.755815 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 298498 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2094821 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2094821 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52048.515602 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40015.737067 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40015.565251 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1785564 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1785564 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16146463000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.148023 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 310224 # number of ReadReq misses -system.l2c.ReadReq_misses::total 310224 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1784931 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1784931 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16129314500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.147931 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 309890 # number of ReadReq misses +system.l2c.ReadReq_misses::total 309890 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12413802000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.148022 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12400383500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.147931 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 310223 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 810507500 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 29936 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29936 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 52320.500401 # average SCUpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 309889 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 810515000 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 21199 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 21199 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 52327.059157 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40001.486505 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_miss_latency 1566266500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 29936 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 29936 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 1197484500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000.731201 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_hits::0 1 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_miss_latency 1109229000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 0.999953 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 21198 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 21198 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 847935500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.999953 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 29936 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 99242 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 99242 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52253.672780 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 21198 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 69854 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 69854 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52150.764423 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40126.292296 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 5185758994 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40013.263378 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 3642939498 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 99242 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 99242 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 3982213500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses::0 69854 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 69854 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 2795086500 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 99242 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 69854 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1116157498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 430752 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 430752 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 430752 # number of Writeback hits -system.l2c.Writeback_hits::total 430752 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1115590498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 455270 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 455270 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 455270 # number of Writeback hits +system.l2c.Writeback_hits::total 455270 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.598953 # Average number of references to valid blocks. +system.l2c.avg_refs 4.693284 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2397771 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2395532 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2397771 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52206.280446 # average overall miss latency +system.l2c.demand_accesses::total 2395532 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52206.057388 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40114.981715 # average overall mshr miss latency -system.l2c.demand_hits::0 1785564 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40113.108078 # average overall mshr miss latency +system.l2c.demand_hits::0 1787144 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1785564 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31961050333 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.255323 # miss rate for demand accesses +system.l2c.demand_hits::total 1787144 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31761538842 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.253968 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 612207 # number of demand (read+write) misses +system.l2c.demand_misses::0 608388 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 612207 # number of demand (read+write) misses +system.l2c.demand_misses::total 608388 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24558632496 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.255323 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 24404293484 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.253967 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 612206 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 608387 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.090384 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.378384 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5923.436811 # Average occupied blocks per context -system.l2c.occ_blocks::1 24797.788563 # Average occupied blocks per context -system.l2c.overall_accesses::0 2397771 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.176515 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.325488 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 11568.063937 # Average occupied blocks per context +system.l2c.occ_blocks::1 21331.159568 # Average occupied blocks per context +system.l2c.overall_accesses::0 2395532 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2397771 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52206.280446 # average overall miss latency +system.l2c.overall_accesses::total 2395532 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52206.057388 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40114.981715 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40113.108078 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1785564 # number of overall hits +system.l2c.overall_hits::0 1787144 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1785564 # number of overall hits -system.l2c.overall_miss_latency 31961050333 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.255323 # miss rate for overall accesses +system.l2c.overall_hits::total 1787144 # number of overall hits +system.l2c.overall_miss_latency 31761538842 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.253968 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 612207 # number of overall misses +system.l2c.overall_misses::0 608388 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 612207 # number of overall misses +system.l2c.overall_misses::total 608388 # number of overall misses system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24558632496 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.255323 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 24404293484 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.253967 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 612206 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1926664998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 608387 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1926105498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 396159 # number of replacements -system.l2c.sampled_refs 427780 # Sample count of references to valid blocks. +system.l2c.replacements 394069 # number of replacements +system.l2c.sampled_refs 426267 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30721.225374 # Cycle average of tags in use -system.l2c.total_refs 1967340 # Total number of references to valid blocks. -system.l2c.warmup_cycle 5645112000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119153 # number of writebacks +system.l2c.tagsinuse 32899.223505 # Cycle average of tags in use +system.l2c.total_refs 2000592 # Total number of references to valid blocks. +system.l2c.warmup_cycle 5644310000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 118209 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post |