diff options
Diffstat (limited to 'tests/long/10.linux-boot')
12 files changed, 2800 insertions, 2786 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index ce4b09a6a..f372f8ce3 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -130,6 +130,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu0.tracer trapLatency=13 @@ -565,6 +566,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu1.tracer trapLatency=13 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index e8efa0522..72ae91dc7 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 15 2011 20:24:21 -gem5 started Aug 15 2011 20:25:29 -gem5 executing on nadc-0270 +gem5 compiled Aug 17 2011 16:33:41 +gem5 started Aug 17 2011 16:35:58 +gem5 executing on nadc-0388 command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 98887000 -Exiting @ tick 1899411597500 because m5_exit instruction encountered +Exiting @ tick 1897470973500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 2eeafd392..d4f86dcbd 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,133 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.899412 # Number of seconds simulated -sim_ticks 1899411597500 # Number of ticks simulated +sim_seconds 1.897471 # Number of seconds simulated +sim_ticks 1897470973500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123946 # Simulator instruction rate (inst/s) -host_tick_rate 4137994790 # Simulator tick rate (ticks/s) -host_mem_usage 343492 # Number of bytes of host memory used -host_seconds 459.02 # Real time elapsed on the host -sim_insts 56893410 # Number of instructions simulated -system.l2c.replacements 397094 # number of replacements -system.l2c.tagsinuse 35529.229053 # Cycle average of tags in use -system.l2c.total_refs 2438232 # Total number of references to valid blocks. -system.l2c.sampled_refs 432488 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.637687 # Average number of references to valid blocks. +host_inst_rate 112670 # Simulator instruction rate (inst/s) +host_tick_rate 3808310962 # Simulator tick rate (ticks/s) +host_mem_usage 344004 # Number of bytes of host memory used +host_seconds 498.24 # Real time elapsed on the host +sim_insts 56137023 # Number of instructions simulated +system.l2c.replacements 397425 # number of replacements +system.l2c.tagsinuse 35089.523512 # Cycle average of tags in use +system.l2c.total_refs 2483901 # Total number of references to valid blocks. +system.l2c.sampled_refs 433413 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.731026 # Average number of references to valid blocks. system.l2c.warmup_cycle 9244135000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 10221.529700 # Average occupied blocks per context -system.l2c.occ_blocks::1 2327.457536 # Average occupied blocks per context -system.l2c.occ_blocks::2 22980.241816 # Average occupied blocks per context -system.l2c.occ_percent::0 0.155968 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.035514 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.350651 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1442413 # number of ReadReq hits -system.l2c.ReadReq_hits::1 407625 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1850038 # number of ReadReq hits -system.l2c.Writeback_hits::0 800001 # number of Writeback hits -system.l2c.Writeback_hits::total 800001 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 188 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 71 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 259 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 35 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 35 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 148509 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 19811 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168320 # number of ReadExReq hits -system.l2c.demand_hits::0 1590922 # number of demand (read+write) hits -system.l2c.demand_hits::1 427436 # number of demand (read+write) hits +system.l2c.occ_blocks::0 11999.654790 # Average occupied blocks per context +system.l2c.occ_blocks::1 233.124353 # Average occupied blocks per context +system.l2c.occ_blocks::2 22856.744369 # Average occupied blocks per context +system.l2c.occ_percent::0 0.183100 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.003557 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.348766 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1722706 # number of ReadReq hits +system.l2c.ReadReq_hits::1 146059 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1868765 # number of ReadReq hits +system.l2c.Writeback_hits::0 827102 # number of Writeback hits +system.l2c.Writeback_hits::total 827102 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 179 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 47 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 226 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 26 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 27 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 53 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 168351 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 11011 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 179362 # number of ReadExReq hits +system.l2c.demand_hits::0 1891057 # number of demand (read+write) hits +system.l2c.demand_hits::1 157070 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2018358 # number of demand (read+write) hits -system.l2c.overall_hits::0 1590922 # number of overall hits -system.l2c.overall_hits::1 427436 # number of overall hits +system.l2c.demand_hits::total 2048127 # number of demand (read+write) hits +system.l2c.overall_hits::0 1891057 # number of overall hits +system.l2c.overall_hits::1 157070 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2018358 # number of overall hits -system.l2c.ReadReq_misses::0 301840 # number of ReadReq misses -system.l2c.ReadReq_misses::1 7227 # number of ReadReq misses -system.l2c.ReadReq_misses::total 309067 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3348 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 792 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4140 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 439 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 492 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 931 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 106737 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 17826 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124563 # number of ReadExReq misses -system.l2c.demand_misses::0 408577 # number of demand (read+write) misses -system.l2c.demand_misses::1 25053 # number of demand (read+write) misses +system.l2c.overall_hits::total 2048127 # number of overall hits +system.l2c.ReadReq_misses::0 305325 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4048 # number of ReadReq misses +system.l2c.ReadReq_misses::total 309373 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 2451 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 556 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3007 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 48 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 82 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 130 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 113992 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 10735 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124727 # number of ReadExReq misses +system.l2c.demand_misses::0 419317 # number of demand (read+write) misses +system.l2c.demand_misses::1 14783 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 433630 # number of demand (read+write) misses -system.l2c.overall_misses::0 408577 # number of overall misses -system.l2c.overall_misses::1 25053 # number of overall misses +system.l2c.demand_misses::total 434100 # number of demand (read+write) misses +system.l2c.overall_misses::0 419317 # number of overall misses +system.l2c.overall_misses::1 14783 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 433630 # number of overall misses -system.l2c.ReadReq_miss_latency 16078822000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 5852000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 5401500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6533699500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22612521500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22612521500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1744253 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 414852 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2159105 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 800001 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 800001 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 3536 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 863 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4399 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 474 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 527 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1001 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 255246 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 37637 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292883 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1999499 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 452489 # number of demand (read+write) accesses +system.l2c.overall_misses::total 434100 # number of overall misses +system.l2c.ReadReq_miss_latency 16104881500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 3975000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 681000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6543645500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22648527000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22648527000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2028031 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 150107 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2178138 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 827102 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 827102 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 2630 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 603 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3233 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 74 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 109 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 183 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 282343 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 21746 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304089 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2310374 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 171853 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2451988 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1999499 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 452489 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2482227 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2310374 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 171853 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2451988 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.173048 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.017421 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.946833 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.917729 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.926160 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.933586 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.418173 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.473630 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.204340 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.055367 # miss rate for demand accesses +system.l2c.overall_accesses::total 2482227 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.150552 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.026967 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.931939 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.922056 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.648649 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.752294 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.403736 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.493654 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.181493 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.086021 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.204340 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.055367 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.181493 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.086021 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 53269.354625 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 2224826.622388 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52746.684680 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3978478.631423 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 1747.909200 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 7388.888889 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 1621.787026 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 7149.280576 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 12304.100228 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 10978.658537 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 14187.500000 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 8304.878049 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 61213.070444 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 366526.394031 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 57404.427504 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 609561.760596 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 55344.577644 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 902587.374765 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 54012.899549 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1532065.683555 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 55344.577644 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 902587.374765 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 54012.899549 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1532065.683555 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -138,70 +138,70 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 122463 # number of writebacks +system.l2c.writebacks 122219 # number of writebacks system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 309050 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 4140 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 931 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 124563 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 433613 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 433613 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 309356 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3007 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 130 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 124727 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 434083 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 434083 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12366985500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 165615000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 37241500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5018687000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17385672500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17385672500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 838004500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1515144998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 2353149498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.177182 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.744964 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12384389500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 120345500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 5200000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5026892500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17411282000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17411282000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 838237000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1420706998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 2258943998 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.152540 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.060903 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.170814 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 4.797219 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.143346 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4.986733 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.964135 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.766603 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.756757 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.192661 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.488012 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 3.309589 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.441757 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 5.735630 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.216861 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.958284 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.187884 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 2.525897 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.216861 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.958284 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.187884 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 2.525897 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40016.131694 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40003.623188 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40001.611171 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40290.351067 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40094.906057 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40094.906057 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40032.808480 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40021.782507 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40303.162106 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40110.490390 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40110.490390 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41701 # number of replacements -system.iocache.tagsinuse 0.379564 # Cycle average of tags in use +system.iocache.replacements 41699 # number of replacements +system.iocache.tagsinuse 0.463134 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41717 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708346603000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.379564 # Average occupied blocks per context -system.iocache.occ_percent::1 0.023723 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1709323096000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.463134 # Average occupied blocks per context +system.iocache.occ_percent::1 0.028946 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -218,10 +218,10 @@ system.iocache.demand_misses::total 41731 # nu system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 41731 # number of overall misses system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_miss_latency 20618998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5720800806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5741419804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5741419804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency 20616998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5721081806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5741698804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5741698804 # number of overall miss cycles system.iocache.ReadReq_accesses::1 179 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) @@ -241,26 +241,26 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115189.932961 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115178.759777 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137678.109501 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137684.872112 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137581.649230 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137588.334907 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137581.649230 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137588.334907 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64641068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64637068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6181.607344 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6180.633773 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 41522 # number of writebacks +system.iocache.writebacks 41520 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.ReadReq_mshr_misses 179 # number of ReadReq MSHR misses @@ -268,10 +268,10 @@ system.iocache.WriteReq_mshr_misses 41552 # nu system.iocache.demand_mshr_misses 41731 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses 41731 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 11310998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3559941996 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3571252994 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3571252994 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 11308998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3560223994 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571532992 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571532992 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -285,10 +285,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63189.932961 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85674.383808 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85577.939517 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85577.939517 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63178.759777 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85681.170437 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85584.649110 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85584.649110 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -309,22 +309,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8691348 # DTB read hits -system.cpu0.dtb.read_misses 30841 # DTB read misses -system.cpu0.dtb.read_acv 585 # DTB read access violations -system.cpu0.dtb.read_accesses 626526 # DTB read accesses -system.cpu0.dtb.write_hits 5727483 # DTB write hits -system.cpu0.dtb.write_misses 5665 # DTB write misses -system.cpu0.dtb.write_acv 282 # DTB write access violations -system.cpu0.dtb.write_accesses 212486 # DTB write accesses -system.cpu0.dtb.data_hits 14418831 # DTB hits -system.cpu0.dtb.data_misses 36506 # DTB misses -system.cpu0.dtb.data_acv 867 # DTB access violations -system.cpu0.dtb.data_accesses 839012 # DTB accesses -system.cpu0.itb.fetch_hits 1018007 # ITB hits -system.cpu0.itb.fetch_misses 28254 # ITB misses -system.cpu0.itb.fetch_acv 951 # ITB acv -system.cpu0.itb.fetch_accesses 1046261 # ITB accesses +system.cpu0.dtb.read_hits 9537119 # DTB read hits +system.cpu0.dtb.read_misses 35694 # DTB read misses +system.cpu0.dtb.read_acv 589 # DTB read access violations +system.cpu0.dtb.read_accesses 644456 # DTB read accesses +system.cpu0.dtb.write_hits 6201700 # DTB write hits +system.cpu0.dtb.write_misses 7404 # DTB write misses +system.cpu0.dtb.write_acv 340 # DTB write access violations +system.cpu0.dtb.write_accesses 219479 # DTB write accesses +system.cpu0.dtb.data_hits 15738819 # DTB hits +system.cpu0.dtb.data_misses 43098 # DTB misses +system.cpu0.dtb.data_acv 929 # DTB access violations +system.cpu0.dtb.data_accesses 863935 # DTB accesses +system.cpu0.itb.fetch_hits 1065001 # ITB hits +system.cpu0.itb.fetch_misses 28395 # ITB misses +system.cpu0.itb.fetch_acv 959 # ITB acv +system.cpu0.itb.fetch_accesses 1093396 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -337,275 +337,275 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 103036446 # number of cpu cycles simulated +system.cpu0.numCycles 112251413 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 12345310 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 10395868 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 412413 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 11143165 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5756291 # Number of BTB hits +system.cpu0.BPredUnit.lookups 13715156 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 11502951 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 484161 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 12377728 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 6363664 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 808447 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 32944 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 25643568 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63130050 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12345310 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6564738 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12229123 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1931790 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 31463202 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31044 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 192852 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 226876 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 96 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7797411 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 265802 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 71034720 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.888721 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.206546 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 918279 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 37972 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 28099564 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 69844028 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13715156 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 7281943 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 13538078 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2172072 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 34812736 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 29955 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 193219 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 330912 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 98 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8567969 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 303515 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 78411579 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.890736 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.207630 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 58805597 82.78% 82.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 896633 1.26% 84.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1683822 2.37% 86.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 790380 1.11% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2590451 3.65% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 578678 0.81% 91.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 651939 0.92% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 969955 1.37% 94.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4067265 5.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64873501 82.73% 82.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 956509 1.22% 83.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1906420 2.43% 86.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 900643 1.15% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2836490 3.62% 91.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 653196 0.83% 91.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 748865 0.96% 92.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1020020 1.30% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4515935 5.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 71034720 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.119815 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.612696 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26620678 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 31169441 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11195503 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 833782 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1215315 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 497181 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 32875 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 61799188 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 97991 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1215315 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27633845 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 10392034 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17602675 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10482679 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3708170 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58338786 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6838 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 387997 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1347242 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39031988 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 70900966 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 70475489 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 425477 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33170605 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5861375 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1485068 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 227968 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10243220 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9180149 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6097470 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1603652 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1903642 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 51204618 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1864754 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 49739725 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 70469 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6805118 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3728302 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1267762 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 71034720 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.700217 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.322322 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 78411579 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.122182 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.622211 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 29218734 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34518564 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 12397503 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 907653 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1369124 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 565623 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 38130 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 68326357 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 115471 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1369124 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 30359966 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12420002 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18653448 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 11559609 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4049428 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 64489639 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6675 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 459269 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1452522 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 43185187 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 78281955 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 77849999 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 431956 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36504578 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 6680601 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1578071 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 238750 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11394232 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10044360 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6546770 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1193752 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 777018 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 56531127 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2009866 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 55005856 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 111558 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7605242 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3895552 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1371310 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 78411579 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.701502 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.348295 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 48628565 68.46% 68.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10107628 14.23% 82.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4889823 6.88% 89.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3044033 4.29% 93.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2225901 3.13% 96.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1246231 1.75% 98.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 700109 0.99% 99.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 154501 0.22% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 37929 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54224531 69.15% 69.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10651966 13.58% 82.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 5211873 6.65% 89.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3322855 4.24% 93.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2518388 3.21% 96.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1465679 1.87% 98.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 653633 0.83% 99.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 263398 0.34% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 99256 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 71034720 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 78411579 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 52156 10.93% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 267781 56.13% 67.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 157153 32.94% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 63058 8.97% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 343865 48.92% 57.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 295935 42.10% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3328 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 33971995 68.30% 68.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 53580 0.11% 68.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15560 0.03% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9077168 18.25% 86.70% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5791424 11.64% 98.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 825016 1.66% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37799296 68.72% 68.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60344 0.11% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15686 0.03% 68.86% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.86% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.86% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.86% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9967542 18.12% 86.99% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6280275 11.42% 98.40% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 877731 1.60% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 49739725 # Type of FU issued -system.cpu0.iq.rate 0.482739 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 477090 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.009592 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 170451707 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59601257 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 48417922 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 610021 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 293075 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 290010 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 49893944 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 319543 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 495668 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 55005856 # Type of FU issued +system.cpu0.iq.rate 0.490024 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 702858 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012778 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 188615716 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65871549 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53572345 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 621990 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 297473 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 294666 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 55378554 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 326832 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 547956 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1332465 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 15476 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 20341 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 527918 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1439562 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 14656 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 23453 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 541104 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 14091 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 218656 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18437 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 167543 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1215315 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6999311 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 544202 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 56199276 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 754553 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9180149 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6097470 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1645846 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 470730 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6896 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 20341 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 291584 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 326384 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 617968 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 49204821 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8748371 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 534903 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1369124 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8683441 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 605421 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 62052001 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 831027 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10044360 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6546770 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1774362 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 483184 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 10442 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 23453 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 350905 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 357470 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 708375 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 54360123 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9599991 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 645732 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3129904 # number of nop insts executed -system.cpu0.iew.exec_refs 14495988 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7765506 # Number of branches executed -system.cpu0.iew.exec_stores 5747617 # Number of stores executed -system.cpu0.iew.exec_rate 0.477548 # Inst execution rate -system.cpu0.iew.wb_sent 48811342 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 48707932 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23956930 # num instructions producing a value -system.cpu0.iew.wb_consumers 32092147 # num instructions consuming a value +system.cpu0.iew.exec_nop 3511008 # number of nop insts executed +system.cpu0.iew.exec_refs 15823517 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8665836 # Number of branches executed +system.cpu0.iew.exec_stores 6223526 # Number of stores executed +system.cpu0.iew.exec_rate 0.484271 # Inst execution rate +system.cpu0.iew.wb_sent 53987864 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 53867011 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26614200 # num instructions producing a value +system.cpu0.iew.wb_consumers 35806994 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.472725 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.746504 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.479878 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.743268 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 48759720 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 7342909 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 596992 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 565842 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 69819405 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.698369 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.595257 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 53695815 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 8260876 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638556 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 645745 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 77042455 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.696964 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.608185 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 51124042 73.22% 73.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8032267 11.50% 84.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4140271 5.93% 90.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2329968 3.34% 93.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1273302 1.82% 95.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 518646 0.74% 96.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 361032 0.52% 97.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 714639 1.02% 98.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1325238 1.90% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 56792844 73.72% 73.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8505609 11.04% 84.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4528626 5.88% 90.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2490278 3.23% 93.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1477167 1.92% 95.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 617055 0.80% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 444256 0.58% 97.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 490319 0.64% 97.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1696301 2.20% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 69819405 # Number of insts commited each cycle -system.cpu0.commit.count 48759720 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 77042455 # Number of insts commited each cycle +system.cpu0.commit.count 53695815 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13417236 # Number of memory references committed -system.cpu0.commit.loads 7847684 # Number of loads committed -system.cpu0.commit.membars 202015 # Number of memory barriers committed -system.cpu0.commit.branches 7296729 # Number of branches committed -system.cpu0.commit.fp_insts 287598 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45136958 # Number of committed integer instructions. -system.cpu0.commit.function_calls 626830 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1325238 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14610464 # Number of memory references committed +system.cpu0.commit.loads 8604798 # Number of loads committed +system.cpu0.commit.membars 217772 # Number of memory barriers committed +system.cpu0.commit.branches 8097271 # Number of branches committed +system.cpu0.commit.fp_insts 292136 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 49674100 # Number of committed integer instructions. +system.cpu0.commit.function_calls 705369 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1696301 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124403287 # The number of ROB reads -system.cpu0.rob.rob_writes 113421475 # The number of ROB writes -system.cpu0.timesIdled 1076474 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 32001726 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 45967748 # Number of Instructions Simulated -system.cpu0.committedInsts_total 45967748 # Number of Instructions Simulated -system.cpu0.cpi 2.241494 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.241494 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.446131 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.446131 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 64511715 # number of integer regfile reads -system.cpu0.int_regfile_writes 35217125 # number of integer regfile writes -system.cpu0.fp_regfile_reads 141815 # number of floating regfile reads -system.cpu0.fp_regfile_writes 144143 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1768684 # number of misc regfile reads -system.cpu0.misc_regfile_writes 843519 # number of misc regfile writes +system.cpu0.rob.rob_reads 137112360 # The number of ROB reads +system.cpu0.rob.rob_writes 125284104 # The number of ROB writes +system.cpu0.timesIdled 1232970 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 33839834 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 50579161 # Number of Instructions Simulated +system.cpu0.committedInsts_total 50579161 # Number of Instructions Simulated +system.cpu0.cpi 2.219321 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.219321 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.450588 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.450588 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 71273377 # number of integer regfile reads +system.cpu0.int_regfile_writes 38974201 # number of integer regfile writes +system.cpu0.fp_regfile_reads 144005 # number of floating regfile reads +system.cpu0.fp_regfile_writes 146400 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1864820 # number of misc regfile reads +system.cpu0.misc_regfile_writes 888952 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -637,233 +637,233 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 880531 # number of replacements -system.cpu0.icache.tagsinuse 509.999835 # Cycle average of tags in use -system.cpu0.icache.total_refs 6871052 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 881041 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.798788 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23352841000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 509.999835 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.996093 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 6871052 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6871052 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 6871052 # number of demand (read+write) hits +system.cpu0.icache.replacements 972255 # number of replacements +system.cpu0.icache.tagsinuse 509.997473 # Cycle average of tags in use +system.cpu0.icache.total_refs 7540990 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 972767 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.752103 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23351428000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 509.997473 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.996089 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::0 7540990 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7540990 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 7540990 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6871052 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 6871052 # number of overall hits +system.cpu0.icache.demand_hits::total 7540990 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 7540990 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 6871052 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 926359 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 926359 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 926359 # number of demand (read+write) misses +system.cpu0.icache.overall_hits::total 7540990 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 1026979 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1026979 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 1026979 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 926359 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 926359 # number of overall misses +system.cpu0.icache.demand_misses::total 1026979 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 1026979 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 926359 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 13849490998 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 13849490998 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 13849490998 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 7797411 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7797411 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 7797411 # number of demand (read+write) accesses +system.cpu0.icache.overall_misses::total 1026979 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 15345865496 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 15345865496 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 15345865496 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 8567969 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8567969 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 8567969 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7797411 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 7797411 # number of overall (read+write) accesses +system.cpu0.icache.demand_accesses::total 8567969 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 8567969 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7797411 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.118803 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.118803 # miss rate for demand accesses +system.cpu0.icache.overall_accesses::total 8567969 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.119863 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.119863 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.118803 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::0 0.119863 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14950.457650 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::0 14942.725699 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14950.457650 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::0 14942.725699 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14950.457650 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 14942.725699 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1091498 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 1169997 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 105 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 101 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 10395.219048 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11584.128713 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 208 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 45158 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 45158 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 45158 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 881201 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 881201 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 881201 # number of overall MSHR misses +system.cpu0.icache.writebacks 201 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 54044 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 54044 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 54044 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 972935 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 972935 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 972935 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 10516036498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 10516036498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 10516036498 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 11633224497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 11633224497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 11633224497 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.113012 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.113555 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.113012 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.113555 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.113012 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.113555 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11933.754612 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11933.754612 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11933.754612 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11956.836271 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11956.836271 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11956.836271 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1121199 # number of replacements -system.cpu0.dcache.tagsinuse 488.854716 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10572300 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1121711 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.425155 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1341445 # number of replacements +system.cpu0.dcache.tagsinuse 503.508011 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11371142 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1341956 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.473558 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 489.854716 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 504.508011 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.956747 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::0 0.985367 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 6494021 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6494021 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 3693282 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3693282 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 174657 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174657 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 196468 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 196468 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 10187303 # number of demand (read+write) hits +system.cpu0.dcache.ReadReq_hits::0 7002154 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7002154 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::0 3971242 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3971242 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 182799 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 182799 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::0 208802 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 208802 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::0 10973396 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10187303 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 10187303 # number of overall hits +system.cpu0.dcache.demand_hits::total 10973396 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::0 10973396 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 10187303 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 1375687 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1375687 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 1662707 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1662707 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 20152 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20152 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 3348 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3348 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 3038394 # number of demand (read+write) misses +system.cpu0.dcache.overall_hits::total 10973396 # number of overall hits +system.cpu0.dcache.ReadReq_misses::0 1698188 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1698188 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::0 1810110 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1810110 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::0 21696 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21696 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::0 665 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 665 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::0 3508298 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3038394 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 3038394 # number of overall misses +system.cpu0.dcache.demand_misses::total 3508298 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::0 3508298 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 3038394 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 31827617500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 51165322075 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 294994000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 41962000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 82992939575 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 82992939575 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 7869708 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7869708 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 5355989 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5355989 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 194809 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 194809 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 199816 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199816 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 13225697 # number of demand (read+write) accesses +system.cpu0.dcache.overall_misses::total 3508298 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 37024597500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 55205693695 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency 326548500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 6352500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency 92230291195 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 92230291195 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 8700342 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8700342 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 5781352 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5781352 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 204495 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 204495 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 209467 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 209467 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 14481694 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13225697 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 13225697 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14481694 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 14481694 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13225697 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.174808 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.310439 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.103445 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.016755 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.229734 # miss rate for demand accesses +system.cpu0.dcache.overall_accesses::total 14481694 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.195186 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.313095 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106096 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003175 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.242257 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.229734 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.242257 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 23135.798695 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 21802.413808 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 30772.302080 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 30498.529755 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14638.447797 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15051.092367 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 12533.452808 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9552.631579 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 27314.739160 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 26289.183871 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 27314.739160 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 26289.183871 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 855518470 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 221500 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 97807 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8747.006554 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 22150 # average number of cycles each access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 889959290 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 98831 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9004.859710 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 602926 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 516336 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1401114 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 4413 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 1917450 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 1917450 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 859351 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 261593 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 15739 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 3348 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 1120944 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 1120944 # number of overall MSHR misses +system.cpu0.dcache.writebacks 791115 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 651520 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1525368 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 4914 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 2176888 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 2176888 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 1046668 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 284742 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 16782 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 665 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 1331410 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 1331410 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 21884756500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 7717990970 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 167906500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 31911000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 29602747470 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 29602747470 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 634931500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1090823998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 1725755498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.109197 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 24224955000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 8301968289 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 194959000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 4349000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 32526923289 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 32526923289 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 917419500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1254211998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 2171631498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.120302 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.048841 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049252 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.080792 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.082066 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.016755 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.003175 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.084755 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.091937 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.084755 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.091937 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 25466.609686 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29503.813061 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10668.180952 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 9531.362007 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 26408.765710 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 26408.765710 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23144.831981 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29156.107244 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11617.149327 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6539.849624 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 24430.433367 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 24430.433367 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -874,22 +874,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2335038 # DTB read hits -system.cpu1.dtb.read_misses 11141 # DTB read misses -system.cpu1.dtb.read_acv 15 # DTB read access violations -system.cpu1.dtb.read_accesses 329726 # DTB read accesses -system.cpu1.dtb.write_hits 1301059 # DTB write hits -system.cpu1.dtb.write_misses 3075 # DTB write misses -system.cpu1.dtb.write_acv 63 # DTB write access violations -system.cpu1.dtb.write_accesses 125932 # DTB write accesses -system.cpu1.dtb.data_hits 3636097 # DTB hits -system.cpu1.dtb.data_misses 14216 # DTB misses -system.cpu1.dtb.data_acv 78 # DTB access violations -system.cpu1.dtb.data_accesses 455658 # DTB accesses -system.cpu1.itb.fetch_hits 423788 # ITB hits -system.cpu1.itb.fetch_misses 7837 # ITB misses -system.cpu1.itb.fetch_acv 166 # ITB acv -system.cpu1.itb.fetch_accesses 431625 # ITB accesses +system.cpu1.dtb.read_hits 1324275 # DTB read hits +system.cpu1.dtb.read_misses 10298 # DTB read misses +system.cpu1.dtb.read_acv 4 # DTB read access violations +system.cpu1.dtb.read_accesses 333543 # DTB read accesses +system.cpu1.dtb.write_hits 770562 # DTB write hits +system.cpu1.dtb.write_misses 3363 # DTB write misses +system.cpu1.dtb.write_acv 49 # DTB write access violations +system.cpu1.dtb.write_accesses 128416 # DTB write accesses +system.cpu1.dtb.data_hits 2094837 # DTB hits +system.cpu1.dtb.data_misses 13661 # DTB misses +system.cpu1.dtb.data_acv 53 # DTB access violations +system.cpu1.dtb.data_accesses 461959 # DTB accesses +system.cpu1.itb.fetch_hits 370005 # ITB hits +system.cpu1.itb.fetch_misses 7545 # ITB misses +system.cpu1.itb.fetch_acv 134 # ITB acv +system.cpu1.itb.fetch_accesses 377550 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -902,500 +902,500 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 20152954 # number of cpu cycles simulated +system.cpu1.numCycles 9912659 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 3242658 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 2662310 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 131441 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 2892914 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 1375784 # Number of BTB hits +system.cpu1.BPredUnit.lookups 1745252 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 1443345 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 65834 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 1584413 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 702878 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 235158 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 7774 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 6188689 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 16200802 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3242658 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1610942 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 3090469 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 613653 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 7714239 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 27241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65046 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 159598 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1940544 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 74817 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 17655267 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.917619 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.257026 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 119333 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 5152 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 3326193 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 8368967 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1745252 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 822211 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1597560 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 342353 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 3930227 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65364 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 47873 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1048710 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 37506 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 9217508 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.907942 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.250031 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 14564798 82.50% 82.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 197815 1.12% 83.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 462974 2.62% 86.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 255072 1.44% 87.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 513820 2.91% 90.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 162072 0.92% 91.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 211046 1.20% 92.71% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 121453 0.69% 93.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1166217 6.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 7619948 82.67% 82.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 115536 1.25% 83.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 231432 2.51% 86.43% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 132066 1.43% 87.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 251396 2.73% 90.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 87805 0.95% 91.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 105965 1.15% 92.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 72910 0.79% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 600450 6.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 17655267 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.160902 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.803892 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 6415483 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 7821687 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2861971 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 154408 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 401717 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 149324 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 8351 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 15726471 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21041 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 401717 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 6681295 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2118018 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 4943945 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2656010 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 854280 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 14736815 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 186 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 221815 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 138242 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 9911157 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 18088761 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 17988130 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 100631 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7897558 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2013599 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 424269 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 36275 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2592161 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2485755 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1426985 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 360752 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 285996 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 12852454 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 484885 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 12271073 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 26221 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2300844 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1315458 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 356394 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 17655267 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.695038 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.354056 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 9217508 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.176063 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.844271 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3400940 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 4036286 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1484850 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 73785 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 221646 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 74292 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4556 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 8102747 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 13778 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 221646 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3537754 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 421646 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3194279 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1408453 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 433728 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 7527296 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 85 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 45933 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 92379 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 5035349 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 9221754 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 9169185 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52569 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 3992895 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1042454 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 304748 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 22314 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1288706 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1415531 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 837109 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 144169 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 91214 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 6583258 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 323533 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 6259296 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 22632 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1284449 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 724409 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 248666 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 9217508 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.679066 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.329101 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 12407145 70.27% 70.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2235941 12.66% 82.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1035355 5.86% 88.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 796484 4.51% 93.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 626149 3.55% 96.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 333560 1.89% 98.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 156466 0.89% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 49558 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 14609 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 6458729 70.07% 70.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1222372 13.26% 83.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 577704 6.27% 89.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 392327 4.26% 93.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 292985 3.18% 97.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 159359 1.73% 98.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 73107 0.79% 99.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 30242 0.33% 99.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10683 0.12% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 17655267 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 9217508 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 13105 7.34% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 95150 53.29% 60.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 70292 39.37% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2814 1.95% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 81545 56.44% 58.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 60126 41.61% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3979 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 8216703 66.96% 66.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 19600 0.16% 67.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11030 0.09% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1988 0.02% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2431476 19.81% 87.07% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1328460 10.83% 97.90% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 257837 2.10% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3976 0.06% 0.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3873185 61.88% 61.94% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10062 0.16% 62.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10067 0.16% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1379075 22.03% 84.33% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 790293 12.63% 96.95% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 190650 3.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 12271073 # Type of FU issued -system.cpu1.iq.rate 0.608897 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 178547 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014550 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 42255695 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 15570864 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 11866318 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 146486 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 71642 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 70264 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 12369614 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 76027 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 105474 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 6259296 # Type of FU issued +system.cpu1.iq.rate 0.631445 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 144485 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.023083 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 21824812 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 8155075 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 6057514 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 78405 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 38858 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 37639 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 6359227 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 40578 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 60856 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 463598 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 9284 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4789 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 195743 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 266775 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6711 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3171 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 114531 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 5212 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 50812 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 348 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 21986 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 401717 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1622444 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 62821 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 14027082 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 177744 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2485755 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1426985 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 441055 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 11459 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3097 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4789 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 106850 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 88794 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 195644 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 12103351 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2352431 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 167722 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 221646 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 305727 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 11882 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 7168806 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98535 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1415531 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 837109 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 301857 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4025 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4971 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3171 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 47886 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 59778 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 107664 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 6180810 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1338159 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 78486 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 689743 # number of nop insts executed -system.cpu1.iew.exec_refs 3661778 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1907962 # Number of branches executed -system.cpu1.iew.exec_stores 1309347 # Number of stores executed -system.cpu1.iew.exec_rate 0.600575 # Inst execution rate -system.cpu1.iew.wb_sent 11974198 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 11936582 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5946561 # num instructions producing a value -system.cpu1.iew.wb_consumers 8293064 # num instructions consuming a value +system.cpu1.iew.exec_nop 262015 # number of nop insts executed +system.cpu1.iew.exec_refs 2115427 # number of memory reference insts executed +system.cpu1.iew.exec_branches 905329 # Number of branches executed +system.cpu1.iew.exec_stores 777268 # Number of stores executed +system.cpu1.iew.exec_rate 0.623527 # Inst execution rate +system.cpu1.iew.wb_sent 6122723 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 6095153 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2947422 # num instructions producing a value +system.cpu1.iew.wb_consumers 4027218 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.592299 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.717052 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.614886 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.731875 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 11515527 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 2436187 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 128491 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 177413 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 17253550 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.667429 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.563448 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 5779093 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1316908 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 74867 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 99712 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 8995862 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.642417 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.546372 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 12827961 74.35% 74.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1952306 11.32% 85.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 928648 5.38% 91.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 493505 2.86% 93.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 338427 1.96% 95.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 153865 0.89% 96.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 124614 0.72% 97.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 119099 0.69% 98.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 315125 1.83% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 6736606 74.89% 74.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1094915 12.17% 87.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 391523 4.35% 91.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 242834 2.70% 94.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 155077 1.72% 95.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 75617 0.84% 96.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 76298 0.85% 97.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 67487 0.75% 98.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 155505 1.73% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 17253550 # Number of insts commited each cycle -system.cpu1.commit.count 11515527 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 8995862 # Number of insts commited each cycle +system.cpu1.commit.count 5779093 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3253399 # Number of memory references committed -system.cpu1.commit.loads 2022157 # Number of loads committed -system.cpu1.commit.membars 41280 # Number of memory barriers committed -system.cpu1.commit.branches 1729331 # Number of branches committed -system.cpu1.commit.fp_insts 68665 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 10682634 # Number of committed integer instructions. -system.cpu1.commit.function_calls 174972 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 315125 # number cycles where commit BW limit reached +system.cpu1.commit.refs 1871334 # Number of memory references committed +system.cpu1.commit.loads 1148756 # Number of loads committed +system.cpu1.commit.membars 20308 # Number of memory barriers committed +system.cpu1.commit.branches 819762 # Number of branches committed +system.cpu1.commit.fp_insts 36255 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 5407958 # Number of committed integer instructions. +system.cpu1.commit.function_calls 88494 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 155505 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 30796624 # The number of ROB reads -system.cpu1.rob.rob_writes 28304513 # The number of ROB writes -system.cpu1.timesIdled 230784 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2497687 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 10925662 # Number of Instructions Simulated -system.cpu1.committedInsts_total 10925662 # Number of Instructions Simulated -system.cpu1.cpi 1.844552 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.844552 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.542137 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.542137 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 15857410 # number of integer regfile reads -system.cpu1.int_regfile_writes 8648406 # number of integer regfile writes -system.cpu1.fp_regfile_reads 40377 # number of floating regfile reads -system.cpu1.fp_regfile_writes 39511 # number of floating regfile writes -system.cpu1.misc_regfile_reads 441161 # number of misc regfile reads -system.cpu1.misc_regfile_writes 195544 # number of misc regfile writes -system.cpu1.icache.replacements 205961 # number of replacements -system.cpu1.icache.tagsinuse 502.866762 # Cycle average of tags in use -system.cpu1.icache.total_refs 1723284 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 206473 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.346292 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1708291874000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 502.866762 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.982162 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 1723284 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1723284 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 1723284 # number of demand (read+write) hits +system.cpu1.rob.rob_reads 15845699 # The number of ROB reads +system.cpu1.rob.rob_writes 14412433 # The number of ROB writes +system.cpu1.timesIdled 81222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 695151 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 5557862 # Number of Instructions Simulated +system.cpu1.committedInsts_total 5557862 # Number of Instructions Simulated +system.cpu1.cpi 1.783538 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.783538 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.560683 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.560683 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 8056762 # number of integer regfile reads +system.cpu1.int_regfile_writes 4390923 # number of integer regfile writes +system.cpu1.fp_regfile_reads 24497 # number of floating regfile reads +system.cpu1.fp_regfile_writes 23023 # number of floating regfile writes +system.cpu1.misc_regfile_reads 283037 # number of misc regfile reads +system.cpu1.misc_regfile_writes 133939 # number of misc regfile writes +system.cpu1.icache.replacements 109497 # number of replacements +system.cpu1.icache.tagsinuse 452.896457 # Cycle average of tags in use +system.cpu1.icache.total_refs 933398 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 110009 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.484742 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1874842259000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 452.896457 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.884563 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::0 933398 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 933398 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 933398 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1723284 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 1723284 # number of overall hits +system.cpu1.icache.demand_hits::total 933398 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 933398 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 1723284 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 217260 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 217260 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 217260 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 933398 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 115312 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 115312 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 115312 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 217260 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 217260 # number of overall misses +system.cpu1.icache.demand_misses::total 115312 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 115312 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 217260 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 3300371999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 3300371999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 3300371999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 1940544 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1940544 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 1940544 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 115312 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 1734763499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 1734763499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 1734763499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 1048710 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1048710 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 1048710 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1940544 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 1940544 # number of overall (read+write) accesses +system.cpu1.icache.demand_accesses::total 1048710 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 1048710 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1940544 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.111958 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.111958 # miss rate for demand accesses +system.cpu1.icache.overall_accesses::total 1048710 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.109956 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.109956 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.111958 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.109956 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 15190.886491 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 15044.084735 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 15190.886491 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 15044.084735 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 15190.886491 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 15044.084735 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 349000 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 115999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 33 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 10575.757576 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6444.388889 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 52 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 10723 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 10723 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 10723 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 206537 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 206537 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 206537 # number of overall MSHR misses +system.cpu1.icache.writebacks 32 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 5233 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 5233 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 5233 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 110079 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 110079 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 110079 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 2520725000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 2520725000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 2520725000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 1320813499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 1320813499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 1320813499 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.106433 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.104966 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.106433 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.104966 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.106433 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.104966 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12204.713925 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 12204.713925 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 12204.713925 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11998.778141 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11998.778141 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11998.778141 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 248685 # number of replacements -system.cpu1.dcache.tagsinuse 476.656972 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2836087 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 248990 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 11.390365 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 39851697000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 476.656972 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.930971 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 1838875 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1838875 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 950135 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 950135 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 25812 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 25812 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 24969 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 24969 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 2789010 # number of demand (read+write) hits +system.cpu1.dcache.replacements 62178 # number of replacements +system.cpu1.dcache.tagsinuse 392.683341 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1692677 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62506 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 27.080232 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1874637412500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::0 392.683341 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.766960 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::0 1125457 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1125457 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::0 544800 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 544800 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 16569 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 16569 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::0 14697 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 14697 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::0 1670257 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2789010 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 2789010 # number of overall hits +system.cpu1.dcache.demand_hits::total 1670257 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 1670257 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 2789010 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 315850 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 315850 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 245510 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 245510 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 5339 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5339 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 3179 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3179 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 561360 # number of demand (read+write) misses +system.cpu1.dcache.overall_hits::total 1670257 # number of overall hits +system.cpu1.dcache.ReadReq_misses::0 106593 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 106593 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::0 157299 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 157299 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::0 1471 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1471 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::0 688 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 688 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::0 263892 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 561360 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 561360 # number of overall misses +system.cpu1.dcache.demand_misses::total 263892 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::0 263892 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 561360 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 4714821500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 8024030885 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 65075500 # 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number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 3350370 # number of demand (read+write) accesses +system.cpu1.dcache.overall_misses::total 263892 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 1779114500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 5160494262 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 19390000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 8230500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 6939608762 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 6939608762 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 1232050 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1232050 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 702099 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 702099 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 18040 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 18040 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 15385 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 15385 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 1934149 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3350370 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 3350370 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1934149 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 1934149 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3350370 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.146585 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.205337 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.171391 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.112939 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.167552 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 1934149 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.086517 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.224041 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.081541 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044719 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.136438 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.167552 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.136438 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 14927.406997 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 16690.725470 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 32683.112236 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 32806.910800 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 12188.705750 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13181.509177 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13509.908776 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 11962.936047 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 22692.839506 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 26297.154753 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 22692.839506 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 26297.154753 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 135872392 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 106000 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 10757 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12631.067398 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 26500 # average number of cycles each access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 86924497 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6880 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12634.374564 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 196815 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 98942 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 203211 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 1094 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 302153 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 302153 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 216908 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 42299 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 4245 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 3179 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 259207 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 259207 # number of overall MSHR misses +system.cpu1.dcache.writebacks 35754 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 63001 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 133631 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 299 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 196632 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 196632 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 43592 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 23668 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 1172 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 688 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 67260 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 67260 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2649753500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 1268849871 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 33277000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 33400500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 3918603371 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 3918603371 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 300850000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 586892500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 887742500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.100666 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 554109500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 750522486 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11597500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 6158000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 1304631986 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 1304631986 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 18620500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 319072500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 337693000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035382 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.035378 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.033710 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.136272 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.064967 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.112939 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.044719 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.077367 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.034775 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.077367 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.034775 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12216.024766 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29997.160004 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7839.104829 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10506.605851 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 15117.660291 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 15117.660291 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12711.265829 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31710.431215 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9895.477816 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 8950.581395 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 19396.847844 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 19396.847844 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1403,31 +1403,31 @@ system.cpu1.dcache.mshr_cap_events 0 # nu system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5037 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 186073 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65315 40.13% 40.13% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 237 0.15% 40.27% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1923 1.18% 41.46% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 222 0.14% 41.59% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 95069 58.41% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 162766 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 63957 49.17% 49.17% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 237 0.18% 49.35% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1923 1.48% 50.83% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 222 0.17% 51.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63735 49.00% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 130074 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863353937000 98.10% 98.10% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 90928000 0.00% 98.11% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 390512500 0.02% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 85006500 0.00% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 35490372000 1.87% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1899410756000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.979208 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6377 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 199477 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 71613 40.63% 40.63% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.13% 40.76% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1921 1.09% 41.85% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 8 0.00% 41.86% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 102492 58.14% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 176271 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 70248 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 237 0.17% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1921 1.35% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 8 0.01% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 70240 49.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 142654 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1858831999000 97.96% 97.96% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 90898500 0.00% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 391654500 0.02% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 4204500 0.00% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 38151374000 2.01% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1897470130500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980939 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.670408 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.685322 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.72% 3.72% # number of syscalls executed system.cpu0.kern.syscall::3 18 8.37% 12.09% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.40% 13.49% # number of syscalls executed @@ -1459,59 +1459,59 @@ system.cpu0.kern.syscall::144 2 0.93% 99.07% # nu system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 215 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 307 0.18% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3778 2.20% 2.39% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.42% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 155399 90.68% 93.10% # number of callpals executed -system.cpu0.kern.callpal::rdps 6322 3.69% 96.79% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.79% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 96.79% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.80% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.80% # number of callpals executed -system.cpu0.kern.callpal::rti 4984 2.91% 99.71% # number of callpals executed -system.cpu0.kern.callpal::callsys 369 0.22% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 135 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 171369 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7417 # number of protection mode switches +system.cpu0.kern.callpal::wripir 104 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3842 2.08% 2.14% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.16% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpipl 169337 91.54% 93.71% # number of callpals executed +system.cpu0.kern.callpal::rdps 6360 3.44% 97.14% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.14% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 97.14% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.15% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.15% # number of callpals executed +system.cpu0.kern.callpal::rti 4767 2.58% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 135 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 184989 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7265 # number of protection mode switches system.cpu0.kern.mode_switch::user 1246 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1245 system.cpu0.kern.mode_good::user 1246 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.167858 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.171370 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1897486158000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1924590000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1895606727500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1863395000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3779 # number of times the context was actually changed +system.cpu0.kern.swap_context 3843 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 4032 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 54228 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 17280 37.82% 37.82% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1921 4.20% 42.02% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 307 0.67% 42.69% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 26187 57.31% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 45695 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 17261 47.36% 47.36% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1921 5.27% 52.64% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 307 0.84% 53.48% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16954 46.52% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 36443 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1869444423500 98.44% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 345691000 0.02% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 121909500 0.01% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29169069500 1.54% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1899081093500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998900 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2270 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 38355 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10172 33.29% 33.29% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1920 6.28% 39.57% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 104 0.34% 39.91% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18361 60.09% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30557 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10160 45.68% 45.68% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1920 8.63% 54.32% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 104 0.47% 54.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10056 45.22% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22240 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1871109076500 98.61% 98.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 343280000 0.02% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 41782500 0.00% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 25970941500 1.37% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1897465080500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998820 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.647420 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.547683 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 12 10.81% 10.81% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.90% 11.71% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.01% 20.72% # number of syscalls executed @@ -1528,35 +1528,35 @@ system.cpu1.kern.syscall::74 10 9.01% 97.30% # nu system.cpu1.kern.syscall::132 3 2.70% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 111 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 222 0.47% 0.47% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.47% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.48% # number of callpals executed -system.cpu1.kern.callpal::swpctx 871 1.85% 2.32% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.33% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.34% # number of callpals executed -system.cpu1.kern.callpal::swpipl 40736 86.30% 88.64% # number of callpals executed -system.cpu1.kern.callpal::rdps 2431 5.15% 93.79% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.79% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 93.80% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.81% # number of callpals executed -system.cpu1.kern.callpal::rti 2730 5.78% 99.59% # number of callpals executed -system.cpu1.kern.callpal::callsys 146 0.31% 99.90% # number of callpals executed -system.cpu1.kern.callpal::imb 45 0.10% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 8 0.03% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 391 1.24% 1.27% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.28% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.31% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26005 82.46% 83.77% # number of callpals executed +system.cpu1.kern.callpal::rdps 2390 7.58% 91.35% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.35% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.02% 91.37% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.38% # number of callpals executed +system.cpu1.kern.callpal::rti 2527 8.01% 99.39% # number of callpals executed +system.cpu1.kern.callpal::callsys 146 0.46% 99.85% # number of callpals executed +system.cpu1.kern.callpal::imb 45 0.14% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 47204 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1142 # number of protection mode switches +system.cpu1.kern.callpal::total 31535 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 869 # number of protection mode switches system.cpu1.kern.mode_switch::user 492 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2462 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 761 +system.cpu1.kern.mode_switch::idle 2051 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 521 system.cpu1.kern.mode_good::user 492 -system.cpu1.kern.mode_good::idle 269 -system.cpu1.kern.mode_switch_good::kernel 0.666375 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 29 +system.cpu1.kern.mode_switch_good::kernel 0.599540 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.109261 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.775636 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 35491661500 1.87% 1.87% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 858235500 0.05% 1.91% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862377378000 98.09% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 872 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.014139 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.613679 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2030212000 0.11% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 852485500 0.04% 0.15% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893908030500 99.85% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 392 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 4bc0cb36c..a8911f6cc 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -130,6 +130,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index a2519d6a4..b71599069 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 15 2011 20:24:21 -gem5 started Aug 15 2011 20:25:48 -gem5 executing on nadc-0270 +gem5 compiled Aug 17 2011 16:33:41 +gem5 started Aug 17 2011 16:35:09 +gem5 executing on nadc-0388 command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1858708914500 because m5_exit instruction encountered +Exiting @ tick 1857897393500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index eab7f5386..c17b9a135 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.858709 # Number of seconds simulated -sim_ticks 1858708914500 # Number of ticks simulated +sim_seconds 1.857897 # Number of seconds simulated +sim_ticks 1857897393500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124964 # Simulator instruction rate (inst/s) -host_tick_rate 4374927606 # Simulator tick rate (ticks/s) -host_mem_usage 340632 # Number of bytes of host memory used -host_seconds 424.85 # Real time elapsed on the host -sim_insts 53091761 # Number of instructions simulated -system.l2c.replacements 391302 # number of replacements -system.l2c.tagsinuse 34944.632545 # Cycle average of tags in use -system.l2c.total_refs 2405534 # Total number of references to valid blocks. -system.l2c.sampled_refs 424233 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.670313 # Average number of references to valid blocks. +host_inst_rate 111366 # Simulator instruction rate (inst/s) +host_tick_rate 3896929552 # Simulator tick rate (ticks/s) +host_mem_usage 340840 # Number of bytes of host memory used +host_seconds 476.76 # Real time elapsed on the host +sim_insts 53094627 # Number of instructions simulated +system.l2c.replacements 391325 # number of replacements +system.l2c.tagsinuse 34942.141711 # Cycle average of tags in use +system.l2c.total_refs 2407783 # Total number of references to valid blocks. +system.l2c.sampled_refs 424213 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.675882 # Average number of references to valid blocks. system.l2c.warmup_cycle 5611809000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12322.596332 # Average occupied blocks per context -system.l2c.occ_blocks::1 22622.036213 # Average occupied blocks per context -system.l2c.occ_percent::0 0.188028 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.345185 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1801216 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1801216 # number of ReadReq hits -system.l2c.Writeback_hits::0 835065 # number of Writeback hits -system.l2c.Writeback_hits::total 835065 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 13 # number of UpgradeReq hits +system.l2c.occ_blocks::0 12320.874417 # Average occupied blocks per context +system.l2c.occ_blocks::1 22621.267294 # Average occupied blocks per context +system.l2c.occ_percent::0 0.188002 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.345173 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1800422 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1800422 # number of ReadReq hits +system.l2c.Writeback_hits::0 834998 # number of Writeback hits +system.l2c.Writeback_hits::total 834998 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 183191 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183191 # number of ReadExReq hits -system.l2c.demand_hits::0 1984407 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::0 183185 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183185 # number of ReadExReq hits +system.l2c.demand_hits::0 1983607 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1984407 # number of demand (read+write) hits -system.l2c.overall_hits::0 1984407 # number of overall hits +system.l2c.demand_hits::total 1983607 # number of demand (read+write) hits +system.l2c.overall_hits::0 1983607 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1984407 # number of overall hits -system.l2c.ReadReq_misses::0 308126 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308126 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 31 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 31 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 116919 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116919 # number of ReadExReq misses -system.l2c.demand_misses::0 425045 # number of demand (read+write) misses +system.l2c.overall_hits::total 1983607 # number of overall hits +system.l2c.ReadReq_misses::0 308136 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308136 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 36 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 36 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 116850 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116850 # number of ReadExReq misses +system.l2c.demand_misses::0 424986 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 425045 # number of demand (read+write) misses -system.l2c.overall_misses::0 425045 # number of overall misses +system.l2c.demand_misses::total 424986 # number of demand (read+write) misses +system.l2c.overall_misses::0 424986 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 425045 # number of overall misses -system.l2c.ReadReq_miss_latency 16035962500 # number of ReadReq miss cycles +system.l2c.overall_misses::total 424986 # number of overall misses +system.l2c.ReadReq_miss_latency 16038372500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency 425000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6137530000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22173492500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22173492500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2109342 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2109342 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 835065 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835065 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 44 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 44 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_miss_latency 6129219000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22167591500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22167591500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2108558 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2108558 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 834998 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 834998 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 52 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 52 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 300110 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300110 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2409452 # number of demand (read+write) accesses +system.l2c.ReadExReq_accesses::0 300035 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300035 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2408593 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2409452 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2409452 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2408593 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2408593 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2409452 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.146077 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.704545 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.389587 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.176407 # miss rate for demand accesses +system.l2c.overall_accesses::total 2408593 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.146136 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.692308 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.389455 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.176446 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.176407 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.176446 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52043.522780 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52049.655022 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 13709.677419 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 11805.555556 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52493.863273 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52453.735558 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52167.399922 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52160.757060 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52167.399922 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52160.757060 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -99,43 +99,43 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 117722 # number of writebacks +system.l2c.writebacks 117715 # number of writebacks system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 308126 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 31 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 116919 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 425045 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 425045 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 308136 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 36 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 116850 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 424986 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 424986 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12333217500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 1300000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4715307000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17048524500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17048524500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 809593500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1114721998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 1924315498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146077 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12334391000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 1500000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4708487500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17042878500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17042878500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 810033000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1115131998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 1925164998 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146136 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.704545 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.692308 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.389587 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.389455 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.176407 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.176446 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.176407 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.176446 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40026.539468 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 41935.483871 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40329.689785 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40109.928361 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40109.928361 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40029.048862 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 41666.666667 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40295.143346 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40102.211602 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40102.211602 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -143,13 +143,13 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.266801 # Cycle average of tags in use +system.iocache.tagsinuse 1.260372 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708338851000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.266801 # Average occupied blocks per context -system.iocache.occ_percent::1 0.079175 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708338825000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 1.260372 # Average occupied blocks per context +system.iocache.occ_percent::1 0.078773 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -167,9 +167,9 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5722275806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5742213804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5742213804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency 5722330806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5742268804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5742268804 # number of overall miss cycles system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) @@ -192,19 +192,19 @@ system.iocache.ReadReq_avg_miss_latency::0 inf # system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137713.607191 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137714.930834 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137620.462648 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137621.780803 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137620.462648 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137621.780803 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64594068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64585068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10468 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10462 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6170.621704 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6173.300325 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -217,9 +217,9 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3561421998 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3572363996 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3572363996 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561477996 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3572419994 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3572419994 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -234,9 +234,9 @@ system.iocache.overall_mshr_miss_rate::0 inf # ms system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85710.001877 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85616.872283 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85616.872283 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85711.349538 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85618.214356 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85618.214356 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -257,22 +257,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10154080 # DTB read hits -system.cpu.dtb.read_misses 43144 # DTB read misses -system.cpu.dtb.read_acv 557 # DTB read access violations -system.cpu.dtb.read_accesses 952445 # DTB read accesses -system.cpu.dtb.write_hits 6614848 # DTB write hits -system.cpu.dtb.write_misses 9467 # DTB write misses -system.cpu.dtb.write_acv 320 # DTB write access violations -system.cpu.dtb.write_accesses 334339 # DTB write accesses -system.cpu.dtb.data_hits 16768928 # DTB hits -system.cpu.dtb.data_misses 52611 # DTB misses -system.cpu.dtb.data_acv 877 # DTB access violations -system.cpu.dtb.data_accesses 1286784 # DTB accesses -system.cpu.itb.fetch_hits 1336327 # ITB hits -system.cpu.itb.fetch_misses 39787 # ITB misses -system.cpu.itb.fetch_acv 1065 # ITB acv -system.cpu.itb.fetch_accesses 1376114 # ITB accesses +system.cpu.dtb.read_hits 10156439 # DTB read hits +system.cpu.dtb.read_misses 47122 # DTB read misses +system.cpu.dtb.read_acv 587 # DTB read access violations +system.cpu.dtb.read_accesses 977122 # DTB read accesses +system.cpu.dtb.write_hits 6633598 # DTB write hits +system.cpu.dtb.write_misses 11598 # DTB write misses +system.cpu.dtb.write_acv 414 # DTB write access violations +system.cpu.dtb.write_accesses 348122 # DTB write accesses +system.cpu.dtb.data_hits 16790037 # DTB hits +system.cpu.dtb.data_misses 58720 # DTB misses +system.cpu.dtb.data_acv 1001 # DTB access violations +system.cpu.dtb.data_accesses 1325244 # DTB accesses +system.cpu.itb.fetch_hits 1333506 # ITB hits +system.cpu.itb.fetch_misses 39875 # ITB misses +system.cpu.itb.fetch_acv 1125 # ITB acv +system.cpu.itb.fetch_accesses 1373381 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,275 +285,275 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 117237485 # number of cpu cycles simulated +system.cpu.numCycles 116343633 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14455551 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12084424 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 532367 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13050115 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 6745735 # Number of BTB hits +system.cpu.BPredUnit.lookups 14429393 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12066685 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 532769 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13006399 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 6718907 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 978348 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45278 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29236023 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 74164805 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14455551 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7724083 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 14385478 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2439202 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37224537 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33011 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 262840 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 335923 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9135306 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 330174 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 83080083 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.892691 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.209867 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 975114 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45137 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29132882 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 73870037 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14429393 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7694021 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 14329837 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2400358 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36580859 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32012 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 259840 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 335514 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 170 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9103703 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 330872 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 82240103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.898224 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.215946 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68694605 82.68% 82.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1023953 1.23% 83.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2033478 2.45% 86.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 975932 1.17% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2976777 3.58% 91.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 700548 0.84% 91.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 794915 0.96% 92.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1072238 1.29% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4807637 5.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67910266 82.58% 82.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1028745 1.25% 83.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2026192 2.46% 86.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 969086 1.18% 87.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2957231 3.60% 91.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 692695 0.84% 91.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 793723 0.97% 92.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1070407 1.30% 94.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4791758 5.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 83080083 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123301 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632603 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30551542 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36838313 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 13095678 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1034253 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1560296 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 613869 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42144 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 72480994 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 127271 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1560296 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31800995 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12812731 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19871114 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 12262779 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4772166 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 68475649 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4094 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 996372 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1464404 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 45853535 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 83251938 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 82772461 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479477 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38260770 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7592757 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1700825 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251533 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12956852 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10812074 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7051744 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2165147 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2346616 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 60096918 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2117388 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 58031681 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 82818 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8738509 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4816872 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1449642 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 83080083 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.698503 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.311149 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 82240103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.124024 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.634930 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30393620 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36243117 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 13115942 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 960226 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1527197 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 611480 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42119 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 72202344 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 128169 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1527197 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31599738 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12790599 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19770106 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 12256569 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4295892 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 68223425 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6893 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 500375 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1520799 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 45688467 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 82930883 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 82451857 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479026 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38262876 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7425583 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1700626 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251543 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12011289 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10748783 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7011270 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1273745 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 840870 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 59873388 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2116185 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 58064745 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 115927 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8494287 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4438181 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1448436 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 82240103 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.706039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.353017 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56639169 68.17% 68.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11994103 14.44% 82.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5929931 7.14% 89.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3560683 4.29% 94.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2591551 3.12% 97.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1336446 1.61% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 797054 0.96% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 184259 0.22% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 46887 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56753994 69.01% 69.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11193552 13.61% 82.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5499635 6.69% 89.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3512602 4.27% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2643529 3.21% 96.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1548822 1.88% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 707324 0.86% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 273213 0.33% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 107432 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 83080083 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 82240103 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 68783 12.83% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 305726 57.04% 69.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 161454 30.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 64991 8.48% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 378109 49.32% 57.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 323577 42.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39661101 68.34% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62145 0.11% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25610 0.04% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10623971 18.31% 86.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6695582 11.54% 98.36% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952355 1.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39655118 68.29% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62174 0.11% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10635929 18.32% 86.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6722688 11.58% 98.36% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952312 1.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 58031681 # Type of FU issued -system.cpu.iq.rate 0.494993 # Inst issue rate -system.cpu.iq.fu_busy_cnt 535963 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009236 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 199072460 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 70641414 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56449878 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 689765 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 333951 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328040 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58199260 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361103 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 552721 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 58064745 # Type of FU issued +system.cpu.iq.rate 0.499080 # Inst issue rate +system.cpu.iq.fu_busy_cnt 766677 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013204 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 198560467 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 70176120 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56485252 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 691729 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 332805 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328298 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58461376 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 362765 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 576950 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1698615 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15451 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 23451 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 659180 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1635037 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13784 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 26178 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 618376 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18682 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 200829 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18266 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 170591 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1560296 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8872665 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 625505 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 65852816 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 871025 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10812074 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7051744 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1870069 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 491565 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7470 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 23451 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 385257 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 383183 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 768440 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57350351 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10227555 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 681329 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1527197 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8965647 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 616674 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 65615916 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 866303 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10748783 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7011270 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1869859 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 484759 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15737 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 26178 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 387398 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 383164 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 770562 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57355078 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10233934 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 709666 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3638510 # number of nop insts executed -system.cpu.iew.exec_refs 16867130 # number of memory reference insts executed -system.cpu.iew.exec_branches 9102477 # Number of branches executed -system.cpu.iew.exec_stores 6639575 # Number of stores executed -system.cpu.iew.exec_rate 0.489181 # Inst execution rate -system.cpu.iew.wb_sent 56909286 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56777918 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28083144 # num instructions producing a value -system.cpu.iew.wb_consumers 37838196 # num instructions consuming a value +system.cpu.iew.exec_nop 3626343 # number of nop insts executed +system.cpu.iew.exec_refs 16894519 # number of memory reference insts executed +system.cpu.iew.exec_branches 9105401 # Number of branches executed +system.cpu.iew.exec_stores 6660585 # Number of stores executed +system.cpu.iew.exec_rate 0.492980 # Inst execution rate +system.cpu.iew.wb_sent 56953037 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56813550 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28082126 # num instructions producing a value +system.cpu.iew.wb_consumers 37827297 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.484298 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742190 # average fanout of values written-back +system.cpu.iew.wb_rate 0.488325 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742377 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56286421 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9443080 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667746 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 702134 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 81519787 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.690463 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.566765 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56289333 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9199733 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667749 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 702560 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80712906 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.697402 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.610815 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59658965 73.18% 73.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9249179 11.35% 84.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5213125 6.39% 90.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2451549 3.01% 93.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1701758 2.09% 96.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 617367 0.76% 96.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 434350 0.53% 97.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 791574 0.97% 98.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1401920 1.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59526212 73.75% 73.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8907000 11.04% 84.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4712189 5.84% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2603041 3.23% 93.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1533921 1.90% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 653559 0.81% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 475046 0.59% 97.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 520427 0.64% 97.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1781511 2.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 81519787 # Number of insts commited each cycle -system.cpu.commit.count 56286421 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 80712906 # Number of insts commited each cycle +system.cpu.commit.count 56289333 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15506023 # Number of memory references committed -system.cpu.commit.loads 9113459 # Number of loads committed -system.cpu.commit.membars 227879 # Number of memory barriers committed -system.cpu.commit.branches 8462155 # Number of branches committed +system.cpu.commit.refs 15506640 # Number of memory references committed +system.cpu.commit.loads 9113746 # Number of loads committed +system.cpu.commit.membars 227885 # Number of memory barriers committed +system.cpu.commit.branches 8462674 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52124782 # Number of committed integer instructions. -system.cpu.commit.function_calls 744514 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1401920 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52127663 # Number of committed integer instructions. +system.cpu.commit.function_calls 744579 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1781511 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 145596309 # The number of ROB reads -system.cpu.rob.rob_writes 133022104 # The number of ROB writes -system.cpu.timesIdled 1258228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34157402 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 53091761 # Number of Instructions Simulated -system.cpu.committedInsts_total 53091761 # Number of Instructions Simulated -system.cpu.cpi 2.208205 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.208205 # CPI: Total CPI of All Threads -system.cpu.ipc 0.452857 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.452857 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 75150720 # number of integer regfile reads -system.cpu.int_regfile_writes 41017067 # number of integer regfile writes -system.cpu.fp_regfile_reads 166113 # number of floating regfile reads -system.cpu.fp_regfile_writes 167453 # number of floating regfile writes -system.cpu.misc_regfile_reads 1996494 # number of misc regfile reads -system.cpu.misc_regfile_writes 949911 # number of misc regfile writes +system.cpu.rob.rob_reads 144169402 # The number of ROB reads +system.cpu.rob.rob_writes 132508314 # The number of ROB writes +system.cpu.timesIdled 1255085 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34103530 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 53094627 # Number of Instructions Simulated +system.cpu.committedInsts_total 53094627 # Number of Instructions Simulated +system.cpu.cpi 2.191251 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.191251 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456360 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456360 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 75184837 # number of integer regfile reads +system.cpu.int_regfile_writes 41033576 # number of integer regfile writes +system.cpu.fp_regfile_reads 166484 # number of floating regfile reads +system.cpu.fp_regfile_writes 167413 # number of floating regfile writes +system.cpu.misc_regfile_reads 1996811 # number of misc regfile reads +system.cpu.misc_regfile_writes 949905 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -585,231 +585,231 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # 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number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1064551 # number of overall misses +system.cpu.icache.demand_misses::total 1066279 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1066279 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1064551 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15926988994 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15926988994 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15926988994 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9135306 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9135306 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9135306 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1066279 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15932595494 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15932595494 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15932595494 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9103703 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9103703 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9103703 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9135306 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9135306 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9103703 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9103703 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9135306 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.116532 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.116532 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9103703 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.117126 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.117126 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.116532 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.117126 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14961.226840 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14942.238846 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14961.226840 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14942.238846 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14961.226840 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14942.238846 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1261996 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 1325996 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 120 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10516.633333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10607.968000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 232 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 58739 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 58739 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 58739 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1005812 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1005812 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1005812 # number of overall MSHR misses +system.cpu.icache.writebacks 235 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 60920 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 60920 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 60920 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1005359 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1005359 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1005359 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12051659996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12051659996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12051659996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12047978496 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12047978496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12047978496 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110102 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110434 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.110102 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.110434 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.110102 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.110434 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11982.020493 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11982.020493 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11982.020493 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11983.757539 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11983.757539 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11983.757539 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1403296 # number of replacements -system.cpu.dcache.tagsinuse 511.995990 # Cycle average of tags in use -system.cpu.dcache.total_refs 12128638 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1403808 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.639813 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1402933 # number of replacements +system.cpu.dcache.tagsinuse 511.995988 # Cycle average of tags in use +system.cpu.dcache.total_refs 12110548 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1403445 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.629158 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 19282000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.995990 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 511.995988 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 7493448 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7493448 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4222901 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4222901 # 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miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.314394 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105292 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.240661 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.242404 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.240661 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.242404 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 21573.928434 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 21527.673772 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 29637.169294 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 29855.716180 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15630.814203 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14975.474369 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 25774.459847 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 25835.068930 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 25774.459847 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 25835.068930 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 916364836 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 209000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 100291 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9137.059517 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23222.222222 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 919195309 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 193500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 102335 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8982.218293 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 24187.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 834833 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 691203 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1635634 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 5726 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2326837 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2326837 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1087666 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 298810 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 17536 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks 834763 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 719698 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1637137 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 5136 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2356835 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2356835 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1087356 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 298794 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 17473 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1386476 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1386476 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 1386150 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1386150 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24813377000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8487477836 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207860000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24800644000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8504282309 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206126500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 33300854836 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 33300854836 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904007000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234009498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 2138016498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117303 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency 33304926309 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33304926309 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904508000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234433998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 2138941998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117129 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048529 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048524 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081447 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081373 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.089858 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.089770 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.089858 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.089770 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22813.416067 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28404.263030 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11853.330292 # average LoadLockedReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22808.210007 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28462.025037 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11796.858010 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24018.342067 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24018.342067 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24026.928045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24026.928045 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -817,27 +817,27 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6434 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211594 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74884 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 241 0.13% 41.09% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105815 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182822 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73517 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73519 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149159 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1820013648500 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 93762000 0.01% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 384408000 0.02% 97.94% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38216235500 2.06% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1858708054000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981745 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6435 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211583 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74879 40.96% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 243 0.13% 41.09% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1881 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105809 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182812 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73512 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1881 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73515 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149151 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1819252477000 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94027000 0.01% 97.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 384302500 0.02% 97.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38165726500 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1857896533000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981744 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694788 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694790 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -876,8 +876,8 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175485 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6787 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175475 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6786 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed @@ -885,20 +885,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5215 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192443 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5956 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2101 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.callpal::total 192432 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5954 # number of protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320349 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320289 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080914 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.401263 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29483328500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2787065000 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1826437652500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.401126 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29181178000 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2689752000 0.14% 1.72% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1826025595000 98.28% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 4a2cdb533..003c8a4f1 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -132,6 +132,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index 3ff5b25a6..71e7a1461 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 16 2011 18:25:06 -gem5 started Aug 16 2011 18:26:03 -gem5 executing on nadc-0270 +gem5 compiled Aug 18 2011 19:13:50 +gem5 started Aug 18 2011 19:17:05 +gem5 executing on nadc-0330 command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 79671140500 because m5_exit instruction encountered +Exiting @ tick 79074238500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 149a25fba..a632bc081 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,101 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.079671 # Number of seconds simulated -sim_ticks 79671140500 # Number of ticks simulated +sim_seconds 0.079074 # Number of seconds simulated +sim_ticks 79074238500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87754 # Simulator instruction rate (inst/s) -host_tick_rate 134768287 # Simulator tick rate (ticks/s) -host_mem_usage 390652 # Number of bytes of host memory used -host_seconds 591.17 # Real time elapsed on the host -sim_insts 51877383 # Number of instructions simulated -system.l2c.replacements 94989 # number of replacements -system.l2c.tagsinuse 38233.191793 # Cycle average of tags in use -system.l2c.total_refs 1049232 # Total number of references to valid blocks. -system.l2c.sampled_refs 127381 # Sample count of references to valid blocks. -system.l2c.avg_refs 8.236958 # Average number of references to valid blocks. +host_inst_rate 94294 # Simulator instruction rate (inst/s) +host_tick_rate 143722804 # Simulator tick rate (ticks/s) +host_mem_usage 389860 # Number of bytes of host memory used +host_seconds 550.19 # Real time elapsed on the host +sim_insts 51879448 # Number of instructions simulated +system.l2c.replacements 94945 # number of replacements +system.l2c.tagsinuse 38237.402486 # Cycle average of tags in use +system.l2c.total_refs 1052101 # Total number of references to valid blocks. +system.l2c.sampled_refs 127394 # Sample count of references to valid blocks. +system.l2c.avg_refs 8.258639 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 6845.786735 # Average occupied blocks per context -system.l2c.occ_blocks::1 31387.405058 # Average occupied blocks per context -system.l2c.occ_percent::0 0.104458 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.478934 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 745449 # number of ReadReq hits -system.l2c.ReadReq_hits::1 96884 # number of ReadReq hits -system.l2c.ReadReq_hits::total 842333 # number of ReadReq hits -system.l2c.Writeback_hits::0 434303 # number of Writeback hits -system.l2c.Writeback_hits::total 434303 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 53 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 53 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 11 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 61363 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 61363 # number of ReadExReq hits -system.l2c.demand_hits::0 806812 # number of demand (read+write) hits -system.l2c.demand_hits::1 96884 # number of demand (read+write) hits -system.l2c.demand_hits::total 903696 # number of demand (read+write) hits -system.l2c.overall_hits::0 806812 # number of overall hits -system.l2c.overall_hits::1 96884 # number of overall hits -system.l2c.overall_hits::total 903696 # number of overall hits -system.l2c.ReadReq_misses::0 21092 # number of ReadReq misses -system.l2c.ReadReq_misses::1 91 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21183 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 1724 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1724 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 107716 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107716 # number of ReadExReq misses -system.l2c.demand_misses::0 128808 # number of demand (read+write) misses -system.l2c.demand_misses::1 91 # number of demand (read+write) misses -system.l2c.demand_misses::total 128899 # number of demand (read+write) misses -system.l2c.overall_misses::0 128808 # number of overall misses -system.l2c.overall_misses::1 91 # number of overall misses -system.l2c.overall_misses::total 128899 # number of overall misses -system.l2c.ReadReq_miss_latency 1106899000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 5649720000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 6756619000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 6756619000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 766541 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 96975 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 863516 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 434303 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 434303 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 1777 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1777 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 11 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 169079 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169079 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 935620 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 96975 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1032595 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 935620 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 96975 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1032595 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027516 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000938 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028454 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.970174 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.637075 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.137671 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000938 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.138610 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.137671 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000938 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.138610 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52479.565712 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 12163725.274725 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12216204.840437 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 392.111369 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 6834.607637 # Average occupied blocks per context +system.l2c.occ_blocks::1 31402.794849 # Average occupied blocks per context +system.l2c.occ_percent::0 0.104288 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.479169 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 744764 # number of ReadReq hits +system.l2c.ReadReq_hits::1 111075 # number of ReadReq hits +system.l2c.ReadReq_hits::total 855839 # number of ReadReq hits +system.l2c.Writeback_hits::0 435185 # number of Writeback hits +system.l2c.Writeback_hits::total 435185 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 29 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 61163 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 61163 # number of ReadExReq hits +system.l2c.demand_hits::0 805927 # number of demand (read+write) hits +system.l2c.demand_hits::1 111075 # number of demand (read+write) hits +system.l2c.demand_hits::total 917002 # number of demand (read+write) hits +system.l2c.overall_hits::0 805927 # number of overall hits +system.l2c.overall_hits::1 111075 # number of overall hits +system.l2c.overall_hits::total 917002 # number of overall hits +system.l2c.ReadReq_misses::0 21158 # number of ReadReq misses +system.l2c.ReadReq_misses::1 88 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21246 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 1695 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1695 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 107672 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107672 # number of ReadExReq misses +system.l2c.demand_misses::0 128830 # number of demand (read+write) misses +system.l2c.demand_misses::1 88 # number of demand (read+write) misses +system.l2c.demand_misses::total 128918 # number of demand (read+write) misses +system.l2c.overall_misses::0 128830 # number of overall misses +system.l2c.overall_misses::1 88 # number of overall misses +system.l2c.overall_misses::total 128918 # number of overall misses +system.l2c.ReadReq_miss_latency 1110312000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 728500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 5647552000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 6757864000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 6757864000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 765922 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 111163 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 877085 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 435185 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 435185 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 1724 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1724 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 168835 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 168835 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 934757 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 111163 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1045920 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 934757 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 111163 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1045920 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.027624 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000792 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028416 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.983179 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.637735 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.137822 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000792 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.138614 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.137822 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000792 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.138614 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52477.171755 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 12617181.818182 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 12669658.989937 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 429.793510 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52450.146682 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52451.445130 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52454.963977 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 74248560.439560 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 74301015.403538 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52454.963977 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 74248560.439560 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 74301015.403538 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52455.670263 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 76793909.090909 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 76846364.761172 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52455.670263 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 76793909.090909 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 76846364.761172 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,44 +105,50 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 87788 # number of writebacks -system.l2c.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 54 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 54 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 21129 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 1724 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 107716 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 128845 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 128845 # number of overall MSHR misses +system.l2c.writebacks 87817 # number of writebacks +system.l2c.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 52 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 52 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 21194 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1695 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 1 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 107672 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 128866 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 128866 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 846282000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 68961500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4309813000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 5156095000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 5156095000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 28946860000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 748497446 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 29695357446 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027564 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.217881 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.245445 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.970174 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 848895000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 67801500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 40000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4307970000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 5156865000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 5156865000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 28946635000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 749324446 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 29695959446 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027671 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.190657 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.218328 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.983179 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.637075 # mshr miss rate for ReadExReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.637735 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.137711 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.328641 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.466352 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.137711 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.328641 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.466352 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40053.102371 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.870070 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40010.889747 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40017.812100 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40017.812100 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.137860 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.159253 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.297113 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.137860 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.159253 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.297113 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40053.552892 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.884956 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40010.123338 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40017.265997 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40017.265997 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -150,27 +157,27 @@ system.l2c.soft_prefetch_mshr_full 0 # nu system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 13454003 # DTB read hits -system.cpu.dtb.read_misses 56352 # DTB read misses -system.cpu.dtb.write_hits 7087382 # DTB write hits -system.cpu.dtb.write_misses 9992 # DTB write misses +system.cpu.dtb.read_hits 25900550 # DTB read hits +system.cpu.dtb.read_misses 64651 # DTB read misses +system.cpu.dtb.write_hits 7192881 # DTB write hits +system.cpu.dtb.write_misses 13036 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 2710 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2485 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 947 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 2886 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3633 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1097 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 572 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 13510355 # DTB read accesses -system.cpu.dtb.write_accesses 7097374 # DTB write accesses +system.cpu.dtb.perms_faults 915 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25965201 # DTB read accesses +system.cpu.dtb.write_accesses 7205917 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 20541385 # DTB hits -system.cpu.dtb.misses 66344 # DTB misses -system.cpu.dtb.accesses 20607729 # DTB accesses -system.cpu.itb.inst_hits 6364119 # ITB inst hits -system.cpu.itb.inst_misses 7846 # ITB inst misses +system.cpu.dtb.hits 33093431 # DTB hits +system.cpu.dtb.misses 77687 # DTB misses +system.cpu.dtb.accesses 33171118 # DTB accesses +system.cpu.itb.inst_hits 6310237 # ITB inst hits +system.cpu.itb.inst_misses 7717 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -179,515 +186,515 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 1638 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 1666 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 4337 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 4317 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 6371965 # ITB inst accesses -system.cpu.itb.hits 6364119 # DTB hits -system.cpu.itb.misses 7846 # DTB misses -system.cpu.itb.accesses 6371965 # DTB accesses -system.cpu.numCycles 159342282 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 6317954 # ITB inst accesses +system.cpu.itb.hits 6310237 # DTB hits +system.cpu.itb.misses 7717 # DTB misses +system.cpu.itb.accesses 6317954 # DTB accesses +system.cpu.numCycles 158148478 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 12557399 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10608534 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 646709 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11154990 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8780554 # Number of BTB hits +system.cpu.BPredUnit.lookups 12403718 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10473693 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 647177 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11077874 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8725285 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 870083 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 147860 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 16065730 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 58984795 # Number of instructions fetch has processed -system.cpu.fetch.Branches 12557399 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9650637 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 15473829 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2924896 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 92331 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 54317634 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 13079 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 97476 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 352 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 6359256 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 271099 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4481 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 88159945 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.843576 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.082771 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 825346 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 148570 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15848399 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 58464536 # Number of instructions fetch has processed +system.cpu.fetch.Branches 12403718 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9550631 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 15311451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2844155 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 92931 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 55530026 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 15278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87268 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 242 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 6305391 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 273417 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4478 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 88893250 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.826227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.063220 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 72705101 82.47% 82.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1269251 1.44% 83.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1767868 2.01% 85.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1323104 1.50% 87.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4670929 5.30% 92.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 784846 0.89% 93.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 764674 0.87% 94.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 594095 0.67% 95.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4280077 4.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 73600633 82.80% 82.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1267818 1.43% 84.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1758600 1.98% 86.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1303689 1.47% 87.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4624910 5.20% 92.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 783016 0.88% 93.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 755228 0.85% 94.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 591057 0.66% 95.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4208299 4.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 88159945 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.078808 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.370177 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 18165141 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 52904570 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 13778388 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1284946 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2026900 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1217125 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 74219 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 71956332 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 242640 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2026900 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19696589 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 30046666 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18688452 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 12532114 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5169224 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 69519785 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 458017 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 271395 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2649588 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 136 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 71288380 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 300070248 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 300002932 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 67316 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 51888569 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 19399810 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 812076 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 663924 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 14280198 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 12080470 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8183550 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3516652 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4162890 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 62699092 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4040128 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 64163344 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 176578 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14335802 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 27947195 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1077859 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 88159945 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.727806 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.267218 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 88893250 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.078431 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.369681 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17889712 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 54159673 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 13693957 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1214512 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1935396 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1196991 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 73836 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 71078898 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 241088 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1935396 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19399410 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 33418578 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16504909 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 12375675 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5259282 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 68683031 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 458239 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 182953 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2809051 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 307 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 70419738 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 296318415 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296251688 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 66727 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 51890716 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18529021 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 807343 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 660120 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 14009466 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 11753719 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8138684 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 887625 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1407204 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 61880073 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4035866 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 76596153 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165478 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 13504163 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 24143581 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1073057 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 88893250 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.861664 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.427794 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 57192817 64.87% 64.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14605860 16.57% 81.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7161098 8.12% 89.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4501948 5.11% 94.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2827013 3.21% 97.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1117751 1.27% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 514797 0.58% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 165433 0.19% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 73228 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55657719 62.61% 62.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14175743 15.95% 78.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6670691 7.50% 86.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4258110 4.79% 90.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5767054 6.49% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1381276 1.55% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 654272 0.74% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 222610 0.25% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 105775 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 88159945 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 88893250 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31666 2.83% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 952275 85.11% 87.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 134939 12.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 28225 0.64% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4144387 93.61% 94.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 254758 5.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2393223 3.73% 3.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39946954 62.26% 65.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 68785 0.11% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 1 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 5 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 883 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 14271744 22.24% 88.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7481749 11.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2393223 3.12% 3.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39796206 51.96% 55.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 68882 0.09% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 880 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26733019 34.90% 90.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7603891 9.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 64163344 # Type of FU issued -system.cpu.iq.rate 0.402676 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1118882 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017438 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 217833874 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 81127166 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 59171315 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 14043 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9868 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6386 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 62881739 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7264 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 405736 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 76596153 # Type of FU issued +system.cpu.iq.rate 0.484331 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4427371 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.057801 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 246739451 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 79485386 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 59144129 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 16089 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9683 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6534 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 78621825 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8476 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 479578 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2901377 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4794 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 62495 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1106451 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2574412 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7673 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 75993 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1060962 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3460272 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8665 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 15898252 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 9806 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2026900 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18611531 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 438534 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 66914101 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 333018 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 12080470 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8183550 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4008088 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 19000 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 218050 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 62495 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 538548 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 174972 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 713520 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 63251439 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 13958320 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 911905 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1935396 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 21193831 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 271998 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 66089327 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 340309 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 11753719 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8138684 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4003938 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 14746 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 54897 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 75993 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 528463 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 171712 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 700175 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 75657925 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 26402371 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 938228 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 174881 # number of nop insts executed -system.cpu.iew.exec_refs 21351791 # number of memory reference insts executed -system.cpu.iew.exec_branches 10154168 # Number of branches executed -system.cpu.iew.exec_stores 7393471 # Number of stores executed -system.cpu.iew.exec_rate 0.396953 # Inst execution rate -system.cpu.iew.wb_sent 62861793 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 59177701 # cumulative count of insts written-back -system.cpu.iew.wb_producers 31313815 # num instructions producing a value -system.cpu.iew.wb_consumers 56258797 # num instructions consuming a value +system.cpu.iew.exec_nop 173388 # number of nop insts executed +system.cpu.iew.exec_refs 33905993 # number of memory reference insts executed +system.cpu.iew.exec_branches 10120483 # Number of branches executed +system.cpu.iew.exec_stores 7503622 # Number of stores executed +system.cpu.iew.exec_rate 0.478398 # Inst execution rate +system.cpu.iew.wb_sent 75261887 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 59150663 # cumulative count of insts written-back +system.cpu.iew.wb_producers 31134340 # num instructions producing a value +system.cpu.iew.wb_consumers 55908801 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.371387 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.556603 # average fanout of values written-back +system.cpu.iew.wb_rate 0.374020 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.556877 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 52000613 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 12648879 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2962269 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 619998 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 86133073 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.603724 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.472813 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 52002678 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 11830112 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2962809 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 620839 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 86957882 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.598021 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.499250 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 65560207 76.12% 76.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 10449932 12.13% 88.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2547278 2.96% 91.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1482527 1.72% 92.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3350826 3.89% 96.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 701267 0.81% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 459898 0.53% 98.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 309587 0.36% 98.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1271551 1.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67332100 77.43% 77.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9518451 10.95% 88.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2434571 2.80% 91.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1362976 1.57% 92.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3331765 3.83% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 735683 0.85% 97.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 547610 0.63% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 322786 0.37% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1371940 1.58% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 86133073 # Number of insts commited each cycle -system.cpu.commit.count 52000613 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 86957882 # Number of insts commited each cycle +system.cpu.commit.count 52002678 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 16256192 # Number of memory references committed -system.cpu.commit.loads 9179093 # Number of loads committed +system.cpu.commit.refs 16257029 # Number of memory references committed +system.cpu.commit.loads 9179307 # Number of loads committed system.cpu.commit.membars 3 # Number of memory barriers committed -system.cpu.commit.branches 8429232 # Number of branches committed +system.cpu.commit.branches 8429555 # Number of branches committed system.cpu.commit.fp_insts 6017 # Number of committed floating point instructions. -system.cpu.commit.int_insts 42424073 # Number of committed integer instructions. -system.cpu.commit.function_calls 530211 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1271551 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 42425734 # Number of committed integer instructions. +system.cpu.commit.function_calls 530212 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1371940 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 148569921 # The number of ROB reads -system.cpu.rob.rob_writes 131336271 # The number of ROB writes -system.cpu.timesIdled 1042391 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 71182337 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 51877383 # Number of Instructions Simulated -system.cpu.committedInsts_total 51877383 # Number of Instructions Simulated -system.cpu.cpi 3.071517 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.071517 # CPI: Total CPI of All Threads -system.cpu.ipc 0.325572 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.325572 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 282588210 # number of integer regfile reads -system.cpu.int_regfile_writes 61106256 # number of integer regfile writes -system.cpu.fp_regfile_reads 4893 # number of floating regfile reads -system.cpu.fp_regfile_writes 1856 # number of floating regfile writes -system.cpu.misc_regfile_reads 78190097 # number of misc regfile reads -system.cpu.misc_regfile_writes 511386 # number of misc regfile writes -system.cpu.icache.replacements 514643 # number of replacements -system.cpu.icache.tagsinuse 498.228732 # Cycle average of tags in use -system.cpu.icache.total_refs 5803201 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 515155 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.264961 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 4757853000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 498.228732 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.973103 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 5803201 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5803201 # number of ReadReq hits -system.cpu.icache.demand_hits::0 5803201 # number of demand (read+write) hits +system.cpu.rob.rob_reads 148477639 # The number of ROB reads +system.cpu.rob.rob_writes 129612178 # The number of ROB writes +system.cpu.timesIdled 1077202 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 69255228 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 51879448 # Number of Instructions Simulated +system.cpu.committedInsts_total 51879448 # Number of Instructions Simulated +system.cpu.cpi 3.048384 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.048384 # CPI: Total CPI of All Threads +system.cpu.ipc 0.328043 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.328043 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 332418442 # number of integer regfile reads +system.cpu.int_regfile_writes 60962055 # number of integer regfile writes +system.cpu.fp_regfile_reads 5604 # number of floating regfile reads +system.cpu.fp_regfile_writes 1962 # number of floating regfile writes +system.cpu.misc_regfile_reads 77838046 # number of misc regfile reads +system.cpu.misc_regfile_writes 516400 # number of misc regfile writes +system.cpu.icache.replacements 512227 # number of replacements +system.cpu.icache.tagsinuse 498.830885 # Cycle average of tags in use +system.cpu.icache.total_refs 5748931 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 512739 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.212198 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 5183255000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 498.830885 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.974279 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 5748931 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5748931 # number of ReadReq hits +system.cpu.icache.demand_hits::0 5748931 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5803201 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 5803201 # number of overall hits +system.cpu.icache.demand_hits::total 5748931 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 5748931 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 5803201 # number of overall hits -system.cpu.icache.ReadReq_misses::0 555943 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 555943 # number of ReadReq misses -system.cpu.icache.demand_misses::0 555943 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 5748931 # number of overall hits +system.cpu.icache.ReadReq_misses::0 556349 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 556349 # number of ReadReq misses +system.cpu.icache.demand_misses::0 556349 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 555943 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 555943 # number of overall misses +system.cpu.icache.demand_misses::total 556349 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 556349 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 555943 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 8279205988 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 8279205988 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 8279205988 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 6359144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6359144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 6359144 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 556349 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 8277697991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 8277697991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 8277697991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 6305280 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6305280 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 6305280 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6359144 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 6359144 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 6305280 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 6305280 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6359144 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.087424 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.087424 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 6305280 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.088235 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.088235 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.087424 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.088235 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14892.184969 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14878.606758 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14892.184969 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14878.606758 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14892.184969 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14878.606758 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1847492 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 1588993 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 239 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 215 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7730.092050 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7390.665116 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 43333 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 40711 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 40711 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 40711 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 515232 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 515232 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 515232 # number of overall MSHR misses +system.cpu.icache.writebacks 43070 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 43600 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 43600 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 43600 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 512749 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 512749 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 512749 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 6216481992 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 6216481992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 6216481992 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 6199069493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 6199069493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 6199069493 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency 5831500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 5831500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.081022 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.081321 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.081022 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.081321 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.081022 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.081321 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12065.403531 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12065.403531 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12065.403531 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12089.871444 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12089.871444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12089.871444 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # 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Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48622000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.738850 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999490 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 8178281 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8178281 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4620670 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4620670 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 103371 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 103371 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 104399 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 104399 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 12798951 # number of demand (read+write) hits +system.cpu.dcache.occ_blocks::0 511.736879 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999486 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 8094618 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8094618 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4617752 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4617752 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 103516 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 103516 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 104961 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 104961 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 12712370 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12798951 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 12798951 # number of overall hits +system.cpu.dcache.demand_hits::total 12712370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 12712370 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 12798951 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 482976 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 482976 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 2042377 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2042377 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 6546 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6546 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::0 11 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 2525353 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 12712370 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 499321 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 499321 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 2045255 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2045255 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 6620 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6620 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::0 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::0 2544576 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2525353 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 2525353 # number of overall misses +system.cpu.dcache.demand_misses::total 2544576 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 2544576 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2525353 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 7135135000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 80554552279 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 99000500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency 159000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 87689687279 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 87689687279 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 8661257 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8661257 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6663047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6663047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 109917 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 109917 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 104410 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 104410 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15324304 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 2544576 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 7292417500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 81386403267 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 99908000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency 55000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency 88678820767 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 88678820767 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 8593939 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8593939 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6663007 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6663007 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 110136 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 110136 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 104962 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 104962 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 15256946 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15324304 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15324304 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 15256946 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 15256946 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15324304 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.055763 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.306523 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.059554 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000105 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.164794 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 15256946 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.058102 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.306957 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.060108 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000010 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::0 0.166781 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.164794 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.166781 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 14773.270307 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 14604.668139 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 39441.568466 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 39792.790272 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15123.816071 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15091.842900 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14454.545455 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 55000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 34723.734575 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 34850.136434 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 34723.734575 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 34850.136434 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7890493 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 750500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1025 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 25 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7698.041951 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 30020 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 8903490 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 871500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1190 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 31 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7481.924370 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28112.903226 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 390970 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 234674 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1871578 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 927 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2106252 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2106252 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 248302 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 170799 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 5619 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 419101 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 419101 # number of overall MSHR misses +system.cpu.dcache.writebacks 392115 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 249191 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1874723 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 1026 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2123914 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2123914 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 250130 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 170532 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 5594 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses 420662 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 420662 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3306153500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 6559898993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66534000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency 121000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9866052493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9866052493 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199897500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 945697168 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 39145594668 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.028668 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 3343532500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 6556670490 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66421000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency 52000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9900202990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9900202990 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199457500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 947259668 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 39146717168 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.029105 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025634 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025594 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051120 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050792 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000105 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000010 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.027349 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.027572 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.027349 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.027572 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13315.049818 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38407.127635 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11840.896957 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23540.990103 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23540.990103 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13367.179067 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38448.329287 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11873.614587 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 52000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23534.816527 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23534.816527 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 3bb35a882..23340838e 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/chips/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/arm/scratch/sysexplr/dist/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -148,6 +148,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -1300,7 +1301,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-x86.img +image_file=/arm/scratch/sysexplr/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1320,7 +1321,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img +image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 1778e84dc..c0ff48d52 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simout +Redirecting stderr to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 15 2011 11:12:24 -gem5 started Aug 15 2011 11:17:26 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 19:14:00 +gem5 started Aug 17 2011 19:16:38 +gem5 executing on nadc-0388 command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /arm/scratch/sysexplr/dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5151638875500 because m5_exit instruction encountered +Exiting @ tick 5139621012500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 34270b518..74858b319 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,97 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.151639 # Number of seconds simulated -sim_ticks 5151638875500 # Number of ticks simulated +sim_seconds 5.139621 # Number of seconds simulated +sim_ticks 5139621012500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136272 # Simulator instruction rate (inst/s) -host_tick_rate 835912815 # Simulator tick rate (ticks/s) -host_mem_usage 404376 # Number of bytes of host memory used -host_seconds 6162.89 # Real time elapsed on the host -sim_insts 839831731 # Number of instructions simulated -system.l2c.replacements 168782 # number of replacements -system.l2c.tagsinuse 38205.196893 # Cycle average of tags in use -system.l2c.total_refs 3762867 # Total number of references to valid blocks. -system.l2c.sampled_refs 202558 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.576739 # Average number of references to valid blocks. +host_inst_rate 264330 # Simulator instruction rate (inst/s) +host_tick_rate 1617420466 # Simulator tick rate (ticks/s) +host_mem_usage 409996 # Number of bytes of host memory used +host_seconds 3177.67 # Real time elapsed on the host +sim_insts 839951837 # Number of instructions simulated +system.l2c.replacements 170440 # number of replacements +system.l2c.tagsinuse 38394.915319 # Cycle average of tags in use +system.l2c.total_refs 3798996 # Total number of references to valid blocks. +system.l2c.sampled_refs 206462 # Sample count of references to valid blocks. +system.l2c.avg_refs 18.400461 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11735.089031 # Average occupied blocks per context -system.l2c.occ_blocks::1 26470.107863 # Average occupied blocks per context -system.l2c.occ_percent::0 0.179063 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.403902 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2331067 # number of ReadReq hits -system.l2c.ReadReq_hits::1 125887 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2456954 # number of ReadReq hits -system.l2c.Writeback_hits::0 1588356 # number of Writeback hits -system.l2c.Writeback_hits::total 1588356 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 357 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 357 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 150454 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 150454 # number of ReadExReq hits -system.l2c.demand_hits::0 2481521 # number of demand (read+write) hits -system.l2c.demand_hits::1 125887 # number of demand (read+write) hits -system.l2c.demand_hits::total 2607408 # number of demand (read+write) hits -system.l2c.overall_hits::0 2481521 # number of overall hits -system.l2c.overall_hits::1 125887 # number of overall hits -system.l2c.overall_hits::total 2607408 # number of overall hits -system.l2c.ReadReq_misses::0 64696 # number of ReadReq misses -system.l2c.ReadReq_misses::1 91 # number of ReadReq misses -system.l2c.ReadReq_misses::total 64787 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3960 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3960 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 142190 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 142190 # number of ReadExReq misses -system.l2c.demand_misses::0 206886 # number of demand (read+write) misses -system.l2c.demand_misses::1 91 # number of demand (read+write) misses -system.l2c.demand_misses::total 206977 # number of demand (read+write) misses -system.l2c.overall_misses::0 206886 # number of overall misses -system.l2c.overall_misses::1 91 # number of overall misses -system.l2c.overall_misses::total 206977 # number of overall misses -system.l2c.ReadReq_miss_latency 3398610000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 37586500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7439728500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 10838338500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 10838338500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2395763 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 125978 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2521741 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1588356 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1588356 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 4317 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4317 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 292644 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292644 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2688407 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 125978 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2814385 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2688407 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 125978 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2814385 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027004 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000722 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.027727 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.917304 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.485880 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.076955 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000722 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.077677 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.076955 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000722 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.077677 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52531.995796 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 37347362.637363 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 37399894.633158 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 9491.540404 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 11966.871938 # Average occupied blocks per context +system.l2c.occ_blocks::1 26428.043381 # Average occupied blocks per context +system.l2c.occ_percent::0 0.182600 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.403260 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2331798 # number of ReadReq hits +system.l2c.ReadReq_hits::1 145238 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2477036 # number of ReadReq hits +system.l2c.Writeback_hits::0 1588821 # number of Writeback hits +system.l2c.Writeback_hits::total 1588821 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 321 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 321 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 149873 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 149873 # number of ReadExReq hits +system.l2c.demand_hits::0 2481671 # number of demand (read+write) hits +system.l2c.demand_hits::1 145238 # number of demand (read+write) hits +system.l2c.demand_hits::total 2626909 # number of demand (read+write) hits +system.l2c.overall_hits::0 2481671 # number of overall hits +system.l2c.overall_hits::1 145238 # number of overall hits +system.l2c.overall_hits::total 2626909 # number of overall hits +system.l2c.ReadReq_misses::0 68032 # number of ReadReq misses +system.l2c.ReadReq_misses::1 90 # number of ReadReq misses +system.l2c.ReadReq_misses::total 68122 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3926 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3926 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 142738 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 142738 # number of ReadExReq misses +system.l2c.demand_misses::0 210770 # number of demand (read+write) misses +system.l2c.demand_misses::1 90 # number of demand (read+write) misses +system.l2c.demand_misses::total 210860 # number of demand (read+write) misses +system.l2c.overall_misses::0 210770 # number of overall misses +system.l2c.overall_misses::1 90 # number of overall misses +system.l2c.overall_misses::total 210860 # number of overall misses +system.l2c.ReadReq_miss_latency 3572833000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 39364500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7469371500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 11042204500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 11042204500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2399830 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 145328 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2545158 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1588821 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1588821 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 4247 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4247 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 292611 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292611 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2692441 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 145328 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2837769 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2692441 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 145328 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2837769 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.028349 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000619 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028968 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.924417 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.487808 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.078282 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000619 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.078901 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.078282 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000619 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.078901 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52516.947907 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 39698144.444444 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 39750661.392351 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 10026.617422 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52322.445320 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52329.243089 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52387.974537 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 119102620.879121 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 119155008.853658 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52387.974537 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 119102620.879121 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 119155008.853658 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52389.830147 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 122691161.111111 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 122743550.941258 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52389.830147 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 122691161.111111 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 122743550.941258 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -100,88 +100,88 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 142964 # number of writebacks +system.l2c.writebacks 142383 # number of writebacks system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 64785 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3960 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 142190 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 206975 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 206975 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 68120 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3926 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 142738 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 210858 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 210858 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 2608555500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 158748000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5705556000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 8314111500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 8314111500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 61533015500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1222291500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 62755307000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027041 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.514256 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.541298 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.917304 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 2742078500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 157403500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5729564000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 8471642500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 8471642500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 61532429500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1222286000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 62754715500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.028385 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.468733 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.497118 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.924417 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.485880 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.487808 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.076988 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.642946 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.719934 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.076988 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.642946 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.719934 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40264.806668 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40087.878788 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40126.281736 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40169.641261 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40169.641261 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.078315 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.450911 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.529226 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.078315 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.450911 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.529226 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40253.647974 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40092.587876 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40140.425115 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40177.003007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40177.003007 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47575 # number of replacements -system.iocache.tagsinuse 0.165993 # Cycle average of tags in use +system.iocache.replacements 47570 # number of replacements +system.iocache.tagsinuse 0.129176 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994554828000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.165993 # Average occupied blocks per context -system.iocache.occ_percent::1 0.010375 # Average percentage of cache occupancy +system.iocache.warmup_cycle 4994509673000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.129176 # Average occupied blocks per context +system.iocache.occ_percent::1 0.008073 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 909 # number of ReadReq misses -system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.ReadReq_misses::1 905 # number of ReadReq misses +system.iocache.ReadReq_misses::total 905 # number of ReadReq misses system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47629 # number of demand (read+write) misses -system.iocache.demand_misses::total 47629 # number of demand (read+write) misses +system.iocache.demand_misses::1 47625 # number of demand (read+write) misses +system.iocache.demand_misses::total 47625 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47629 # number of overall misses -system.iocache.overall_misses::total 47629 # number of overall misses -system.iocache.ReadReq_miss_latency 113908932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 6372665160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 6486574092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 6486574092 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 909 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.overall_misses::1 47625 # number of overall misses +system.iocache.overall_misses::total 47625 # number of overall misses +system.iocache.ReadReq_miss_latency 113496932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 6374731160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 6488228092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 6488228092 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47629 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 47625 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47629 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 47625 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -191,37 +191,37 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 125312.356436 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 125410.974586 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 136401.223459 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 136445.444349 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 136189.592307 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 136235.760462 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 136189.592307 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 136235.760462 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68832452 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 68743556 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11274 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11268 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6105.415292 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6100.777068 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 46668 # number of writebacks +system.iocache.writebacks 46667 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 905 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 47629 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 47629 # number of overall MSHR misses +system.iocache.demand_mshr_misses 47625 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 47625 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 66617982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3942909802 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 4009527784 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 4009527784 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 66413982 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3944974906 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 4011388888 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 4011388888 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -235,10 +235,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 73287.108911 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 84394.473502 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 84182.489324 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 84182.489324 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 73385.615470 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 84438.675214 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 84228.638068 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 84228.638068 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -255,415 +255,415 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 449440116 # number of cpu cycles simulated +system.cpu.numCycles 449087853 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91251942 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 91251942 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1248755 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 89986362 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 83883414 # Number of BTB hits +system.cpu.BPredUnit.lookups 91217869 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 91217869 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1248400 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 89951778 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 83914735 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28443020 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 451559426 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91251942 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83883414 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 171343402 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6212938 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 155361 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 82525667 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36777 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 48486 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 28382208 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 451447456 # Number of instructions fetch has processed +system.cpu.fetch.Branches 91217869 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83914735 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 171329150 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6161718 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 187674 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 82029365 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36833 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 58090 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 319 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9929678 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 556225 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4240 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 287412747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.086350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.403158 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 9909586 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 559902 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3975 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 286820350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.091965 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.403436 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 116615067 40.57% 40.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1502902 0.52% 41.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72824785 25.34% 66.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1334009 0.46% 66.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1960992 0.68% 67.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4008264 1.39% 68.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1565099 0.54% 69.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2187101 0.76% 70.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85414528 29.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 116059602 40.46% 40.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1498115 0.52% 40.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72812872 25.39% 66.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1272717 0.44% 66.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2053780 0.72% 67.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3977163 1.39% 68.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1588647 0.55% 69.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2196057 0.77% 70.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85361397 29.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 287412747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.203035 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.004715 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33501642 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 78913894 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165819274 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4318222 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4859715 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 883193903 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 620 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4859715 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37708099 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52423571 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10078562 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 165633752 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 16709048 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 878518097 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 13834 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 11653087 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2148761 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 880915046 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1725729327 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1725728311 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1016 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 843223982 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37691057 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 489641 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 492542 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43070507 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19803638 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10755992 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3194647 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3198862 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 871443389 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 900411 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 866326988 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165756 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 31682293 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47289832 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 148825 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 287412747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.014226 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.369116 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 286820350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.203118 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.005254 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33356268 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 78574400 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 165851521 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4241450 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4796711 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 882885518 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 603 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4796711 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37592669 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 52283630 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10046208 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 165609505 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 16491627 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 878188662 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14524 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 11489749 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2124384 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 880584292 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1724975571 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1724975011 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 560 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 843343914 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 37240371 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 491374 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 493473 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42595982 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19743931 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10730204 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1270430 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1078815 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 870972067 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 898477 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 866458351 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 218010 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 31071842 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 45598434 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 144784 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 286820350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.020910 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.373009 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82109167 28.57% 28.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23029898 8.01% 36.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 14429245 5.02% 41.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 9845202 3.43% 45.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 79549613 27.68% 72.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4871174 1.69% 74.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72852960 25.35% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 572992 0.20% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 152496 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82323990 28.70% 28.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22353891 7.79% 36.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 14123864 4.92% 41.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 9769344 3.41% 44.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79473928 27.71% 72.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4992964 1.74% 74.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72968378 25.44% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 634028 0.22% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 179963 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 287412747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 286820350 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 198235 9.39% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1790050 84.77% 94.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 123321 5.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 195550 8.86% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1820080 82.44% 91.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 192012 8.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 300321 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 831068974 95.93% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25494883 2.94% 98.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9462810 1.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 302678 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 830926438 95.90% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25678898 2.96% 98.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9550337 1.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 866326988 # Type of FU issued -system.cpu.iq.rate 1.927569 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2111606 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002437 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2022483969 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 904056296 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 855552025 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 163 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 498 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 60 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 868138190 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 83 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1311048 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 866458351 # Type of FU issued +system.cpu.iq.rate 1.929374 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2207642 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002548 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2022315315 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 902983728 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 855563326 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 258 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 55 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 868363218 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1360799 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4470522 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13972 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 31558 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2334229 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4398376 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17098 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 43182 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2298641 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7818225 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 154758 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7817204 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 161145 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4859715 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33597470 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6022609 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 872343800 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 300494 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19803638 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10756022 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 899609 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5535817 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 26257 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 31558 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 897955 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 529978 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1427933 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 864227296 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25025491 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2099691 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4796711 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33445550 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6029017 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 871870544 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 303715 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19743931 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10730246 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 897675 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5516781 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 26023 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 43182 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 896575 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 530355 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1426930 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 864313806 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25191099 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2144544 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 34264216 # number of memory reference insts executed -system.cpu.iew.exec_branches 86728541 # Number of branches executed -system.cpu.iew.exec_stores 9238725 # Number of stores executed -system.cpu.iew.exec_rate 1.922898 # Inst execution rate -system.cpu.iew.wb_sent 863623792 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 855552085 # cumulative count of insts written-back -system.cpu.iew.wb_producers 671682498 # num instructions producing a value -system.cpu.iew.wb_consumers 1172193952 # num instructions consuming a value +system.cpu.iew.exec_refs 34501157 # number of memory reference insts executed +system.cpu.iew.exec_branches 86709322 # Number of branches executed +system.cpu.iew.exec_stores 9310058 # Number of stores executed +system.cpu.iew.exec_rate 1.924598 # Inst execution rate +system.cpu.iew.wb_sent 863645103 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 855563381 # cumulative count of insts written-back +system.cpu.iew.wb_producers 671472669 # num instructions producing a value +system.cpu.iew.wb_consumers 1171866734 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.903595 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.573013 # average fanout of values written-back +system.cpu.iew.wb_rate 1.905114 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572994 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 839831731 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 32406647 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 751584 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1254294 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 282568841 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.972131 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.859839 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 839951837 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 31810372 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 753691 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1255440 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 282039656 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.978134 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.864065 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102495617 36.27% 36.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13009464 4.60% 40.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4878881 1.73% 42.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76962899 27.24% 69.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4022439 1.42% 71.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1857740 0.66% 71.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1158664 0.41% 72.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71619728 25.35% 97.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6563409 2.32% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 102542445 36.36% 36.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12533027 4.44% 40.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4681692 1.66% 42.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76967359 27.29% 69.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4010237 1.42% 71.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1852910 0.66% 71.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1082027 0.38% 72.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71603983 25.39% 97.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6765976 2.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 282568841 # Number of insts commited each cycle -system.cpu.commit.count 839831731 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 282039656 # Number of insts commited each cycle +system.cpu.commit.count 839951837 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23754906 # Number of memory references committed -system.cpu.commit.loads 15333113 # Number of loads committed +system.cpu.commit.refs 23777157 # Number of memory references committed +system.cpu.commit.loads 15345552 # Number of loads committed system.cpu.commit.membars 801 # Number of memory barriers committed -system.cpu.commit.branches 85519800 # Number of branches committed +system.cpu.commit.branches 85535847 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768449243 # Number of committed integer instructions. +system.cpu.commit.int_insts 768568499 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6563409 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6765976 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1148162427 # The number of ROB reads -system.cpu.rob.rob_writes 1749350545 # The number of ROB writes -system.cpu.timesIdled 3069835 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 162027369 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 839831731 # Number of Instructions Simulated -system.cpu.committedInsts_total 839831731 # Number of Instructions Simulated -system.cpu.cpi 0.535155 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.535155 # CPI: Total CPI of All Threads -system.cpu.ipc 1.868618 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.868618 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1406651660 # number of integer regfile reads -system.cpu.int_regfile_writes 857603051 # number of integer regfile writes -system.cpu.fp_regfile_reads 60 # number of floating regfile reads -system.cpu.misc_regfile_reads 282221875 # number of misc regfile reads -system.cpu.misc_regfile_writes 407507 # number of misc regfile writes -system.cpu.icache.replacements 1029232 # number of replacements -system.cpu.icache.tagsinuse 510.471706 # Cycle average of tags in use -system.cpu.icache.total_refs 8833811 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1029744 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.578648 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 54597932000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.471706 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.997015 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8833811 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8833811 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8833811 # number of demand (read+write) hits +system.cpu.rob.rob_reads 1146952939 # The number of ROB reads +system.cpu.rob.rob_writes 1748336346 # The number of ROB writes +system.cpu.timesIdled 3079654 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 162267503 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 839951837 # Number of Instructions Simulated +system.cpu.committedInsts_total 839951837 # Number of Instructions Simulated +system.cpu.cpi 0.534659 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.534659 # CPI: Total CPI of All Threads +system.cpu.ipc 1.870351 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.870351 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1407338355 # number of integer regfile reads +system.cpu.int_regfile_writes 857621513 # number of integer regfile writes +system.cpu.fp_regfile_reads 55 # number of floating regfile reads +system.cpu.misc_regfile_reads 282388563 # number of misc regfile reads +system.cpu.misc_regfile_writes 410581 # number of misc regfile writes +system.cpu.icache.replacements 1030220 # number of replacements +system.cpu.icache.tagsinuse 510.462524 # Cycle average of tags in use +system.cpu.icache.total_refs 8809167 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1030732 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.546515 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 54553868000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.462524 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.996997 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8809167 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8809167 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8809167 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8833811 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8833811 # number of overall hits +system.cpu.icache.demand_hits::total 8809167 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8809167 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8833811 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1095865 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1095865 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1095865 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8809167 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1100416 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1100416 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1100416 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1095865 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1095865 # number of overall misses +system.cpu.icache.demand_misses::total 1100416 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1100416 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1095865 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16411974488 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16411974488 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16411974488 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9929676 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9929676 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9929676 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1100416 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 16477170489 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 16477170489 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 16477170489 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9909583 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9909583 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9909583 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9929676 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9929676 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9909583 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9909583 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9929676 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.110363 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.110363 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9909583 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.111046 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.111046 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.110363 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.111046 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14976.273983 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14973.583162 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14976.273983 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14973.583162 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14976.273983 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14973.583162 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2523491 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2487991 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 250 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 243 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10093.964000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10238.646091 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 1562 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 63554 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 63554 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 63554 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1032311 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1032311 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1032311 # number of overall MSHR misses +system.cpu.icache.writebacks 1561 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 67148 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 67148 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 67148 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1033268 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1033268 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1033268 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12460934991 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12460934991 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12460934991 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12490519491 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12490519491 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12490519491 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.103962 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.104270 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.103962 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.104270 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.103962 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.104270 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12070.911761 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12070.911761 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12070.911761 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12088.363804 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12088.363804 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12088.363804 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 11904 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.021281 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 25742 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 11916 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.160289 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5113551809500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::1 6.021281 # Average occupied blocks per context -system.cpu.itb_walker_cache.occ_percent::1 0.376330 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::1 25787 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25787 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 13461 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 5.999270 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 28519 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 13469 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.117381 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5126859452000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::1 5.999270 # Average occupied blocks per context +system.cpu.itb_walker_cache.occ_percent::1 0.374954 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::1 28575 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 28575 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::1 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::1 25790 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25790 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::1 28578 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 28578 # number of demand (read+write) hits system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::1 25790 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25790 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::1 12756 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 12756 # number of ReadReq misses +system.cpu.itb_walker_cache.overall_hits::1 28578 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 28578 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 14318 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 14318 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 12756 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 12756 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 14318 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 14318 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 12756 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 12756 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency 165450000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency 165450000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency 165450000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 38543 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 38543 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.overall_misses::1 14318 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 14318 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency 183495000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency 183495000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency 183495000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::1 42893 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 42893 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 38546 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 38546 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 42896 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 42896 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 38546 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 38546 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.330955 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.overall_accesses::1 42896 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 42896 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.333807 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.330929 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.333784 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.330929 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.333784 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12970.366886 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12815.686548 # average ReadReq miss latency system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12970.366886 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12815.686548 # average overall miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12970.366886 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12815.686548 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -673,83 +673,83 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 2156 # number of writebacks +system.cpu.itb_walker_cache.writebacks 2322 # number of writebacks system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.itb_walker_cache.ReadReq_mshr_misses 12756 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses 12756 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses 12756 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses 14318 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses 14318 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses 14318 # number of overall MSHR misses system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 126704000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency 126704000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency 126704000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 140154000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency 140154000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency 140154000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.330955 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.333807 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.330929 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.333784 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.330929 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.333784 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9932.894324 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9932.894324 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9932.894324 # average overall mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9788.657634 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9788.657634 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9788.657634 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 123389 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.858352 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 128795 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 123405 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.043677 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101298251000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 13.858352 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.866147 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 128795 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 128795 # number of ReadReq hits +system.cpu.dtb_walker_cache.replacements 143345 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.852844 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 148404 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 143358 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.035199 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5098934943000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 13.852844 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.865803 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 148429 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 148429 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 128795 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 128795 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 148429 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 148429 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 128795 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 128795 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 124284 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 124284 # number of ReadReq misses +system.cpu.dtb_walker_cache.overall_hits::1 148429 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 148429 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 144294 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 144294 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 124284 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 124284 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 144294 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 144294 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 124284 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 124284 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency 1723739000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency 1723739000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency 1723739000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 253079 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 253079 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.overall_misses::1 144294 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 144294 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency 1999592000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency 1999592000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency 1999592000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::1 292723 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 292723 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 253079 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 253079 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 292723 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 292723 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 253079 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 253079 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.491088 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.overall_accesses::1 292723 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 292723 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.492937 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.491088 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.492937 # miss rate for demand accesses system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.491088 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.492937 # miss rate for overall accesses system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13869.355669 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13857.762624 # average ReadReq miss latency system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13869.355669 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13857.762624 # average overall miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13869.355669 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13857.762624 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -759,136 +759,136 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 38359 # number of writebacks +system.cpu.dtb_walker_cache.writebacks 36787 # number of writebacks system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.ReadReq_mshr_misses 124284 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses 124284 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses 124284 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses 144294 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses 144294 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses 144294 # number of overall MSHR misses system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1347076500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1347076500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1347076500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1562734500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1562734500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1562734500 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.491088 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.492937 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.491088 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.492937 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.491088 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.492937 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10838.696051 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10838.696051 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10838.696051 # average overall mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10830.211235 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10830.211235 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10830.211235 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1658768 # number of replacements -system.cpu.dcache.tagsinuse 511.997453 # Cycle average of tags in use -system.cpu.dcache.total_refs 17937343 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1659280 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.810317 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1661784 # number of replacements +system.cpu.dcache.tagsinuse 511.998465 # Cycle average of tags in use +system.cpu.dcache.total_refs 18023326 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1662296 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.842429 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 13135000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.997453 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 11377605 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11377605 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 6537446 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6537446 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 17915051 # number of demand (read+write) hits +system.cpu.dcache.occ_blocks::0 511.998465 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999997 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 11452816 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11452816 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 6548488 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6548488 # number of WriteReq hits +system.cpu.dcache.demand_hits::0 18001304 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 17915051 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 17915051 # number of overall hits +system.cpu.dcache.demand_hits::total 18001304 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 18001304 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 17915051 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 2443873 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2443873 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1875033 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1875033 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 4318906 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 18001304 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 2480783 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2480783 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1873809 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1873809 # number of WriteReq misses +system.cpu.dcache.demand_misses::0 4354592 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4318906 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 4318906 # number of overall misses +system.cpu.dcache.demand_misses::total 4354592 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 4354592 # 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number of overall misses +system.cpu.dcache.ReadReq_miss_latency 37442770000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 63502469838 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 100945239838 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 100945239838 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13933599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13933599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8422297 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8422297 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 22355896 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22233957 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 22233957 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 22355896 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 22355896 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22233957 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.176817 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.222887 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.194248 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 22355896 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.178043 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.222482 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.194785 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.194248 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.194785 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15015.335494 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15093.125840 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 33600.571579 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33889.510531 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 23084.029504 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 23181.331302 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 23084.029504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 23181.331302 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1066704607 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6645500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 69708 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 391 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15302.470405 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16996.163683 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1084772653 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6673000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73247 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 392 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14809.789520 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17022.959184 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1546279 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1076649 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1578166 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2654815 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2654815 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1367224 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 296867 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1664091 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1664091 # number of overall MSHR misses +system.cpu.dcache.writebacks 1548151 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1110544 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1577040 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2687584 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2687584 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1370239 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 296769 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1667008 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1667008 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 18012012500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 9730106607 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 27742119107 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 27742119107 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86947466500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1385748000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 88333214500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098920 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 18185435000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 9767723153 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 27953158153 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 27953158153 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86946921000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1385819000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 88332740000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098341 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035289 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035236 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.074845 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.074567 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.074845 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.074567 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13174.148859 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32775.979166 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16671.034882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16671.034882 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13271.724860 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32913.556177 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16768.460711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16768.460711 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency |