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-rw-r--r--tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt18
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 389bae1e3..6b71bf251 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 492863 # Simulator instruction rate (inst/s)
-host_mem_usage 387392 # Number of bytes of host memory used
-host_seconds 185.09 # Real time elapsed on the host
-host_tick_rate 800055292 # Simulator tick rate (ticks/s)
+host_inst_rate 2007081 # Simulator instruction rate (inst/s)
+host_mem_usage 346528 # Number of bytes of host memory used
+host_seconds 45.45 # Real time elapsed on the host
+host_tick_rate 3258049978 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91226321 # Number of instructions simulated
sim_seconds 0.148086 # Number of seconds simulated
@@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 946798 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.871228 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3568.549501 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.871228 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 27284389 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14657.859438 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency
@@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 599 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.249187 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 510.335448 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.249187 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 107830780 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 54527.545910 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
@@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 15408 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.009921 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.271918 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 325.097811 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8910.209882 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.009921 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.271918 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 947397 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
@@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 70993656 # nu
system.cpu.num_load_insts 22573967 # Number of load instructions
system.cpu.num_mem_refs 27318811 # number of memory refs
system.cpu.num_store_insts 4744844 # Number of store instructions
-system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
+system.cpu.workload.num_syscalls 442 # Number of system calls
---------- End Simulation Statistics ----------