diff options
Diffstat (limited to 'tests/long/10.mcf/ref/arm')
| -rwxr-xr-x | tests/long/10.mcf/ref/arm/linux/o3-timing/simout | 6 | ||||
| -rw-r--r-- | tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt | 783 |
2 files changed, 391 insertions, 398 deletions
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index 4a81b3d8f..c90ea128a 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:18:43 -gem5 started Jul 9 2011 01:04:44 +gem5 compiled Jul 15 2011 18:02:03 +gem5 started Jul 16 2011 01:23:12 gem5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 33955329500 because target called exit() +Exiting @ tick 34059187000 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index cba4db906..4687ee8e5 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033955 # Number of seconds simulated -sim_ticks 33955329500 # Number of ticks simulated +sim_seconds 0.034059 # Number of seconds simulated +sim_ticks 34059187000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64380 # Simulator instruction rate (inst/s) -host_tick_rate 23956859 # Simulator tick rate (ticks/s) -host_mem_usage 390580 # Number of bytes of host memory used -host_seconds 1417.35 # Real time elapsed on the host -sim_insts 91249680 # Number of instructions simulated +host_inst_rate 66126 # Simulator instruction rate (inst/s) +host_tick_rate 24681632 # Simulator tick rate (ticks/s) +host_mem_usage 390692 # Number of bytes of host memory used +host_seconds 1379.94 # Real time elapsed on the host +sim_insts 91249685 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,300 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 67910660 # number of cpu cycles simulated +system.cpu.numCycles 68118375 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 28244508 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22629080 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1414299 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25112752 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24086234 # Number of BTB hits +system.cpu.BPredUnit.lookups 28264225 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22664811 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1422221 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25307717 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24243974 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 121674 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 12927 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 16032012 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 135606393 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28244508 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24207908 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 33529641 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6010411 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 13862842 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 113570 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 12949 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 16006756 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 135411326 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28264225 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24357544 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 33580343 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5963217 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 14095577 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 15326942 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 412294 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 67880028 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.019137 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.751435 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 149 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 15302646 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 409174 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 68087836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.009786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.740415 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 34404593 50.68% 50.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6761573 9.96% 60.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5940167 8.75% 69.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4952932 7.30% 76.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2875416 4.24% 80.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1738729 2.56% 83.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1585314 2.34% 85.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3119241 4.60% 90.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6502063 9.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 34562720 50.76% 50.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6711035 9.86% 60.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6005592 8.82% 69.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5006532 7.35% 76.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2908486 4.27% 81.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1809535 2.66% 83.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1604855 2.36% 86.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3043201 4.47% 90.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6435880 9.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 67880028 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.415907 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.996835 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 18687820 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12370381 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31414917 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 983964 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4422946 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4499724 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 32863 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 133147735 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31368 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4422946 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20483676 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 968140 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8316666 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 30556439 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3132161 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128513000 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 288426 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1795950 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 14 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 149798068 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 559931036 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 559926436 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4600 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429111 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 42368952 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 668763 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 669407 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 7564309 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30008124 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6129267 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1456420 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 516652 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 120184129 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 637684 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107766890 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 87998 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 29120799 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 70180475 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 83323 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 67880028 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.587608 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.759573 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 68087836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.414928 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.987883 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 18687372 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12574245 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31471424 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 979506 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4375289 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4503619 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 30122 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132907777 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31137 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4375289 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20501176 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1029913 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8340304 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 30584541 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3256613 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128189435 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 288306 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1934414 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 17 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 149540723 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 558211899 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 558194258 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17641 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429119 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 42111599 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 671866 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 673475 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 7619625 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29869898 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6025284 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1488843 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 609505 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 119834900 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 639591 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107581328 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 88511 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 28762009 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 69412751 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 85229 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 68087836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.580037 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.751787 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25488891 37.55% 37.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14322408 21.10% 58.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10131350 14.93% 73.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 8118242 11.96% 85.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4318324 6.36% 91.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2337223 3.44% 95.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2482658 3.66% 99.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 475759 0.70% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 205173 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25433380 37.35% 37.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14679481 21.56% 58.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10190142 14.97% 73.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 8113823 11.92% 85.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4222569 6.20% 92.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2284074 3.35% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2481556 3.64% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 482376 0.71% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 200435 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 67880028 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 68087836 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57394 10.75% 10.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.01% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 196663 36.84% 47.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 279761 52.40% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 54498 10.46% 10.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.01% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191599 36.78% 47.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 274842 52.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 75833735 70.37% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10982 0.01% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 110 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 182 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26490777 24.58% 94.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5431101 5.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 75715085 70.38% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10984 0.01% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 147 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26496641 24.63% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5358008 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107766890 # Type of FU issued -system.cpu.iq.rate 1.586892 # Inst issue rate -system.cpu.iq.fu_busy_cnt 533845 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.004954 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 284035005 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 150060826 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 103585232 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 646 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 916 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 298 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 108300410 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 325 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 363305 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107581328 # Type of FU issued +system.cpu.iq.rate 1.579329 # Inst issue rate +system.cpu.iq.fu_busy_cnt 520966 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.004843 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 283858560 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 149349424 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 103392608 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1409 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1914 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 392 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 108101654 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 640 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 354645 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7432292 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 39631 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 124361 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1382559 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7294065 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41309 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 115131 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1278575 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30723 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 30521 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4422946 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 101110 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18559 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 120860696 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 802315 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30008124 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6129267 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 632825 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10731 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 224 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 124361 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1290705 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 209600 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1500305 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 105816782 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 26069680 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1950108 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4375289 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 100045 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 19331 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 120513426 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 799995 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29869898 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6025284 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 634734 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 10994 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1046 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 115131 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1306667 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 208134 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1514801 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 105623962 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 26069380 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1957366 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 38883 # number of nop insts executed -system.cpu.iew.exec_refs 31358457 # number of memory reference insts executed -system.cpu.iew.exec_branches 21276544 # Number of branches executed -system.cpu.iew.exec_stores 5288777 # Number of stores executed -system.cpu.iew.exec_rate 1.558176 # Inst execution rate -system.cpu.iew.wb_sent 104017986 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 103585530 # cumulative count of insts written-back -system.cpu.iew.wb_producers 60888984 # num instructions producing a value -system.cpu.iew.wb_consumers 97986900 # num instructions consuming a value +system.cpu.iew.exec_nop 38935 # number of nop insts executed +system.cpu.iew.exec_refs 31285154 # number of memory reference insts executed +system.cpu.iew.exec_branches 21282801 # Number of branches executed +system.cpu.iew.exec_stores 5215774 # Number of stores executed +system.cpu.iew.exec_rate 1.550594 # Inst execution rate +system.cpu.iew.wb_sent 103821828 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 103393000 # cumulative count of insts written-back +system.cpu.iew.wb_producers 60779146 # num instructions producing a value +system.cpu.iew.wb_consumers 97604196 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.525321 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.621399 # average fanout of values written-back +system.cpu.iew.wb_rate 1.517843 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.622710 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 91262289 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 29597995 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 554361 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1394652 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 63457083 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.438173 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.204542 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 91262294 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 29250695 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 554362 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1405283 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 63712548 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.432407 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.197517 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 29495808 46.48% 46.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16759375 26.41% 72.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5313552 8.37% 81.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4030004 6.35% 87.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1955590 3.08% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 709900 1.12% 91.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 461456 0.73% 92.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 205982 0.32% 92.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4525416 7.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 29657705 46.55% 46.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16839810 26.43% 72.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5318691 8.35% 81.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3965283 6.22% 87.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2147247 3.37% 90.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 617953 0.97% 91.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 460758 0.72% 92.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 194856 0.31% 92.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4510245 7.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 63457083 # Number of insts commited each cycle -system.cpu.commit.count 91262289 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 63712548 # Number of insts commited each cycle +system.cpu.commit.count 91262294 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322539 # Number of memory references committed -system.cpu.commit.loads 22575831 # Number of loads committed +system.cpu.commit.refs 27322541 # Number of memory references committed +system.cpu.commit.loads 22575832 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722425 # Number of branches committed +system.cpu.commit.branches 18722426 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533138 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533142 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4525416 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4510245 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 179786217 # The number of ROB reads -system.cpu.rob.rob_writes 246157217 # The number of ROB writes -system.cpu.timesIdled 1527 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30632 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 91249680 # Number of Instructions Simulated -system.cpu.committedInsts_total 91249680 # Number of Instructions Simulated -system.cpu.cpi 0.744229 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.744229 # CPI: Total CPI of All Threads -system.cpu.ipc 1.343672 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.343672 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 502577811 # number of integer regfile reads -system.cpu.int_regfile_writes 122258624 # number of integer regfile writes -system.cpu.fp_regfile_reads 150 # number of floating regfile reads -system.cpu.fp_regfile_writes 373 # number of floating regfile writes -system.cpu.misc_regfile_reads 189862426 # number of misc regfile reads -system.cpu.misc_regfile_writes 11512 # number of misc regfile writes +system.cpu.rob.rob_reads 179709558 # The number of ROB reads +system.cpu.rob.rob_writes 245415120 # The number of ROB writes +system.cpu.timesIdled 1511 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30539 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 91249685 # Number of Instructions Simulated +system.cpu.committedInsts_total 91249685 # Number of Instructions Simulated +system.cpu.cpi 0.746505 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.746505 # CPI: Total CPI of All Threads +system.cpu.ipc 1.339575 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.339575 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 501634552 # number of integer regfile reads +system.cpu.int_regfile_writes 122095043 # number of integer regfile writes +system.cpu.fp_regfile_reads 176 # number of floating regfile reads +system.cpu.fp_regfile_writes 493 # number of floating regfile writes +system.cpu.misc_regfile_reads 189665669 # number of misc regfile reads +system.cpu.misc_regfile_writes 11514 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 615.328313 # Cycle average of tags in use -system.cpu.icache.total_refs 15326008 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 726 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 21110.203857 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 611.147709 # Cycle average of tags in use +system.cpu.icache.total_refs 15301726 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 719 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 21281.955494 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 615.328313 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.300453 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 15326008 # number of ReadReq hits -system.cpu.icache.demand_hits 15326008 # number of demand (read+write) hits -system.cpu.icache.overall_hits 15326008 # number of overall hits -system.cpu.icache.ReadReq_misses 934 # number of ReadReq misses -system.cpu.icache.demand_misses 934 # number of demand (read+write) misses -system.cpu.icache.overall_misses 934 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 32832500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 32832500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 32832500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 15326942 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 15326942 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 15326942 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35152.569593 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35152.569593 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35152.569593 # average overall miss latency +system.cpu.icache.occ_blocks::0 611.147709 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.298412 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 15301726 # number of ReadReq hits +system.cpu.icache.demand_hits 15301726 # number of demand (read+write) hits +system.cpu.icache.overall_hits 15301726 # number of overall hits +system.cpu.icache.ReadReq_misses 920 # number of ReadReq misses +system.cpu.icache.demand_misses 920 # number of demand (read+write) misses +system.cpu.icache.overall_misses 920 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 32420000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 32420000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 32420000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 15302646 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 15302646 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 15302646 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000060 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000060 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000060 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35239.130435 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35239.130435 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35239.130435 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,142 +354,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 207 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 207 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 207 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 727 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 727 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 727 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 201 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 201 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 201 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 719 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 719 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 719 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 25012500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 25012500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 25012500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 24811500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 24811500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 24811500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000047 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000047 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000047 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34405.089409 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34405.089409 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34405.089409 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34508.344924 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34508.344924 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34508.344924 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943475 # number of replacements -system.cpu.dcache.tagsinuse 3548.617037 # Cycle average of tags in use -system.cpu.dcache.total_refs 29160006 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947571 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 30.773426 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12936791000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3548.617037 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.866362 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 24566182 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 4581344 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 6728 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 5751 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 29147526 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 29147526 # number of overall hits -system.cpu.dcache.ReadReq_misses 998551 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 153637 # number of WriteReq misses +system.cpu.dcache.replacements 943449 # number of replacements +system.cpu.dcache.tagsinuse 3548.737651 # Cycle average of tags in use +system.cpu.dcache.total_refs 29169762 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947545 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 30.784566 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12973953000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 3548.737651 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.866391 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 24598373 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 4558911 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 6726 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 5752 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 29157284 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 29157284 # number of overall hits +system.cpu.dcache.ReadReq_misses 981426 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 176070 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1152188 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1152188 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5569139000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4384723397 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 126500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 9953862397 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9953862397 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 25564733 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 1157496 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1157496 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5458949500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4506223422 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 124500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 9965172922 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 9965172922 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 25579799 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 6735 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 5751 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30299714 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30299714 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.039060 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.032447 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.001039 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.038026 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.038026 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 5577.220392 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 28539.501533 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 18071.428571 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 8639.095701 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 8639.095701 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23292477 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses 6733 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 5752 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 30314780 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 30314780 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.038367 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.037185 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.001040 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.038183 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.038183 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 5562.262972 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 25593.362992 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 8609.250418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 8609.250418 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23278498 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8136 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8128 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2862.890487 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2863.988435 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 942916 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 85616 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 119000 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 942894 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 79978 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 129972 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 204616 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 204616 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 912935 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 34637 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 947572 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 947572 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 209950 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 209950 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 901448 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 46098 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 947546 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 947546 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2294888500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1057301024 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3352189524 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3352189524 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2249272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1085068550 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3334340550 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3334340550 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.035711 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.007315 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.031273 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.031273 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2513.747967 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30525.190519 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3537.662071 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3537.662071 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.035241 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009736 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.031257 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.031257 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2495.176649 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23538.299926 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3518.922089 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3518.922089 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 747 # number of replacements -system.cpu.l2cache.tagsinuse 9154.979721 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1625557 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15570 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 104.403147 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 744 # number of replacements +system.cpu.l2cache.tagsinuse 9122.566359 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1596024 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15565 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 102.539287 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 397.893639 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8757.086082 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.012143 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.267245 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 912568 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 942916 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 20133 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 932701 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 932701 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1056 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses +system.cpu.l2cache.occ_blocks::0 396.658867 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 8725.907492 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.012105 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.266294 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 901114 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 942894 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 31559 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 932673 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 932673 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1052 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 14540 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 15596 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 15596 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 36204000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 498983500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 535187500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 535187500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 913624 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 942916 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 34673 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 948297 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 948297 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.001156 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.419346 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.016446 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.016446 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34284.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34317.984869 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34315.689920 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34315.689920 # average overall miss latency +system.cpu.l2cache.demand_misses 15592 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 15592 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 36036000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 498937500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 534973500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 534973500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 902166 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 942894 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 46099 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 948265 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 948265 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.001166 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.315408 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.016443 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.016443 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34254.752852 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34314.821183 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34310.768343 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34310.768343 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,28 +499,24 @@ system.cpu.l2cache.writebacks 32 # nu system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1046 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 1042 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 14540 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 15586 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 15586 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 15582 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 15582 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 32557500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 451767000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 484324500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 484324500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 32402000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 451783000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 484185000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 484185000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001145 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.419346 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.016436 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.016436 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31125.717017 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31070.632737 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31074.329526 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31074.329526 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001155 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.315408 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.016432 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.016432 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31095.969290 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31071.733150 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31073.353870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31073.353870 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |