diff options
Diffstat (limited to 'tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index ac46d4baa..61025e455 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1327795 # Simulator instruction rate (inst/s) -host_mem_usage 337424 # Number of bytes of host memory used -host_seconds 183.64 # Real time elapsed on the host -host_tick_rate 1995461602 # Simulator tick rate (ticks/s) +host_inst_rate 712663 # Simulator instruction rate (inst/s) +host_mem_usage 336988 # Number of bytes of host memory used +host_seconds 342.15 # Real time elapsed on the host +host_tick_rate 1070988197 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated -sim_seconds 0.366446 # Number of seconds simulated -sim_ticks 366445521000 # Number of ticks simulated +sim_seconds 0.366435 # Number of seconds simulated +sim_ticks 366435406000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency @@ -77,14 +77,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 935475 # number of replacements system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3569.547350 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3569.622607 # Cycle average of tags in use system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134389803000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 134379688000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 94875 # number of writebacks -system.cpu.icache.ReadReq_accesses 244431627 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 244430745 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 244420630 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 49308000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses @@ -93,16 +93,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # ms system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 277132.363946 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 244431627 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55904.761905 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency -system.cpu.icache.demand_hits 244430745 # number of demand (read+write) hits +system.cpu.icache.demand_hits 244420630 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 49308000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses system.cpu.icache.demand_misses 882 # number of demand (read+write) misses @@ -113,11 +113,11 @@ system.cpu.icache.demand_mshr_misses 882 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 244431627 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 244430745 # number of overall hits +system.cpu.icache.overall_hits 244420630 # number of overall hits system.cpu.icache.overall_miss_latency 49308000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses system.cpu.icache.overall_misses 882 # number of overall misses @@ -130,8 +130,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 25 # number of replacements system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 726.233997 # Cycle average of tags in use -system.cpu.icache.total_refs 244430745 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 726.242454 # Cycle average of tags in use +system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -204,12 +204,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 891 # number of replacements system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8958.603097 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 8958.837724 # Cycle average of tags in use system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 41 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 732891042 # number of cpu cycles simulated +system.cpu.numCycles 732870812 # number of cpu cycles simulated system.cpu.num_insts 243835278 # Number of instructions executed system.cpu.num_refs 105711442 # Number of memory references system.cpu.workload.PROG:num_syscalls 443 # Number of system calls |