diff options
Diffstat (limited to 'tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 1b0d7fe21..3eb9bf1a6 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 483058 # Simulator instruction rate (inst/s) -host_mem_usage 359588 # Number of bytes of host memory used -host_seconds 504.77 # Real time elapsed on the host -host_tick_rate 718005180 # Simulator tick rate (ticks/s) +host_inst_rate 2305909 # Simulator instruction rate (inst/s) +host_mem_usage 337512 # Number of bytes of host memory used +host_seconds 105.74 # Real time elapsed on the host +host_tick_rate 3427441926 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.362431 # Number of seconds simulated @@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses 939567 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.870074 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 3563.824259 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.870074 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 14660.150899 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency @@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 882 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.354281 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 725.567632 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.354281 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55857.142857 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency @@ -183,10 +183,10 @@ system.cpu.l2cache.demand_mshr_misses 15648 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.011460 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.270424 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 375.506440 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 8861.245791 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.011460 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.270424 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -228,6 +228,6 @@ system.cpu.num_int_register_writes 215451608 # nu system.cpu.num_load_insts 82803522 # Number of load instructions system.cpu.num_mem_refs 105711442 # number of memory refs system.cpu.num_store_insts 22907920 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 443 # Number of system calls +system.cpu.workload.num_syscalls 443 # Number of system calls ---------- End Simulation Statistics ---------- |