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-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini102
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out999
-rwxr-xr-xtests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr2
-rwxr-xr-xtests/long/10.mcf/ref/sparc/linux/simple-atomic/simout26
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt45
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini205
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out999
-rwxr-xr-xtests/long/10.mcf/ref/sparc/linux/simple-timing/simerr2
-rwxr-xr-xtests/long/10.mcf/ref/sparc/linux/simple-timing/simout26
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt244
10 files changed, 0 insertions, 2650 deletions
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
deleted file mode 100644
index 77055bd16..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ /dev/null
@@ -1,102 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[0]
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb itb tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
-
-[system.cpu.dtb]
-type=SparcTLB
-size=64
-
-[system.cpu.itb]
-type=SparcTLB
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
-gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:268435455
-zero=false
-port=system.membus.port[1]
-
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
deleted file mode 100644
index 095132477..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
+++ /dev/null
@@ -1,999 +0,0 @@
-()
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diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr
deleted file mode 100755
index e45cd058f..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr
+++ /dev/null
@@ -1,2 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
deleted file mode 100755
index 18a19b6d7..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ /dev/null
@@ -1,26 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:20:13
-gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-MCF SPEC version 1.6.I
-by Andreas Loebel
-Copyright (c) 1998,1999 ZIB Berlin
-All Rights Reserved.
-
-nodes : 500
-active arcs : 1905
-simplex iterations : 1502
-flow value : 4990014995
-new implicit arcs : 23867
-active arcs : 25772
-simplex iterations : 2663
-flow value : 3080014995
-checksum : 68389
-optimal
-Exiting @ tick 122215830000 because target called exit()
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
deleted file mode 100644
index e3ffceab4..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.122216 # Number of seconds simulated
-sim_ticks 122215830000 # Number of ticks simulated
-final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3409932 # Simulator instruction rate (inst/s)
-host_tick_rate 1709135687 # Simulator tick rate (ticks/s)
-host_mem_usage 338176 # Number of bytes of host memory used
-host_seconds 71.51 # Real time elapsed on the host
-sim_insts 243835278 # Number of instructions simulated
-system.physmem.bytes_read 1306360053 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 977686044 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 91606089 # Number of bytes written to this memory
-system.physmem.num_reads 326641945 # Number of read requests responded to by this memory
-system.physmem.num_writes 22901951 # Number of write requests responded to by this memory
-system.physmem.num_other 3886 # Number of other requests responded to by this memory
-system.physmem.bw_read 10688959466 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 7999667834 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 749543566 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 11438503032 # Total bandwidth to/from this memory (bytes/s)
-system.cpu.workload.num_syscalls 443 # Number of system calls
-system.cpu.numCycles 244431661 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 243835278 # Number of instructions executed
-system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
-system.cpu.num_func_calls 4252956 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls
-system.cpu.num_int_insts 194726506 # number of integer instructions
-system.cpu.num_fp_insts 11630 # number of float instructions
-system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read
-system.cpu.num_int_register_writes 215451567 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
-system.cpu.num_mem_refs 105711442 # number of memory refs
-system.cpu.num_load_insts 82803522 # Number of load instructions
-system.cpu.num_store_insts 22907920 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 244431661 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-
----------- End Simulation Statistics ----------
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
deleted file mode 100644
index acd41b2d5..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ /dev/null
@@ -1,205 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[0]
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=262144
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.dtb]
-type=SparcTLB
-size=64
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=131072
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.itb]
-type=SparcTLB
-size=64
-
-[system.cpu.l2cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=2097152
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
-
-[system.cpu.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
-gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:268435455
-zero=false
-port=system.membus.port[1]
-
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out
deleted file mode 100644
index 095132477..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out
+++ /dev/null
@@ -1,999 +0,0 @@
-()
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diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr
deleted file mode 100755
index e45cd058f..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr
+++ /dev/null
@@ -1,2 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
deleted file mode 100755
index ca44a686d..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
+++ /dev/null
@@ -1,26 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:21:35
-gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-MCF SPEC version 1.6.I
-by Andreas Loebel
-Copyright (c) 1998,1999 ZIB Berlin
-All Rights Reserved.
-
-nodes : 500
-active arcs : 1905
-simplex iterations : 1502
-flow value : 4990014995
-new implicit arcs : 23867
-active arcs : 25772
-simplex iterations : 2663
-flow value : 3080014995
-checksum : 68389
-optimal
-Exiting @ tick 362430887000 because target called exit()
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
deleted file mode 100644
index 7dc591cfe..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ /dev/null
@@ -1,244 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.362431 # Number of seconds simulated
-sim_ticks 362430887000 # Number of ticks simulated
-final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1587659 # Simulator instruction rate (inst/s)
-host_tick_rate 2359857170 # Simulator tick rate (ticks/s)
-host_mem_usage 346888 # Number of bytes of host memory used
-host_seconds 153.58 # Real time elapsed on the host
-sim_insts 243835278 # Number of instructions simulated
-system.physmem.bytes_read 1001472 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 2560 # Number of bytes written to this memory
-system.physmem.num_reads 15648 # Number of read requests responded to by this memory
-system.physmem.num_writes 40 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 2763208 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 155219 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 7063 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 2770272 # Total bandwidth to/from this memory (bytes/s)
-system.cpu.workload.num_syscalls 443 # Number of system calls
-system.cpu.numCycles 724861774 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 243835278 # Number of instructions executed
-system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
-system.cpu.num_func_calls 4252956 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls
-system.cpu.num_int_insts 194726506 # number of integer instructions
-system.cpu.num_fp_insts 11630 # number of float instructions
-system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read
-system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
-system.cpu.num_mem_refs 105711442 # number of memory refs
-system.cpu.num_load_insts 82803522 # Number of load instructions
-system.cpu.num_store_insts 22907920 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 724861774 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.icache.replacements 25 # number of replacements
-system.cpu.icache.tagsinuse 725.567632 # Cycle average of tags in use
-system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 725.567632 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.354281 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 244420630 # number of ReadReq hits
-system.cpu.icache.demand_hits 244420630 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 244420630 # number of overall hits
-system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses
-system.cpu.icache.demand_misses 882 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 882 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 49266000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 49266000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 49266000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55857.142857 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55857.142857 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55857.142857 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 46620000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 46620000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 46620000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52857.142857 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 935475 # number of replacements
-system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use
-system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 3563.824259 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.870074 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 22855241 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits 3882 # number of SwapReq hits
-system.cpu.dcache.demand_hits 104182818 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 104182818 # number of overall hits
-system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 46710 # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses 4 # number of SwapReq misses
-system.cpu.dcache.demand_misses 939567 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 939567 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 12508482000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 1265712000 # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency 98000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency 13774194000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 13774194000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.002040 # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate 0.001029 # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate 0.008938 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.008938 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14009.502082 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 27097.238279 # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency 24500 # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 14660.150899 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 14660.150899 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 935237 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 46710 # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses 4 # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 939567 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 939567 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 9829911000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 1125582000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency 86000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 10955493000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 10955493000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.002040 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.001029 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.008938 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.008938 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.502082 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24097.238279 # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 21500 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 865 # number of replacements
-system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1585884 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 375.506440 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 8861.245791 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.011460 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.270424 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 892658 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 935237 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 32147 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 924805 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 924805 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 1081 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 14567 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 15648 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 15648 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 56212000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 757484000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 813696000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 813696000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 935237 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.001210 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.311834 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.016639 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.016639 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 40 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 1081 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 14567 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 15648 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 15648 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 43240000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 582680000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 625920000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 625920000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001210 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.311834 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.016639 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.016639 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------