diff options
Diffstat (limited to 'tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index b582ff405..5338d200d 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 839358 # Simulator instruction rate (inst/s) -host_mem_usage 328912 # Number of bytes of host memory used -host_seconds 321.31 # Real time elapsed on the host -host_tick_rate 1189158712 # Simulator tick rate (ticks/s) +host_inst_rate 855655 # Simulator instruction rate (inst/s) +host_mem_usage 331116 # Number of bytes of host memory used +host_seconds 315.19 # Real time elapsed on the host +host_tick_rate 1212247082 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269695959 # Number of instructions simulated sim_seconds 0.382091 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 2195642 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.995395 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4077.137530 # Average occupied blocks per context system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 20188.783508 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 17188.783508 # average overall mshr miss latency @@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses 808 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.325918 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 667.480800 # Average occupied blocks per context system.cpu.icache.overall_accesses 217696172 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -177,6 +181,10 @@ system.cpu.l2cache.demand_mshr_misses 195509 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.198854 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.350512 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 6516.062046 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 11485.589337 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 2067619 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000.158560 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency |