summaryrefslogtreecommitdiff
path: root/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
diff options
context:
space:
mode:
Diffstat (limited to 'tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt')
-rw-r--r--tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt12
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
index fe50ece29..094d83d97 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,11 +1,11 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1578716 # Simulator instruction rate (inst/s)
-host_mem_usage 342176 # Number of bytes of host memory used
-host_seconds 170.83 # Real time elapsed on the host
-host_tick_rate 2233960314 # Simulator tick rate (ticks/s)
+host_inst_rate 617251 # Simulator instruction rate (inst/s)
+host_mem_usage 340428 # Number of bytes of host memory used
+host_seconds 436.93 # Real time elapsed on the host
+host_tick_rate 873410949 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 269686785 # Number of instructions simulated
+sim_insts 269695957 # Number of instructions simulated
sim_seconds 0.381621 # Number of seconds simulated
sim_ticks 381620562000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses)
@@ -200,7 +200,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 70892 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 763241124 # number of cpu cycles simulated
-system.cpu.num_insts 269686785 # Number of instructions executed
+system.cpu.num_insts 269695957 # Number of instructions executed
system.cpu.num_refs 122219131 # Number of memory references
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls