summaryrefslogtreecommitdiff
path: root/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
diff options
context:
space:
mode:
Diffstat (limited to 'tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt')
-rw-r--r--tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt18
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
index e90dea7b7..e994cf670 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1018906 # Simulator instruction rate (inst/s)
-host_mem_usage 366224 # Number of bytes of host memory used
-host_seconds 273.03 # Real time elapsed on the host
-host_tick_rate 1355197592 # Simulator tick rate (ticks/s)
+host_inst_rate 1776708 # Simulator instruction rate (inst/s)
+host_mem_usage 344820 # Number of bytes of host memory used
+host_seconds 156.58 # Real time elapsed on the host
+host_tick_rate 2363113199 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 278192520 # Number of instructions simulated
sim_seconds 0.370011 # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 2066829 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.995279 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
@@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 808 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.325289 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
@@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses 76575 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.199945 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.368128 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
@@ -218,6 +218,6 @@ system.cpu.num_int_register_writes 248344166 # nu
system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_mem_refs 122219139 # number of memory refs
system.cpu.num_store_insts 31439751 # Number of store instructions
-system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
+system.cpu.workload.num_syscalls 444 # Number of system calls
---------- End Simulation Statistics ----------