diff options
Diffstat (limited to 'tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index b30863c58..fe50ece29 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1561663 # Simulator instruction rate (inst/s) -host_mem_usage 340216 # Number of bytes of host memory used -host_seconds 172.69 # Real time elapsed on the host -host_tick_rate 2209830759 # Simulator tick rate (ticks/s) +host_inst_rate 1578716 # Simulator instruction rate (inst/s) +host_mem_usage 342176 # Number of bytes of host memory used +host_seconds 170.83 # Real time elapsed on the host +host_tick_rate 2233960314 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269686785 # Number of instructions simulated sim_seconds 0.381621 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 229177 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 12146389000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.007289 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 229177 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 58.501856 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 122219193 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 20116.021869 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 20116.021869 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 120039828 # number of overall hits system.cpu.dcache.overall_miss_latency 43840154000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.017832 # miss rate for overall accesses @@ -81,13 +81,13 @@ system.cpu.icache.ReadReq_misses 808 # nu system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 269424.955446 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 217696172 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency @@ -106,7 +106,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 217696172 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 217695364 # number of overall hits system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses @@ -155,13 +155,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 125325 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 229129 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 229129 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 13.678118 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 2054848 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000.160754 # average overall miss latency @@ -180,7 +180,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 2054848 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000.160754 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1862007 # number of overall hits system.cpu.l2cache.overall_miss_latency 10027763000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.093847 # miss rate for overall accesses |