diff options
Diffstat (limited to 'tests/long/10.mcf/ref')
4 files changed, 38 insertions, 38 deletions
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index 225df2c54..b197a138a 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:19:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 01:06:25 -M5 executing on zizzer +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:48:10 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 165726426000 because target called exit() +Exiting @ tick 164697191500 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 16a3e187b..412b43cf4 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1454099 # Simulator instruction rate (inst/s) -host_mem_usage 332016 # Number of bytes of host memory used -host_seconds 185.47 # Real time elapsed on the host -host_tick_rate 893563512 # Simulator tick rate (ticks/s) +host_inst_rate 738696 # Simulator instruction rate (inst/s) +host_mem_usage 331676 # Number of bytes of host memory used +host_seconds 365.09 # Real time elapsed on the host +host_tick_rate 451120089 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269686773 # Number of instructions simulated -sim_seconds 0.165726 # Number of seconds simulated -sim_ticks 165726426000 # Number of ticks simulated +sim_seconds 0.164697 # Number of seconds simulated +sim_ticks 164697191500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 331452853 # number of cpu cycles simulated +system.cpu.numCycles 329394384 # number of cpu cycles simulated system.cpu.num_insts 269686773 # Number of instructions executed -system.cpu.num_refs 124054655 # Number of memory references +system.cpu.num_refs 122219131 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index fdaf99f0e..ea464f620 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:19:15 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 01:06:48 -M5 executing on zizzer +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:48:10 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 495377140000 because target called exit() +Exiting @ tick 493318720000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index f4739c53b..f7746cc78 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 939339 # Simulator instruction rate (inst/s) -host_mem_usage 339456 # Number of bytes of host memory used -host_seconds 287.10 # Real time elapsed on the host -host_tick_rate 1725433923 # Simulator tick rate (ticks/s) +host_inst_rate 472092 # Simulator instruction rate (inst/s) +host_mem_usage 339120 # Number of bytes of host memory used +host_seconds 571.26 # Real time elapsed on the host +host_tick_rate 863564130 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269686773 # Number of instructions simulated -sim_seconds 0.495377 # Number of seconds simulated -sim_ticks 495377140000 # Number of ticks simulated +sim_seconds 0.493319 # Number of seconds simulated +sim_ticks 493318720000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency @@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 2049944 # number of replacements system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.631489 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.561270 # Cycle average of tags in use system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 165919055000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 165886080000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 229129 # number of writebacks -system.cpu.icache.ReadReq_accesses 331452805 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 329394385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 331451998 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 329393578 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses @@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # ms system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 410721.187113 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 408170.480793 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 331452805 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 329394385 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 331451998 # number of demand (read+write) hits +system.cpu.icache.demand_hits 329393578 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses system.cpu.icache.demand_misses 807 # number of demand (read+write) misses @@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 807 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 331452805 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 329394385 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 331451998 # number of overall hits +system.cpu.icache.overall_hits 329393578 # number of overall hits system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses system.cpu.icache.overall_misses 807 # number of overall misses @@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 666.115369 # Cycle average of tags in use -system.cpu.icache.total_refs 331451998 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 665.896527 # Cycle average of tags in use +system.cpu.icache.total_refs 329393578 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,14 +194,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 108885 # number of replacements system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18052.413380 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18017.047263 # Cycle average of tags in use system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 70892 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 990754280 # number of cpu cycles simulated +system.cpu.numCycles 986637440 # number of cpu cycles simulated system.cpu.num_insts 269686773 # Number of instructions executed -system.cpu.num_refs 124054655 # Number of memory references +system.cpu.num_refs 122219131 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- |