diff options
Diffstat (limited to 'tests/long/10.mcf')
4 files changed, 32 insertions, 32 deletions
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index 6a4d20d87..7af784c72 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 12:49:23 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 14:14:26 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index 9f9cc3407..465862e0f 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 230945 # Simulator instruction rate (inst/s) -host_mem_usage 347768 # Number of bytes of host memory used -host_seconds 395.11 # Real time elapsed on the host -host_tick_rate 113371387 # Simulator tick rate (ticks/s) +host_inst_rate 137427 # Simulator instruction rate (inst/s) +host_mem_usage 350244 # Number of bytes of host memory used +host_seconds 663.99 # Real time elapsed on the host +host_tick_rate 67463360 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91249905 # Number of instructions simulated sim_seconds 0.044795 # Number of seconds simulated @@ -266,16 +266,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 187 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 5457924 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 196064 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 21877 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 398676 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 24099 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 14224 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 8920401 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1867594 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 21877 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 398676 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 24099 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 14224 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 8920401 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1867594 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 14224 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 282853 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1526930 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index c33237447..b2a54aa34 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:30:19 +M5 compiled Apr 21 2011 13:30:37 +M5 started Apr 21 2011 13:35:14 M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 6bc8ba293..516464ff9 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 265187 # Simulator instruction rate (inst/s) -host_mem_usage 346300 # Number of bytes of host memory used -host_seconds 1049.04 # Real time elapsed on the host -host_tick_rate 77591071 # Simulator tick rate (ticks/s) +host_inst_rate 154675 # Simulator instruction rate (inst/s) +host_mem_usage 349680 # Number of bytes of host memory used +host_seconds 1798.56 # Real time elapsed on the host +host_tick_rate 45256270 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192519 # Number of instructions simulated sim_seconds 0.081396 # Number of seconds simulated @@ -233,16 +233,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 66782 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 12492114 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 101572 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 14164 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 43812375 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 37185 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 237293 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 3275 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 30748500 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 8203432 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 14164 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 43812375 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 37185 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 237293 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 3275 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 30748500 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 8203432 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 237293 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 582972 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 2283313 # Number of branches that were predicted taken incorrectly |