diff options
Diffstat (limited to 'tests/long/10.mcf')
6 files changed, 46 insertions, 46 deletions
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini index 7f2a4c792..40541f366 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -49,7 +49,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index 195b58e3f..c22c368b8 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 23:20:12 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-atomic +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:05:48 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 165731691000 because target called exit() +Exiting @ tick 165726426000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index ee5db6e3c..a4a7be0d1 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1935457 # Simulator instruction rate (inst/s) -host_mem_usage 329540 # Number of bytes of host memory used -host_seconds 139.35 # Real time elapsed on the host -host_tick_rate 1189355805 # Simulator tick rate (ticks/s) +host_inst_rate 687504 # Simulator instruction rate (inst/s) +host_mem_usage 331712 # Number of bytes of host memory used +host_seconds 392.27 # Real time elapsed on the host +host_tick_rate 422480782 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269697303 # Number of instructions simulated -sim_seconds 0.165732 # Number of seconds simulated -sim_ticks 165731691000 # Number of ticks simulated +sim_insts 269686773 # Number of instructions simulated +sim_seconds 0.165726 # Number of seconds simulated +sim_ticks 165726426000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 331463383 # number of cpu cycles simulated -system.cpu.num_insts 269697303 # Number of instructions executed +system.cpu.numCycles 331452853 # number of cpu cycles simulated +system.cpu.num_insts 269686773 # Number of instructions executed system.cpu.num_refs 124054655 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini index 106b52826..2447a5715 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -155,7 +155,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index a552023cf..5e04da3a3 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 13 2008 21:51:42 -M5 revision 5729:f186533c0dc2d948be0523b452356918124d7f57 -M5 commit date Sun Nov 09 21:57:15 2008 -0800 -M5 started Nov 13 2008 21:51:43 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-timing +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 20:14:49 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 495387670000 because target called exit() +Exiting @ tick 495377140000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index 94a44a507..2fa37b8f7 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1084581 # Simulator instruction rate (inst/s) -host_mem_usage 336400 # Number of bytes of host memory used -host_seconds 248.67 # Real time elapsed on the host -host_tick_rate 1992187591 # Simulator tick rate (ticks/s) +host_inst_rate 422356 # Simulator instruction rate (inst/s) +host_mem_usage 339176 # Number of bytes of host memory used +host_seconds 638.53 # Real time elapsed on the host +host_tick_rate 775808629 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269697303 # Number of instructions simulated -sim_seconds 0.495388 # Number of seconds simulated -sim_ticks 495387670000 # Number of ticks simulated +sim_insts 269686773 # Number of instructions simulated +sim_seconds 0.495377 # Number of seconds simulated +sim_ticks 495377140000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency @@ -76,14 +76,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 2049944 # number of replacements system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.630642 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.631489 # Cycle average of tags in use system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 165919745000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 165919055000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 229129 # number of writebacks -system.cpu.icache.ReadReq_accesses 331463335 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 331452805 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 331462528 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 331451998 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses @@ -92,16 +92,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # ms system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 410734.235440 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 410721.187113 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 331463335 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 331452805 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 331462528 # number of demand (read+write) hits +system.cpu.icache.demand_hits 331451998 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses system.cpu.icache.demand_misses 807 # number of demand (read+write) misses @@ -112,11 +112,11 @@ system.cpu.icache.demand_mshr_misses 807 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 331463335 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 331452805 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 331462528 # number of overall hits +system.cpu.icache.overall_hits 331451998 # number of overall hits system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses system.cpu.icache.overall_misses 807 # number of overall misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 666.116249 # Cycle average of tags in use -system.cpu.icache.total_refs 331462528 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 666.115369 # Cycle average of tags in use +system.cpu.icache.total_refs 331451998 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,13 +221,13 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 108885 # number of replacements system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18052.553825 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18052.413380 # Cycle average of tags in use system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 70892 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 990775340 # number of cpu cycles simulated -system.cpu.num_insts 269697303 # Number of instructions executed +system.cpu.numCycles 990754280 # number of cpu cycles simulated +system.cpu.num_insts 269686773 # Number of instructions executed system.cpu.num_refs 124054655 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls |