diff options
Diffstat (limited to 'tests/long/20.parser/ref/arm/linux/o3-timing')
| -rw-r--r-- | tests/long/20.parser/ref/arm/linux/o3-timing/config.ini | 7 | ||||
| -rwxr-xr-x | tests/long/20.parser/ref/arm/linux/o3-timing/simout | 6 | ||||
| -rw-r--r-- | tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt | 51 |
3 files changed, 37 insertions, 27 deletions
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini index bdd61e6fb..e2c071016 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini @@ -19,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU @@ -478,7 +479,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -520,7 +521,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -530,5 +531,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout index a9de996c2..c61c0591a 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 8 2012 22:11:51 -gem5 started Jan 9 2012 02:13:40 +gem5 compiled Jan 23 2012 04:16:21 +gem5 started Jan 23 2012 08:49:36 gem5 executing on zizzer command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt index 01bc0f829..0cc2b2b8d 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -2,12 +2,23 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.274199 # Number of seconds simulated sim_ticks 274198757500 # Number of ticks simulated +final_tick 274198757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102660 # Simulator instruction rate (inst/s) -host_tick_rate 49096980 # Simulator tick rate (ticks/s) -host_mem_usage 223104 # Number of bytes of host memory used -host_seconds 5584.84 # Real time elapsed on the host +host_inst_rate 114096 # Simulator instruction rate (inst/s) +host_tick_rate 54566255 # Simulator tick rate (ticks/s) +host_mem_usage 225172 # Number of bytes of host memory used +host_seconds 5025.06 # Real time elapsed on the host sim_insts 573341162 # Number of instructions simulated +system.physmem.bytes_read 15248640 # Number of bytes read from this memory +system.physmem.bytes_inst_read 230400 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10960192 # Number of bytes written to this memory +system.physmem.num_reads 238260 # Number of read requests responded to by this memory +system.physmem.num_writes 171253 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 55611631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 840266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 39971706 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 95583336 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -456,10 +467,10 @@ system.cpu.l2cache.total_refs 1567440 # To system.cpu.l2cache.sampled_refs 239478 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 6.545236 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 204357736000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7517.825600 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13543.290586 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.229426 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.413308 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 7517.812526 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13543.303660 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.229425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.413309 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 760340 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 1079462 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits 116 # number of UpgradeReq hits @@ -471,11 +482,11 @@ system.cpu.l2cache.UpgradeReq_misses 33 # nu system.cpu.l2cache.ReadExReq_misses 108226 # number of ReadExReq misses system.cpu.l2cache.demand_misses 238282 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 238282 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 4448633000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 4448635000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency 68000 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 3706374500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 8155007500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 8155007500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency 8155009500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 8155009500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 890396 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 1079462 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 149 # number of UpgradeReq accesses(hits+misses) @@ -487,11 +498,11 @@ system.cpu.l2cache.UpgradeReq_miss_rate 0.221477 # mi system.cpu.l2cache.ReadExReq_miss_rate 0.317627 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.193548 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.193548 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34205.519161 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34205.534539 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency 2060.606061 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34246.618188 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34224.186048 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34224.186048 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34224.194442 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34224.194442 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,22 +521,22 @@ system.cpu.l2cache.ReadExReq_mshr_misses 108226 # nu system.cpu.l2cache.demand_mshr_misses 238263 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 238263 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4037687500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4037689500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1023000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 3355622000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 7393309500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 7393309500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 7393311500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 7393311500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146044 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.221477 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317627 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.193532 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.193532 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31050.297223 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31050.312603 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.691793 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.036137 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.036137 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |