diff options
Diffstat (limited to 'tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt | 250 |
1 files changed, 127 insertions, 123 deletions
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt index 5187afa41..54e168a67 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,78 +1,82 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 427899 # Simulator instruction rate (inst/s) -host_mem_usage 240600 # Number of bytes of host memory used -host_seconds 1307.48 # Real time elapsed on the host -host_tick_rate 550579326 # Simulator tick rate (ticks/s) +host_inst_rate 827470 # Simulator instruction rate (inst/s) +host_mem_usage 257480 # Number of bytes of host memory used +host_seconds 687.68 # Real time elapsed on the host +host_tick_rate 1050246633 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 559470527 # Number of instructions simulated -sim_seconds 0.719872 # Number of seconds simulated -sim_ticks 719872424000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 127326326 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 19806.811274 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16806.811274 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 126543330 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 15508654000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.006150 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 782996 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 13159666000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.006150 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 782996 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 55727847 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 28149.273084 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25149.273084 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 55371547 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10029586000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.006394 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 356300 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 8960686000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006394 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 356300 # number of WriteReq MSHR misses +sim_insts 569034848 # Number of instructions simulated +sim_seconds 0.722234 # Number of seconds simulated +sim_ticks 722234364000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 159.673059 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 183054173 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22415.807657 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19415.807657 # average overall mshr miss latency -system.cpu.dcache.demand_hits 181914877 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 25538240000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.006224 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1139296 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency +system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 22120352000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006224 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1139296 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.992721 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4066.183353 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 183054173 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22415.807657 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19415.807657 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.992551 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 181914877 # number of overall hits -system.cpu.dcache.overall_miss_latency 25538240000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.006224 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1139296 # number of overall misses +system.cpu.dcache.overall_hits 176840705 # number of overall hits +system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1138918 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 22120352000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006224 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1139296 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1135200 # number of replacements -system.cpu.dcache.sampled_refs 1139296 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1134822 # number of replacements +system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4066.183353 # Cycle average of tags in use -system.cpu.dcache.total_refs 181914877 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 11578483000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1025629 # number of writebacks +system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use +system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1025440 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -94,10 +98,10 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 512145761 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 512134240 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses @@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # ms system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 44452.238521 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 512145761 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency -system.cpu.icache.demand_hits 512134240 # number of demand (read+write) hits +system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses @@ -126,13 +130,13 @@ system.cpu.icache.demand_mshr_misses 11521 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.482234 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 987.615046 # Average occupied blocks per context -system.cpu.icache.overall_accesses 512145761 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.480677 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context +system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 512134240 # number of overall hits +system.cpu.icache.overall_hits 516599864 # number of overall hits system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses system.cpu.icache.overall_misses 11521 # number of overall misses @@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 9788 # number of replacements system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 987.615046 # Cycle average of tags in use -system.cpu.icache.total_refs 512134240 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use +system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -171,94 +175,94 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 356300 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 236267 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 6241716000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.336887 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 120033 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336887 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 120033 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 794517 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits 236229 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 120031 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 683315 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 5782504000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.139962 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 111202 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4448080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139962 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 111202 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 1025629 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1025629 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 5780996000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1025440 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 6.147006 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1150817 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 919582 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 12024220000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.200931 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 231235 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9249400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.200931 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 231235 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.178887 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.445562 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 5861.784368 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14600.161549 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 1150817 # number of overall (read+write) accesses +system.cpu.l2cache.occ_%::0 0.178502 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.445374 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 919582 # number of overall hits -system.cpu.l2cache.overall_miss_latency 12024220000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.200931 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 231235 # number of overall misses +system.cpu.l2cache.overall_hits 919235 # number of overall hits +system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 231204 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9249400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.200931 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 231235 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 212119 # number of replacements -system.cpu.l2cache.sampled_refs 232160 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 212089 # number of replacements +system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 20461.945917 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1427089 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 510281834000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 172310 # number of writebacks +system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 172302 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1439744848 # number of cpu cycles simulated +system.cpu.numCycles 1444468728 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 1439744848 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 1444468728 # Number of busy cycles +system.cpu.num_conditional_control_insts 92286726 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 16003168 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 559470527 # Number of instructions executed -system.cpu.num_int_alu_accesses 464140465 # Number of integer alu accesses -system.cpu.num_int_insts 464140465 # number of integer instructions -system.cpu.num_int_register_reads 1497198689 # number of times the integer registers were read -system.cpu.num_int_register_writes 415939738 # number of times the integer registers were written -system.cpu.num_load_insts 128127024 # Number of load instructions -system.cpu.num_mem_refs 184987503 # number of memory refs +system.cpu.num_insts 569034848 # Number of instructions executed +system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses +system.cpu.num_int_insts 470727703 # number of integer instructions +system.cpu.num_int_register_reads 1511252780 # number of times the integer registers were read +system.cpu.num_int_register_writes 425461081 # number of times the integer registers were written +system.cpu.num_load_insts 126029556 # Number of load instructions +system.cpu.num_mem_refs 182890035 # number of memory refs system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.workload.PROG:num_syscalls 548 # Number of system calls |