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-rwxr-xr-xtests/long/20.parser/ref/x86/linux/simple-atomic/simout10
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt16
-rwxr-xr-xtests/long/20.parser/ref/x86/linux/simple-timing/simout10
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt118
4 files changed, 77 insertions, 77 deletions
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
index 4cc446c6f..20050d89e 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 8 2009 12:30:02
-M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
-M5 started Apr 8 2009 12:52:55
-M5 executing on maize
+M5 compiled Apr 12 2009 13:26:17
+M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch
+M5 started Apr 12 2009 13:27:47
+M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -74,4 +74,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 868476152500 because target called exit()
+Exiting @ tick 868476160000 because target called exit()
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 4ce9ac1a4..95bb2d9ce 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -1,17 +1,17 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2610049 # Simulator instruction rate (inst/s)
-host_mem_usage 203408 # Number of bytes of host memory used
-host_seconds 572.97 # Real time elapsed on the host
-host_tick_rate 1515741316 # Simulator tick rate (ticks/s)
+host_inst_rate 1354692 # Simulator instruction rate (inst/s)
+host_mem_usage 201092 # Number of bytes of host memory used
+host_seconds 1103.93 # Real time elapsed on the host
+host_tick_rate 786714284 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1495482356 # Number of instructions simulated
+sim_insts 1495482368 # Number of instructions simulated
sim_seconds 0.868476 # Number of seconds simulated
-sim_ticks 868476152500 # Number of ticks simulated
+sim_ticks 868476160000 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1736952306 # number of cpu cycles simulated
-system.cpu.num_insts 1495482356 # Number of instructions executed
+system.cpu.numCycles 1736952321 # number of cpu cycles simulated
+system.cpu.num_insts 1495482368 # Number of instructions executed
system.cpu.num_refs 533262337 # Number of memory references
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
index bbd611598..2db6852eb 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 8 2009 12:30:02
-M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
-M5 started Apr 8 2009 12:55:56
-M5 executing on maize
+M5 compiled Apr 12 2009 13:26:17
+M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch
+M5 started Apr 12 2009 13:27:47
+M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -74,4 +74,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 1722352498000 because target called exit()
+Exiting @ tick 1722352562000 because target called exit()
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
index 458dc4744..3f66b5d0c 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1776301 # Simulator instruction rate (inst/s)
-host_mem_usage 210956 # Number of bytes of host memory used
-host_seconds 841.91 # Real time elapsed on the host
-host_tick_rate 2045771672 # Simulator tick rate (ticks/s)
+host_inst_rate 965325 # Simulator instruction rate (inst/s)
+host_mem_usage 208960 # Number of bytes of host memory used
+host_seconds 1549.20 # Real time elapsed on the host
+host_tick_rate 1111767915 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1495482356 # Number of instructions simulated
-sim_seconds 1.722352 # Number of seconds simulated
-sim_ticks 1722352498000 # Number of ticks simulated
+sim_insts 1495482368 # Number of instructions simulated
+sim_seconds 1.722353 # Number of seconds simulated
+sim_ticks 1722352562000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency
@@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0
system.cpu.dcache.replacements 2513875 # number of replacements
system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4086.831321 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4086.831173 # Cycle average of tags in use
system.cpu.dcache.total_refs 530744411 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 8217698000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 8217762000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1463913 # number of writebacks
-system.cpu.icache.ReadReq_accesses 1068347064 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1068344251 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 1068347073 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 48417.910448 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 45417.910448 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1068344259 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 136248000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 127753000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 127806000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 379788.215784 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 379653.254797 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1068347064 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1068344251 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 1068347073 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 48417.910448 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 45417.910448 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1068344259 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 136248000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
-system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses
+system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 127753000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 127806000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 2813 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1068347064 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 1068347073 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 48417.910448 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 45417.910448 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1068344251 # number of overall hits
-system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles
+system.cpu.icache.overall_hits 1068344259 # number of overall hits
+system.cpu.icache.overall_miss_latency 136248000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
-system.cpu.icache.overall_misses 2813 # number of overall misses
+system.cpu.icache.overall_misses 2814 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 127753000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 127806000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1253 # number of replacements
-system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 886.488028 # Cycle average of tags in use
-system.cpu.icache.total_refs 1068344251 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 887.487990 # Cycle average of tags in use
+system.cpu.icache.total_refs 1068344259 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
@@ -134,16 +134,16 @@ system.cpu.l2cache.ReadExReq_misses 791158 # nu
system.cpu.l2cache.ReadExReq_mshr_miss_latency 31646320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 791158 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 1729626 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses 1729627 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1310104 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 21815144000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 21815196000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.242551 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 419522 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 16780880000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_misses 419523 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 16780920000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242551 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 419522 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses 419523 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 674990 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.214655 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
@@ -157,50 +157,50 @@ system.cpu.l2cache.Writeback_accesses 1463913 # nu
system.cpu.l2cache.Writeback_hits 1463913 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 3.428071 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 3.428066 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 2520784 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses 2520785 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000.009499 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1310104 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 62955371500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 62955423500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.480279 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 1210680 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses 1210681 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 48427200000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 48427240000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.480279 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 1210680 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses 1210681 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 2520784 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses 2520785 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000.009499 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1310104 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 62955371500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 62955423500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.480279 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 1210680 # number of overall misses
+system.cpu.l2cache.overall_misses 1210681 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 48427200000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 48427240000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 1210680 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses 1210681 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 663512 # number of replacements
-system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 663513 # number of replacements
+system.cpu.l2cache.sampled_refs 679921 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 17216.029598 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 17216.037197 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 921771430000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.warmup_cycle 921771494000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 481430 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 3444704996 # number of cpu cycles simulated
-system.cpu.num_insts 1495482356 # Number of instructions executed
+system.cpu.numCycles 3444705124 # number of cpu cycles simulated
+system.cpu.num_insts 1495482368 # Number of instructions executed
system.cpu.num_refs 533262337 # Number of memory references
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls