diff options
Diffstat (limited to 'tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt')
| -rw-r--r-- | tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt | 56 |
1 files changed, 36 insertions, 20 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index 5d80e04f0..9be74e08a 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1477024 # Simulator instruction rate (inst/s) -host_mem_usage 207136 # Number of bytes of host memory used -host_seconds 269.91 # Real time elapsed on the host -host_tick_rate 2101151515 # Simulator tick rate (ticks/s) +host_inst_rate 1404632 # Simulator instruction rate (inst/s) +host_mem_usage 189192 # Number of bytes of host memory used +host_seconds 283.82 # Real time elapsed on the host +host_tick_rate 1998169503 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 398664611 # Number of instructions simulated +sim_insts 398664609 # Number of instructions simulated sim_seconds 0.567124 # Number of seconds simulated -sim_ticks 567123959000 # Number of ticks simulated +sim_ticks 567124013000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 24216.842105 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22216.842105 # average ReadReq mshr miss latency @@ -76,14 +76,26 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3289.454030 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3289.453852 # Cycle average of tags in use system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 625 # number of writebacks -system.cpu.icache.ReadReq_accesses 398664612 # number of ReadReq accesses(hits+misses) +system.cpu.dtb.accesses 168275276 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 168275220 # DTB hits +system.cpu.dtb.misses 56 # DTB misses +system.cpu.dtb.read_accesses 94754511 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 94754490 # DTB read hits +system.cpu.dtb.read_misses 21 # DTB read misses +system.cpu.dtb.write_accesses 73520765 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 73520730 # DTB write hits +system.cpu.dtb.write_misses 35 # DTB write misses +system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 23471.004628 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 21471.004628 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 398660939 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 86209000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses @@ -92,16 +104,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # ms system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 108538.235502 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 398664612 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 23471.004628 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 21471.004628 # average overall mshr miss latency -system.cpu.icache.demand_hits 398660939 # number of demand (read+write) hits +system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 86209000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses @@ -112,11 +124,11 @@ system.cpu.icache.demand_mshr_misses 3673 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 398664612 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 23471.004628 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 21471.004628 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 398660939 # number of overall hits +system.cpu.icache.overall_hits 398660993 # number of overall hits system.cpu.icache.overall_miss_latency 86209000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses system.cpu.icache.overall_misses 3673 # number of overall misses @@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1769 # number of replacements system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1795.369888 # Cycle average of tags in use -system.cpu.icache.total_refs 398660939 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1795.369803 # Cycle average of tags in use +system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 398664839 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 398664666 # ITB hits +system.cpu.itb.misses 173 # ITB misses system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency @@ -224,14 +240,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 6 # number of replacements system.cpu.l2cache.sampled_refs 3981 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3355.056948 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3355.056761 # Cycle average of tags in use system.cpu.l2cache.total_refs 510 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 567123959000 # number of cpu cycles simulated -system.cpu.num_insts 398664611 # Number of instructions executed -system.cpu.num_refs 174183401 # Number of memory references +system.cpu.numCycles 567124013000 # number of cpu cycles simulated +system.cpu.num_insts 398664609 # Number of instructions executed +system.cpu.num_refs 174183455 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- |