diff options
Diffstat (limited to 'tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt')
| -rw-r--r-- | tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt | 99 |
1 files changed, 48 insertions, 51 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index ebb18ce61..6d3f9def2 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1238026 # Simulator instruction rate (inst/s) -host_mem_usage 207368 # Number of bytes of host memory used -host_seconds 322.02 # Real time elapsed on the host -host_tick_rate 1761163764 # Simulator tick rate (ticks/s) +host_inst_rate 850841 # Simulator instruction rate (inst/s) +host_mem_usage 157124 # Number of bytes of host memory used +host_seconds 468.55 # Real time elapsed on the host +host_tick_rate 1210368735 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated -sim_seconds 0.567124 # Number of seconds simulated -sim_ticks 567124013000 # Number of ticks simulated +sim_seconds 0.567123 # Number of seconds simulated +sim_ticks 567123353000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24216.842105 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22216.842105 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 23522.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21522.105263 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 23006000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 22346000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 21106000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 20446000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses) @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 24825.515947 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22825.515947 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 24670.731707 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22670.731707 # average overall mshr miss latency system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 105856000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 105196000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 97328000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 96668000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 24825.515947 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22825.515947 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 24670.731707 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22670.731707 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 168270956 # number of overall hits -system.cpu.dcache.overall_miss_latency 105856000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 105196000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_misses 4264 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 97328000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 96668000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3289.453852 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3289.454246 # Cycle average of tags in use system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 625 # number of writebacks @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1769 # number of replacements system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1795.369803 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1795.369921 # Cycle average of tags in use system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -171,13 +171,13 @@ system.cpu.l2cache.ReadExReq_mshr_misses 3202 # nu system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 530 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 90046000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.885356 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4093 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 45023000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885356 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4093 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 88836000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 44418000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -188,13 +188,10 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1232000 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 625 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 625 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.128109 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.120240 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -203,14 +200,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 530 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 160490000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.932268 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7295 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 585 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 159280000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.925240 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7240 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 80245000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.932268 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7295 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 79640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.925240 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7240 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -218,14 +215,14 @@ system.cpu.l2cache.overall_accesses 7825 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 530 # number of overall hits -system.cpu.l2cache.overall_miss_latency 160490000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.932268 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7295 # number of overall misses +system.cpu.l2cache.overall_hits 585 # number of overall hits +system.cpu.l2cache.overall_miss_latency 159280000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7240 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 80245000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.932268 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7295 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 79640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -237,15 +234,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 6 # number of replacements -system.cpu.l2cache.sampled_refs 3981 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 15 # number of replacements +system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3355.056761 # Cycle average of tags in use -system.cpu.l2cache.total_refs 510 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3714.863490 # Cycle average of tags in use +system.cpu.l2cache.total_refs 540 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1134248026 # number of cpu cycles simulated +system.cpu.numCycles 1134246706 # number of cpu cycles simulated system.cpu.num_insts 398664609 # Number of instructions executed system.cpu.num_refs 174183455 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls |