diff options
Diffstat (limited to 'tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 5933cded2..f93d01d91 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2382679 # Simulator instruction rate (inst/s) -host_mem_usage 212620 # Number of bytes of host memory used -host_seconds 167.32 # Real time elapsed on the host -host_tick_rate 3390857898 # Simulator tick rate (ticks/s) +host_inst_rate 860135 # Simulator instruction rate (inst/s) +host_mem_usage 198216 # Number of bytes of host memory used +host_seconds 463.49 # Real time elapsed on the host +host_tick_rate 1224083493 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated sim_seconds 0.567352 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 4264 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.802954 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3288.899192 # Average occupied blocks per context system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency @@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses 3673 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.876526 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1795.124700 # Average occupied blocks per context system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency @@ -209,6 +213,10 @@ system.cpu.l2cache.demand_mshr_misses 7240 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.101996 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.011352 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3342.203160 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 371.972955 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency |