diff options
Diffstat (limited to 'tests/long/30.eon/ref/alpha/tru64/simple-timing')
5 files changed, 116 insertions, 164 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index 452538e49..bc260bf15 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -182,11 +156,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin output=cout diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out index 602da9705..0a9655414 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -27,11 +24,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -50,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -179,23 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index 328856ce7..552adff15 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 689508 # Simulator instruction rate (inst/s) -host_mem_usage 185012 # Number of bytes of host memory used -host_seconds 578.19 # Real time elapsed on the host -host_tick_rate 1033135 # Simulator tick rate (ticks/s) +host_inst_rate 557007 # Simulator instruction rate (inst/s) +host_mem_usage 156576 # Number of bytes of host memory used +host_seconds 715.73 # Real time elapsed on the host +host_tick_rate 396092779 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 398664450 # Number of instructions simulated -sim_seconds 0.000597 # Number of seconds simulated -sim_ticks 597346012 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 94754482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3956.610526 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2956.610526 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 94753532 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3758780 # number of ReadReq miss cycles +sim_insts 398664597 # Number of instructions simulated +sim_seconds 0.283494 # Number of seconds simulated +sim_ticks 283494379000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3630.526316 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2630.526316 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 94753539 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3449000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2808780 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2499000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3940.471580 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2940.471580 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73517525 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 12617390 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3618.988132 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2618.988132 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73517527 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 11588000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 9415390 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8386000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40527.711224 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40527.713391 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 168275209 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3944.164258 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency -system.cpu.dcache.demand_hits 168271057 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 16376170 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3621.628131 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2621.628131 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168271066 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 15037000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 12224170 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10885000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 168275209 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3944.164258 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 168271057 # number of overall hits -system.cpu.dcache.overall_miss_latency 16376170 # number of overall miss cycles +system.cpu.dcache.overall_accesses 168275218 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3621.628131 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2621.628131 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 168271066 # number of overall hits +system.cpu.dcache.overall_miss_latency 15037000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_misses 4152 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 12224170 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10885000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,54 +76,54 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3222.413784 # Cycle average of tags in use -system.cpu.dcache.total_refs 168271057 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3289.772430 # Cycle average of tags in use +system.cpu.dcache.total_refs 168271066 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 625 # number of writebacks -system.cpu.icache.ReadReq_accesses 398664451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3820.906097 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.906097 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 398660777 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 14038009 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 398664598 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3633.814321 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2633.814321 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 398660925 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13347000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 3674 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10364009 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 9674000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3674 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 108508.649156 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 108538.231691 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 398664451 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3820.906097 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency -system.cpu.icache.demand_hits 398660777 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 14038009 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 398664598 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3633.814321 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2633.814321 # average overall mshr miss latency +system.cpu.icache.demand_hits 398660925 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13347000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses -system.cpu.icache.demand_misses 3674 # number of demand (read+write) misses +system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10364009 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 9674000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3674 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 398664451 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3820.906097 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 398660777 # number of overall hits -system.cpu.icache.overall_miss_latency 14038009 # number of overall miss cycles +system.cpu.icache.overall_accesses 398664598 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3633.814321 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2633.814321 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 398660925 # number of overall hits +system.cpu.icache.overall_miss_latency 13347000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses -system.cpu.icache.overall_misses 3674 # number of overall misses +system.cpu.icache.overall_misses 3673 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10364009 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 9674000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3674 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -135,60 +135,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1770 # number of replacements -system.cpu.icache.sampled_refs 3674 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1769 # number of replacements +system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1765.882838 # Cycle average of tags in use -system.cpu.icache.total_refs 398660777 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1795.510184 # Cycle average of tags in use +system.cpu.icache.total_refs 398660925 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 7826 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2983.265505 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.984530 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 7825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2707.276275 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1705.023697 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 21404930 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.916816 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 7175 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13811764 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916816 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 7175 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 19422000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.916805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 7174 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12231840 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 7174 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.177840 # Average number of references to valid blocks. +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.177865 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 7826 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2983.265505 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2707.276275 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1705.023697 # average overall mshr miss latency system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 21404930 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.916816 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7175 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 19422000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.916805 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7174 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 13811764 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.916816 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7175 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 12231840 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.916805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7174 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8451 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2983.265505 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_accesses 8450 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2707.276275 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1705.023697 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1276 # number of overall hits -system.cpu.l2cache.overall_miss_latency 21404930 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.849012 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7175 # number of overall misses +system.cpu.l2cache.overall_miss_latency 19422000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.848994 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7174 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13811764 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.849012 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7175 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 12231840 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.848994 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -201,16 +201,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 7175 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 7174 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6344.042673 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 6483.699084 # Cycle average of tags in use system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 597346012 # number of cpu cycles simulated -system.cpu.num_insts 398664450 # Number of instructions executed -system.cpu.num_refs 174183390 # Number of memory references +system.cpu.numCycles 283494379000 # number of cpu cycles simulated +system.cpu.num_insts 398664597 # Number of instructions executed +system.cpu.num_refs 174183399 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr index 8534c55aa..4bb0d9bbe 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr @@ -1,10 +1,11 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data +warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout index 039e2d4ce..1e8a0ac6f 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.000000 +OO-style eon Time= 0.283333 |