diff options
Diffstat (limited to 'tests/long/30.eon/ref/alpha')
| -rwxr-xr-x | tests/long/30.eon/ref/alpha/tru64/o3-timing/simout | 6 | ||||
| -rw-r--r-- | tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 11 |
2 files changed, 9 insertions, 8 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index 748f3f017..1688d3208 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 13:44:21 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:25:09 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 6eff69d6b..eb0b216c3 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 158570 # Simulator instruction rate (inst/s) -host_mem_usage 213052 # Number of bytes of host memory used -host_seconds 2368.51 # Real time elapsed on the host -host_tick_rate 57558166 # Simulator tick rate (ticks/s) +host_inst_rate 178067 # Simulator instruction rate (inst/s) +host_mem_usage 212832 # Number of bytes of host memory used +host_seconds 2109.17 # Real time elapsed on the host +host_tick_rate 64635199 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574819 # Number of instructions simulated sim_seconds 0.136327 # Number of seconds simulated @@ -145,9 +145,10 @@ system.cpu.dtb.write_hits 80299022 # DT system.cpu.dtb.write_misses 1470 # DTB write misses system.cpu.fetch.Branches 62456368 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 64427463 # Number of cache lines fetched -system.cpu.fetch.Cycles 168595579 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 104167812 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 1484985 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 548969588 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 304 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 6021463 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.229068 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 64427463 # Number of cycles fetch is stalled on an Icache miss |