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-rw-r--r--tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini10
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/inorder-timing/simout6
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt18
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini8
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt18
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini13
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr11
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/simple-atomic/simout16
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt89
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini11
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/simple-timing/simerr11
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/simple-timing/simout16
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt446
-rw-r--r--tests/long/30.eon/ref/arm/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/30.eon/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt18
-rw-r--r--tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini13
-rwxr-xr-xtests/long/30.eon/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/30.eon/ref/arm/linux/simple-atomic/simout16
-rw-r--r--tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt109
-rw-r--r--tests/long/30.eon/ref/arm/linux/simple-timing/config.ini11
-rwxr-xr-xtests/long/30.eon/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/30.eon/ref/arm/linux/simple-timing/simout16
-rw-r--r--tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt474
25 files changed, 707 insertions, 647 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini
index c7fe40f76..16e4d1756 100644
--- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -205,7 +207,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout
index 9794df862..1c2a18294 100755
--- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 8 2011 15:00:53
-gem5 started Jul 8 2011 16:09:26
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
index 8f2720cda..a04efd18a 100644
--- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.139995 # Number of seconds simulated
sim_ticks 139995113500 # Number of ticks simulated
+final_tick 139995113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 56567 # Simulator instruction rate (inst/s)
-host_tick_rate 19864025 # Simulator tick rate (ticks/s)
-host_mem_usage 252292 # Number of bytes of host memory used
-host_seconds 7047.67 # Real time elapsed on the host
+host_inst_rate 118986 # Simulator instruction rate (inst/s)
+host_tick_rate 41783300 # Simulator tick rate (ticks/s)
+host_mem_usage 214012 # Number of bytes of host memory used
+host_seconds 3350.50 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
+system.physmem.bytes_read 469184 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 214784 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 7331 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 3351431 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1534225 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 3351431 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 01d03e5c5..0fce2844b 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
index 46133d214..137fd0ee8 100755
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 16:10:09
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index f27e3deec..28785f469 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.089480 # Number of seconds simulated
sim_ticks 89480174500 # Number of ticks simulated
+final_tick 89480174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 168732 # Simulator instruction rate (inst/s)
-host_tick_rate 40200085 # Simulator tick rate (ticks/s)
-host_mem_usage 211620 # Number of bytes of host memory used
-host_seconds 2225.87 # Real time elapsed on the host
+host_inst_rate 190161 # Simulator instruction rate (inst/s)
+host_tick_rate 45305657 # Simulator tick rate (ticks/s)
+host_mem_usage 214676 # Number of bytes of host memory used
+host_seconds 1975.03 # Real time elapsed on the host
sim_insts 375574794 # Number of instructions simulated
+system.physmem.bytes_read 475840 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 219968 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 7435 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 5317826 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 2458288 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 5317826 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index 5f40a4aa8..8310ba9e4 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
index ea7dd73a3..860580eeb 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
@@ -1,11 +1,7 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
@@ -53,5 +49,4 @@ Writing to chair.cook.ppm
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
index 0fd1f360f..3a628f576 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 12:03:34
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index 6655c3650..3ed2b47f1 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,66 +1,77 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 5567399 # Simulator instruction rate (inst/s)
-host_mem_usage 202284 # Number of bytes of host memory used
-host_seconds 71.61 # Real time elapsed on the host
-host_tick_rate 2783694716 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 398664595 # Number of instructions simulated
sim_seconds 0.199332 # Number of seconds simulated
sim_ticks 199332411500 # Number of ticks simulated
-system.cpu.dtb.data_accesses 168275274 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 168275218 # DTB hits
-system.cpu.dtb.data_misses 56 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
+final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3927016 # Simulator instruction rate (inst/s)
+host_tick_rate 1963508553 # Simulator tick rate (ticks/s)
+host_mem_usage 204908 # Number of bytes of host memory used
+host_seconds 101.52 # Real time elapsed on the host
+sim_insts 398664595 # Number of instructions simulated
+system.physmem.bytes_read 2257107875 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1594658604 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 492356798 # Number of bytes written to this memory
+system.physmem.num_reads 493419140 # Number of read requests responded to by this memory
+system.physmem.num_writes 73520729 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 11323336020 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999996548 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 2470028804 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 13793364824 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 94754510 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94754489 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
-system.cpu.dtb.write_accesses 73520764 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 94754510 # DTB read accesses
system.cpu.dtb.write_hits 73520729 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 398664824 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 73520764 # DTB write accesses
+system.cpu.dtb.data_hits 168275218 # DTB hits
+system.cpu.dtb.data_misses 56 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 168275274 # DTB accesses
system.cpu.itb.fetch_hits 398664651 # ITB hits
system.cpu.itb.fetch_misses 173 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 398664824 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 398664824 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 398664824 # Number of busy cycles
-system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
-system.cpu.num_fp_insts 155295119 # number of float instructions
-system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
-system.cpu.num_func_calls 16015498 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 398664595 # Number of instructions executed
system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
+system.cpu.num_func_calls 16015498 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls
system.cpu.num_int_insts 316365907 # number of integer instructions
+system.cpu.num_fp_insts 155295119 # number of float instructions
system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read
system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written
-system.cpu.num_load_insts 94754510 # Number of load instructions
+system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
system.cpu.num_mem_refs 168275274 # number of memory refs
+system.cpu.num_load_insts 94754510 # Number of load instructions
system.cpu.num_store_insts 73520764 # Number of store instructions
-system.cpu.workload.num_syscalls 215 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 398664824 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
index c222d6133..63aac5a1a 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
index ea7dd73a3..860580eeb 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
@@ -1,11 +1,7 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
@@ -53,5 +49,4 @@ Writing to chair.cook.ppm
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
index 2be6be9ef..06075d86e 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 12:04:03
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 94a73b71f..af7a7f90d 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,255 +1,265 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2583171 # Simulator instruction rate (inst/s)
-host_mem_usage 210032 # Number of bytes of host memory used
-host_seconds 154.33 # Real time elapsed on the host
-host_tick_rate 3676130341 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 398664609 # Number of instructions simulated
sim_seconds 0.567343 # Number of seconds simulated
sim_ticks 567343170000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55212.991880 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52212.991880 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 73517528 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 176792000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 167186000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 54209.537572 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 168271068 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 225078000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 212622000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 3288.912598 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.802957 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 54209.537572 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 168271068 # number of overall hits
-system.cpu.dcache.overall_miss_latency 225078000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 4152 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 212622000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 764 # number of replacements
-system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3288.912598 # Cycle average of tags in use
-system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 649 # number of writebacks
-system.cpu.dtb.data_accesses 168275276 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 168275220 # DTB hits
-system.cpu.dtb.data_misses 56 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
+final_tick 567343170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1814376 # Simulator instruction rate (inst/s)
+host_tick_rate 2582053806 # Simulator tick rate (ticks/s)
+host_mem_usage 213620 # Number of bytes of host memory used
+host_seconds 219.73 # Real time elapsed on the host
+sim_insts 398664609 # Number of instructions simulated
+system.physmem.bytes_read 459520 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 205120 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 7180 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 809951 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 361545 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 809951 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 94754511 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94754490 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
-system.cpu.dtb.write_accesses 73520765 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 94754511 # DTB read accesses
system.cpu.dtb.write_hits 73520730 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
-system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199 # average ReadReq mshr miss latency
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 73520765 # DTB write accesses
+system.cpu.dtb.data_hits 168275220 # DTB hits
+system.cpu.dtb.data_misses 56 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 168275276 # DTB accesses
+system.cpu.itb.fetch_hits 398664666 # ITB hits
+system.cpu.itb.fetch_misses 173 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 398664839 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 215 # Number of system calls
+system.cpu.numCycles 1134686340 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 398664609 # Number of instructions executed
+system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
+system.cpu.num_func_calls 16015498 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls
+system.cpu.num_int_insts 316365921 # number of integer instructions
+system.cpu.num_fp_insts 155295119 # number of float instructions
+system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read
+system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
+system.cpu.num_mem_refs 168275276 # number of memory refs
+system.cpu.num_load_insts 94754511 # Number of load instructions
+system.cpu.num_store_insts 73520765 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 1134686340 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 1769 # number of replacements
+system.cpu.icache.tagsinuse 1795.131074 # Cycle average of tags in use
+system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1795.131074 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.876529 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits
+system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 398660993 # number of overall hits
+system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses
+system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 3673 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 186032000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
-system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
-system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses
+system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 175013000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 175013000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 1795.131074 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.876529 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 398660993 # number of overall hits
-system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
-system.cpu.icache.overall_misses 3673 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 175013000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 1769 # number of replacements
-system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1795.131074 # Cycle average of tags in use
-system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 398664839 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 398664666 # ITB hits
-system.cpu.itb.fetch_misses 173 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 764 # number of replacements
+system.cpu.dcache.tagsinuse 3288.912598 # Cycle average of tags in use
+system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 3288.912598 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.802957 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 73517528 # number of WriteReq hits
+system.cpu.dcache.demand_hits 168271068 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 168271068 # number of overall hits
+system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses
+system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 4152 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 176792000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 225078000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 225078000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55212.991880 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 54209.537572 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 54209.537572 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 649 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 167186000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 212622000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 212622000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52212.991880 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 13 # number of replacements
+system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 656 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 4572 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.143482 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 3397.175455 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 371.536808 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.103674 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.011338 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 163384000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.981262 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits 645 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 645 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 3142 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 125680000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981262 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 3142 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits
+system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 7180 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 209976000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency 163384000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 373360000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 373360000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.143482 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.981262 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.917572 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.917572 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 645 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 373360000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.917572 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 3142 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 125680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 287200000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 287200000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981262 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.917572 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 3397.175455 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 371.536808 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.103674 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.011338 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.917572 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 645 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 373360000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.917572 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 7180 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 287200000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.917572 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 13 # number of replacements
-system.cpu.l2cache.sampled_refs 4572 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 656 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1134686340 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 1134686340 # Number of busy cycles
-system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
-system.cpu.num_fp_insts 155295119 # number of float instructions
-system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
-system.cpu.num_func_calls 16015498 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 398664609 # Number of instructions executed
-system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses
-system.cpu.num_int_insts 316365921 # number of integer instructions
-system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read
-system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written
-system.cpu.num_load_insts 94754511 # Number of load instructions
-system.cpu.num_mem_refs 168275276 # number of memory refs
-system.cpu.num_store_insts 73520765 # Number of store instructions
-system.cpu.workload.num_syscalls 215 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
index 8c023b5bc..297538e80 100644
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout
index 5bda3e9bb..2948fc7c4 100755
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 17:59:30
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:57:55
+gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
index 3a7bc5069..995432cc7 100644
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.104498 # Number of seconds simulated
sim_ticks 104497559500 # Number of ticks simulated
+final_tick 104497559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 166687 # Simulator instruction rate (inst/s)
-host_tick_rate 49899949 # Simulator tick rate (ticks/s)
-host_mem_usage 223124 # Number of bytes of host memory used
-host_seconds 2094.14 # Real time elapsed on the host
+host_inst_rate 155883 # Simulator instruction rate (inst/s)
+host_tick_rate 46665641 # Simulator tick rate (ticks/s)
+host_mem_usage 228988 # Number of bytes of host memory used
+host_seconds 2239.28 # Real time elapsed on the host
sim_insts 349066034 # Number of instructions simulated
+system.physmem.bytes_read 464512 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 192704 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 7258 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 4445195 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1844100 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 4445195 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
index a5b41f00b..5628f29f0 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr b/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr
index 0de362399..bf930ad43 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr
@@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
index e711f37f2..2369bef1b 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:58:30
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:01:21
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
index 01b0f0b3b..7857a9031 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1939083 # Simulator instruction rate (inst/s)
-host_mem_usage 261408 # Number of bytes of host memory used
-host_seconds 180.02 # Real time elapsed on the host
-host_tick_rate 1179584644 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 349065408 # Number of instructions simulated
sim_seconds 0.212344 # Number of seconds simulated
sim_ticks 212344048000 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2434260 # Simulator instruction rate (inst/s)
+host_tick_rate 1480812932 # Simulator tick rate (ticks/s)
+host_mem_usage 218160 # Number of bytes of host memory used
+host_seconds 143.40 # Real time elapsed on the host
+sim_insts 349065408 # Number of instructions simulated
+system.physmem.bytes_read 1875350709 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1394641440 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 400047783 # Number of bytes written to this memory
+system.physmem.num_reads 443242866 # Number of read requests responded to by this memory
+system.physmem.num_writes 82063572 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 8831661291 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 6567838624 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1883960425 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 10715621716 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 424688097 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 424688097 # Number of busy cycles
-system.cpu.num_conditional_control_insts 16271154 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
-system.cpu.num_fp_insts 114216705 # number of float instructions
-system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
-system.cpu.num_func_calls 12433363 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 349065408 # Number of instructions executed
system.cpu.num_int_alu_accesses 279584926 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
+system.cpu.num_func_calls 12433363 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 16271154 # number of instructions that are conditional controls
system.cpu.num_int_insts 279584926 # number of integer instructions
+system.cpu.num_fp_insts 114216705 # number of float instructions
system.cpu.num_int_register_reads 1887652191 # number of times the integer registers were read
system.cpu.num_int_register_writes 251197918 # number of times the integer registers were written
-system.cpu.num_load_insts 94648758 # Number of load instructions
+system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
system.cpu.num_mem_refs 177024357 # number of memory refs
+system.cpu.num_load_insts 94648758 # Number of load instructions
system.cpu.num_store_insts 82375599 # Number of store instructions
-system.cpu.workload.num_syscalls 191 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 424688097 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
index aed18b872..28a0917d8 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr
index 0de362399..bf930ad43 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr
@@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
index daf6c8759..3428f8224 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:00:20
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:03:55
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
index 1ba27a33f..3b365c759 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,279 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1262416 # Simulator instruction rate (inst/s)
-host_mem_usage 269124 # Number of bytes of host memory used
-host_seconds 276.21 # Real time elapsed on the host
-host_tick_rate 1903846429 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 348687131 # Number of instructions simulated
sim_seconds 0.525854 # Number of seconds simulated
sim_ticks 525854475000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 10895 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 10895 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 94571611 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 49749.688667 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46749.688667 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 94570005 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 79898000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1606 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 75080000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000017 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1606 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 10895 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 10895 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 82052677 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55766.016713 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52766.016713 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 82049805 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 160160000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000035 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2872 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 151544000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 2872 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 39446.538633 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 176624288 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 53608.307280 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 50608.307280 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 176619810 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 240058000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 4478 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 226624000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 4478 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 3078.396238 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.751562 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 176624288 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 53608.307280 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 50608.307280 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 176619810 # number of overall hits
-system.cpu.dcache.overall_miss_latency 240058000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 4478 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 226624000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 4478 # number of overall MSHR misses
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-system.cpu.dcache.replacements 1332 # number of replacements
-system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use
-system.cpu.dcache.total_refs 176641600 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 998 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1206167 # Simulator instruction rate (inst/s)
+host_tick_rate 1819018700 # Simulator tick rate (ticks/s)
+host_mem_usage 227092 # Number of bytes of host memory used
+host_seconds 289.09 # Real time elapsed on the host
+sim_insts 348687131 # Number of instructions simulated
+system.physmem.bytes_read 437312 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 167040 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 6833 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 831622 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 317654 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 831622 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 348660359 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 21025.572005 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 18025.572005 # average ReadReq mshr miss latency
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+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
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+system.cpu.itb.inst_misses 0 # ITB inst misses
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+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 191 # Number of system calls
+system.cpu.numCycles 1051708950 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 348687131 # Number of instructions executed
+system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
+system.cpu.num_func_calls 12433363 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 16271153 # number of instructions that are conditional controls
+system.cpu.num_int_insts 279584925 # number of integer instructions
+system.cpu.num_fp_insts 114216705 # number of float instructions
+system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read
+system.cpu.num_int_register_writes 251197915 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
+system.cpu.num_mem_refs 177024357 # number of memory refs
+system.cpu.num_load_insts 94648758 # Number of load instructions
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+system.cpu.num_busy_cycles 1051708950 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 13796 # number of replacements
+system.cpu.icache.tagsinuse 1765.984158 # Cycle average of tags in use
+system.cpu.icache.total_refs 348644756 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 22344.725758 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1765.984158 # Average occupied blocks per context
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system.cpu.icache.ReadReq_hits 348644756 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 328062000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000045 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 15603 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 281253000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000045 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 15603 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 22344.725758 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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+system.cpu.icache.ReadReq_avg_miss_latency 21025.572005 # average ReadReq miss latency
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+system.cpu.icache.overall_avg_miss_latency 21025.572005 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 348660359 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 21025.572005 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency
-system.cpu.icache.demand_hits 348644756 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 328062000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000045 # miss rate for demand accesses
-system.cpu.icache.demand_misses 15603 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 281253000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000045 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 15603 # number of demand (read+write) MSHR misses
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-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 1765.984158 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.862297 # Average percentage of cache occupancy
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-system.cpu.icache.overall_avg_miss_latency 21025.572005 # average overall miss latency
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency 18025.572005 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 348644756 # number of overall hits
-system.cpu.icache.overall_miss_latency 328062000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000045 # miss rate for overall accesses
-system.cpu.icache.overall_misses 15603 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 281253000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000045 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 15603 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 13796 # number of replacements
-system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1765.984158 # Cycle average of tags in use
-system.cpu.icache.total_refs 348644756 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 2872 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 1332 # number of replacements
+system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use
+system.cpu.dcache.total_refs 176641600 # Total number of references to valid blocks.
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+system.cpu.dcache.avg_refs 39446.538633 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 49749.688667 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55766.016713 # average WriteReq miss latency
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+system.cpu.dcache.overall_avg_miss_latency 53608.307280 # average overall miss latency
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+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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+system.cpu.dcache.demand_mshr_miss_latency 226624000 # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52766.016713 # average WriteReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency 50608.307280 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 48 # number of replacements
+system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 13308 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.725374 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 3134.059650 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 341.613272 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.095644 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.010425 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 13232 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 998 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 16 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 148512000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.994429 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits 13248 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 13248 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 3977 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 2856 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 114240000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994429 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 2856 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 17209 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 13232 # number of ReadReq hits
+system.cpu.l2cache.demand_misses 6833 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 6833 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 206804000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.231100 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 3977 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 159080000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231100 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 3977 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency 148512000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 355316000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 355316000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 17209 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 998 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 998 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.725374 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses 2872 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 20081 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 20081 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.231100 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.994429 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.340272 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.340272 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 20081 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 13248 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 355316000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.340272 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 6833 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 3977 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 2856 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 6833 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 6833 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 159080000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 114240000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 273320000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 273320000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231100 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.340272 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 6833 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 3134.059650 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 341.613272 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.095644 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.010425 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 20081 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.340272 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 13248 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 355316000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.340272 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 6833 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 273320000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.340272 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 6833 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 48 # number of replacements
-system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 13308 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1051708950 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 1051708950 # Number of busy cycles
-system.cpu.num_conditional_control_insts 16271153 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
-system.cpu.num_fp_insts 114216705 # number of float instructions
-system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
-system.cpu.num_func_calls 12433363 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 348687131 # Number of instructions executed
-system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses
-system.cpu.num_int_insts 279584925 # number of integer instructions
-system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read
-system.cpu.num_int_register_writes 251197915 # number of times the integer registers were written
-system.cpu.num_load_insts 94648758 # Number of load instructions
-system.cpu.num_mem_refs 177024357 # number of memory refs
-system.cpu.num_store_insts 82375599 # Number of store instructions
-system.cpu.workload.num_syscalls 191 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------