diff options
Diffstat (limited to 'tests/long/30.eon/ref')
11 files changed, 1042 insertions, 1050 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini index b61906e1d..c7fe40f76 100644 --- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -199,12 +200,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/inorder-timing +cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/y/ksewell/cpu2000/binaries/alpha/tru64/eon +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout index ae0215b03..9794df862 100755 --- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 09:22:03 -gem5 started Jun 19 2011 12:35:06 -gem5 executing on zooks -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/inorder-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 16:09:26 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.133333 -Exiting @ tick 140230347500 because target called exit() +Exiting @ tick 139995113500 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 9448fafb4..8f2720cda 100644 --- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.140230 # Number of seconds simulated -sim_ticks 140230347500 # Number of ticks simulated +sim_seconds 0.139995 # Number of seconds simulated +sim_ticks 139995113500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92522 # Simulator instruction rate (inst/s) -host_tick_rate 32544608 # Simulator tick rate (ticks/s) -host_mem_usage 159896 # Number of bytes of host memory used -host_seconds 4308.87 # Real time elapsed on the host +host_inst_rate 56567 # Simulator instruction rate (inst/s) +host_tick_rate 19864025 # Simulator tick rate (ticks/s) +host_mem_usage 252292 # Number of bytes of host memory used +host_seconds 7047.67 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -24,10 +24,10 @@ system.cpu.dtb.data_hits 168277058 # DT system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 168277114 # DTB accesses -system.cpu.itb.fetch_hits 48911022 # ITB hits -system.cpu.itb.fetch_misses 44512 # ITB misses +system.cpu.itb.fetch_hits 48859849 # ITB hits +system.cpu.itb.fetch_misses 44521 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48955534 # ITB accesses +system.cpu.itb.fetch_accesses 48904370 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 280460696 # number of cpu cycles simulated +system.cpu.numCycles 279990228 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 280031759 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279561038 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 6816 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13555694 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266905002 # Number of cycles cpu stages are processed. -system.cpu.activity 95.166633 # Percentage of cycles cpu is active +system.cpu.timesIdled 6809 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13513618 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266476610 # Number of cycles cpu stages are processed. +system.cpu.activity 95.173539 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -61,79 +61,79 @@ system.cpu.comFloats 50439198 # Nu system.cpu.committedInsts 398664595 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions Simulated (Total) -system.cpu.cpi 0.703500 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.702320 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.703500 # CPI: Total CPI of All Threads -system.cpu.ipc 1.421463 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.702320 # CPI: Total CPI of All Threads +system.cpu.ipc 1.423852 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.421463 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 53559776 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 30675983 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 15431294 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 36114910 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 15774675 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 8007515 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 43.679120 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 29804615 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 23755161 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280315566 # Number of Reads from Int. Register File +system.cpu.ipc_total 1.423852 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 53456377 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 30648707 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 15206922 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 35068414 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 15659516 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 44.654189 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 29689183 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 23767194 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280275252 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439651425 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119618904 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439611111 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119572386 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219815385 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100663476 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 168393095 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 14667100 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 763535 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 15430635 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 29156916 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 34.607496 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 205476801 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 219768867 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100597400 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 168369236 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 14604498 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 601765 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 15206263 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 29381288 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 34.104279 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 205417549 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 2124324 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 78228073 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 202232623 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.107296 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107968598 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172492098 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.503127 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 103201194 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177259502 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.202974 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181732278 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98728418 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.202230 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90865904 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189594792 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.601199 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1967 # number of replacements -system.cpu.icache.tagsinuse 1829.231960 # Cycle average of tags in use -system.cpu.icache.total_refs 48906646 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3894 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12559.487930 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 78021134 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201969094 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.134337 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107567321 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172422907 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.581759 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102759298 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177230930 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.298970 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 181219893 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98770335 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.276351 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90498113 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189492115 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.678117 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 1970 # number of replacements +system.cpu.icache.tagsinuse 1829.847469 # Cycle average of tags in use +system.cpu.icache.total_refs 48855472 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3897 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12536.687708 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1829.231960 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.893180 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 48906646 # number of ReadReq hits -system.cpu.icache.demand_hits 48906646 # number of demand (read+write) hits -system.cpu.icache.overall_hits 48906646 # number of overall hits -system.cpu.icache.ReadReq_misses 4375 # number of ReadReq misses -system.cpu.icache.demand_misses 4375 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4375 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 214226000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 214226000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 214226000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 48911021 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 48911021 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 48911021 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 48965.942857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 48965.942857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 48965.942857 # average overall miss latency +system.cpu.icache.occ_blocks::0 1829.847469 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.893480 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 48855472 # number of ReadReq hits +system.cpu.icache.demand_hits 48855472 # number of demand (read+write) hits +system.cpu.icache.overall_hits 48855472 # number of overall hits +system.cpu.icache.ReadReq_misses 4376 # number of ReadReq misses +system.cpu.icache.demand_misses 4376 # number of demand (read+write) misses +system.cpu.icache.overall_misses 4376 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 214318500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 214318500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 214318500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 48859848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 48859848 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 48859848 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000090 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000090 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000090 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 48975.891225 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 48975.891225 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 48975.891225 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -143,35 +143,35 @@ system.cpu.icache.avg_blocked_cycles::no_targets 45000 system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 481 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 481 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 481 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3894 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3894 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3894 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 479 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 479 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 479 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 3897 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 3897 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 3897 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 185204000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 185204000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 185204000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 185285000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 185285000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 185285000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 47561.376477 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 47561.376477 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 47561.376477 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 47545.547857 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 47545.547857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 47545.547857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.909965 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3284.892021 # Cycle average of tags in use system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3284.909965 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.801980 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3284.892021 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.801976 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 94753265 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 73508694 # number of WriteReq hits system.cpu.dcache.demand_hits 168261959 # number of demand (read+write) hits @@ -180,10 +180,10 @@ system.cpu.dcache.ReadReq_misses 1224 # nu system.cpu.dcache.WriteReq_misses 12035 # number of WriteReq misses system.cpu.dcache.demand_misses 13259 # number of demand (read+write) misses system.cpu.dcache.overall_misses 13259 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 63822000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 626725500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 690547500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 690547500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency 63830500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 626731500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 690562000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 690562000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses @@ -192,16 +192,16 @@ system.cpu.dcache.ReadReq_miss_rate 0.000013 # mi system.cpu.dcache.WriteReq_miss_rate 0.000164 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 52142.156863 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 52075.238887 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 52081.416396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 52081.416396 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 52149.101307 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 52075.737432 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 52082.509993 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 52082.509993 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 82468000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 82468500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1848 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44625.541126 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 44625.811688 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 649 # number of writebacks @@ -214,59 +214,59 @@ system.cpu.dcache.WriteReq_mshr_misses 3202 # nu system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 46179500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 169543500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 215723000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 215723000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 46185000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 169537500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 215722500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 215722500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48610 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52949.250468 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51956.406551 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51956.406551 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48615.789474 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52947.376640 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51956.286127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51956.286127 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 13 # number of replacements -system.cpu.l2cache.tagsinuse 3899.405791 # Cycle average of tags in use -system.cpu.l2cache.total_refs 727 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4719 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.154058 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3900.004949 # Cycle average of tags in use +system.cpu.l2cache.total_refs 729 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4720 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.154449 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3528.869361 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 370.536429 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.107693 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3529.472340 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 370.532609 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.107711 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 656 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 658 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 716 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 716 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4185 # number of ReadReq misses +system.cpu.l2cache.demand_hits 718 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 718 # number of overall hits +system.cpu.l2cache.ReadReq_misses 4186 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 3145 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7330 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7330 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 219146000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 164975000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 384121000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 384121000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4841 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 7331 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 7331 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 219209500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 164966000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 384175500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 384175500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 4844 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 3205 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8046 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8046 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.864491 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 8049 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8049 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.864162 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.981279 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.911012 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.911012 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52364.635603 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52456.279809 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52403.956344 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52403.956344 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.910796 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.910796 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52367.295748 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52453.418124 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52404.242259 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52404.242259 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,24 +278,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4185 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 4186 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 3145 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7330 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7330 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 7331 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 7331 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 168185500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 126767000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 294952500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 294952500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 168226500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 126764000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 294990500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 294990500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864491 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864162 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981279 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.911012 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.911012 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40187.694146 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40307.472178 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40239.085948 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40239.085948 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.910796 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.910796 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40187.888199 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40306.518283 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index b5728d762..eb7300ec9 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr index ea7dd73a3..860580eeb 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr @@ -1,11 +1,7 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera @@ -53,5 +49,4 @@ Writing to chair.cook.ppm 13 8 14 14 8 14 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index 1209b95f2..49472bb38 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,18 +1,14 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 12:29:56 -M5 started Apr 21 2011 13:02:51 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 16:09:26 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. -OO-style eon Time= 0.100000 -Exiting @ tick 113012733500 because target called exit() +OO-style eon Time= 0.083333 +Exiting @ tick 90884909500 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index d0a61b61f..1cdac8523 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,504 +1,506 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 199356 # Simulator instruction rate (inst/s) -host_mem_usage 214136 # Number of bytes of host memory used -host_seconds 1883.94 # Real time elapsed on the host -host_tick_rate 59987309 # Simulator tick rate (ticks/s) +sim_seconds 0.090885 # Number of seconds simulated +sim_ticks 90884909500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 375574812 # Number of instructions simulated -sim_seconds 0.113013 # Number of seconds simulated -sim_ticks 113012733500 # Number of ticks simulated +host_inst_rate 96810 # Simulator instruction rate (inst/s) +host_tick_rate 23426991 # Simulator tick rate (ticks/s) +host_mem_usage 252820 # Number of bytes of host memory used +host_seconds 3879.50 # Real time elapsed on the host +sim_insts 375574794 # Number of instructions simulated +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 105630800 # DTB read hits +system.cpu.dtb.read_misses 100510 # DTB read misses +system.cpu.dtb.read_acv 48612 # DTB read access violations +system.cpu.dtb.read_accesses 105731310 # DTB read accesses +system.cpu.dtb.write_hits 79936147 # DTB write hits +system.cpu.dtb.write_misses 1547 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 79937694 # DTB write accesses +system.cpu.dtb.data_hits 185566947 # DTB hits +system.cpu.dtb.data_misses 102057 # DTB misses +system.cpu.dtb.data_acv 48612 # DTB access violations +system.cpu.dtb.data_accesses 185669004 # DTB accesses +system.cpu.itb.fetch_hits 58326026 # ITB hits +system.cpu.itb.fetch_misses 337 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 58326363 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.numCycles 181769821 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 57225452 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 33446848 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3610875 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 40879451 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 32187006 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 30270394 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 39807126 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1409 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 5223677 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 31927422 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 56786170 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 11422526 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 5219312 # The number of times a branch was mispredicted -system.cpu.commit.branches 44587533 # Number of branches committed -system.cpu.commit.bw_lim_events 16035403 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 398664587 # The number of committed instructions +system.cpu.BPredUnit.usedRAS 10725194 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1200 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 60337386 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 506200677 # Number of instructions fetch has processed +system.cpu.fetch.Branches 57225452 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42912200 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 94142068 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13173843 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 17624322 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 179 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7572 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 58326026 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1118192 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 181648006 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.786712 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.242035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 87505938 48.17% 48.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8084169 4.45% 52.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9812284 5.40% 58.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6556715 3.61% 61.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13799395 7.60% 69.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9400037 5.17% 74.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5907170 3.25% 77.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3477374 1.91% 79.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 37104924 20.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 181648006 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.314824 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.784844 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 66587043 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13622871 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 88021771 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3884112 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9532209 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 10337474 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4322 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 494122650 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12073 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9532209 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 71008708 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4690007 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 394366 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 87374252 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8648464 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 480990212 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 42769 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7153610 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 312500874 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 630714726 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 332574792 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 298139934 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 52968555 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38325 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 292 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 23912108 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 111095455 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 85873017 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14526105 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8463039 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 435543273 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 257 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 420425800 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1773859 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 58536245 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 32877731 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 42 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 181648006 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.314508 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.994579 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 45216412 24.89% 24.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 30232996 16.64% 41.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 28617209 15.75% 57.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25676408 14.14% 71.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 23156698 12.75% 84.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15699012 8.64% 92.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7807681 4.30% 97.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3971496 2.19% 99.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1270094 0.70% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 181648006 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 135221 1.15% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 39442 0.34% 1.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 7017 0.06% 1.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 13904 0.12% 1.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 2001949 17.09% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 880826 7.52% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5776712 49.33% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2855706 24.39% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 164795138 39.20% 39.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2124451 0.51% 39.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 34088388 8.11% 47.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8064196 1.92% 49.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3086941 0.73% 50.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16853454 4.01% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1579988 0.38% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 108302425 25.76% 80.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 81497238 19.38% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 420425800 # Type of FU issued +system.cpu.iq.rate 2.312957 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11710777 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.027855 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 685991050 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 291244200 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 242469849 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 349993192 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 202862270 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 165589366 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 253586541 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 178516455 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13913922 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 16340969 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 171857 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 26790 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12352289 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 176199 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 9532209 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2220194 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 306578 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 461167180 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2274758 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 111095455 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 85873017 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 257 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 130 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 26790 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3503569 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 569738 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4073307 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 411738121 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 105779948 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 8687679 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 25623650 # number of nop insts executed +system.cpu.iew.exec_refs 185717662 # number of memory reference insts executed +system.cpu.iew.exec_branches 48391334 # Number of branches executed +system.cpu.iew.exec_stores 79937714 # Number of stores executed +system.cpu.iew.exec_rate 2.265162 # Inst execution rate +system.cpu.iew.wb_sent 409282340 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 408059215 # cumulative count of insts written-back +system.cpu.iew.wb_producers 198971045 # num instructions producing a value +system.cpu.iew.wb_consumers 279819296 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 2.244923 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.711070 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 62502516 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 56265161 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 216073988 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.845037 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.480996 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3606605 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 172115797 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.316258 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.838436 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 99774969 46.18% 46.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 35667629 16.51% 62.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 19281907 8.92% 71.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 16238513 7.52% 79.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11569134 5.35% 84.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7732170 3.58% 88.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5922846 2.74% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3851417 1.78% 92.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16035403 7.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 71294232 41.42% 41.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 26334848 15.30% 56.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15061233 8.75% 65.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13435550 7.81% 73.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8560921 4.97% 78.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6120977 3.56% 81.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5034670 2.93% 84.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3342912 1.94% 86.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22930454 13.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 216073988 # Number of insts commited each cycle -system.cpu.commit.count 398664587 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 172115797 # Number of insts commited each cycle +system.cpu.commit.count 398664569 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 168275214 # Number of memory references committed +system.cpu.commit.loads 94754486 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 44587530 # Number of branches committed system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. +system.cpu.commit.int_insts 316365825 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.int_insts 316365844 # Number of committed integer instructions. -system.cpu.commit.loads 94754489 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.refs 168275218 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 375574812 # Number of Instructions Simulated -system.cpu.committedInsts_total 375574812 # Number of Instructions Simulated -system.cpu.cpi 0.601812 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.601812 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 93199835 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33131.956912 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31878.172589 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 93198164 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 55363500 # number of ReadReq miss cycles +system.cpu.commit.bw_lim_events 22930454 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 610349451 # The number of ROB reads +system.cpu.rob.rob_writes 931879411 # The number of ROB writes +system.cpu.timesIdled 2704 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 121815 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 375574794 # Number of Instructions Simulated +system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated +system.cpu.cpi 0.483978 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.483978 # CPI: Total CPI of All Threads +system.cpu.ipc 2.066211 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.066211 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 410939724 # number of integer regfile reads +system.cpu.int_regfile_writes 176360806 # number of integer regfile writes +system.cpu.fp_regfile_reads 160541736 # number of floating regfile reads +system.cpu.fp_regfile_writes 106688075 # number of floating regfile writes +system.cpu.misc_regfile_reads 350572 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.icache.replacements 2140 # number of replacements +system.cpu.icache.tagsinuse 1834.625402 # Cycle average of tags in use +system.cpu.icache.total_refs 58320710 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4067 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14339.982788 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1834.625402 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.895813 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 58320710 # number of ReadReq hits +system.cpu.icache.demand_hits 58320710 # number of demand (read+write) hits +system.cpu.icache.overall_hits 58320710 # number of overall hits +system.cpu.icache.ReadReq_misses 5316 # number of ReadReq misses +system.cpu.icache.demand_misses 5316 # number of demand (read+write) misses +system.cpu.icache.overall_misses 5316 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 168223000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 168223000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 168223000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 58326026 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 58326026 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 58326026 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 31644.657637 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 31644.657637 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 31644.657637 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 1249 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1249 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1249 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 4067 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 4067 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 4067 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 123582000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 123582000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 123582000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000070 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000070 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000070 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 30386.525695 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 30386.525695 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 30386.525695 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 788 # number of replacements +system.cpu.dcache.tagsinuse 3295.374104 # Cycle average of tags in use +system.cpu.dcache.total_refs 165040256 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4187 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 39417.304992 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 3295.374104 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.804535 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 91538987 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 73501262 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 165040249 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 165040249 # number of overall hits +system.cpu.dcache.ReadReq_misses 1683 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 19466 # number of WriteReq misses +system.cpu.dcache.demand_misses 21149 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 21149 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 56075000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 568706500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 624781500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 624781500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 91540670 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 73520728 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 165061398 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 165061398 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1671 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 686 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 31400000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 30218.957186 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35474.663747 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73502931 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 537837000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000242 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 17798 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 14601 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 113412500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3197 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 39861.573171 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate 0.000265 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33318.478907 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 29215.375527 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 29541.893234 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 29541.893234 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 166720564 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30468.976321 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34627.570540 # average overall mshr miss latency -system.cpu.dcache.demand_hits 166701095 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 593200500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses -system.cpu.dcache.demand_misses 19469 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 15287 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 144812500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.writebacks 662 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 689 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 16273 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 16962 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 16962 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 994 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 3193 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 4187 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 4187 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 31676000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 113165000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 144841000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 144841000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4182 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 3293.121210 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.803985 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 166720564 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30468.976321 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34627.570540 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 166701095 # number of overall hits -system.cpu.dcache.overall_miss_latency 593200500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses -system.cpu.dcache.overall_misses 19469 # number of overall misses -system.cpu.dcache.overall_mshr_hits 15287 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 144812500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4182 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 786 # number of replacements -system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31867.203219 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35441.590980 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34593.026033 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34593.026033 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3293.121210 # Cycle average of tags in use -system.cpu.dcache.total_refs 166701099 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 664 # number of writebacks -system.cpu.decode.BlockedCycles 5613634 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 4438 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 10679460 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 490538381 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 118863884 # Number of cycles decode is idle -system.cpu.decode.RunCycles 90994213 # Number of cycles decode is running -system.cpu.decode.SquashCycles 9813191 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 13275 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 602257 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 183645342 # DTB accesses -system.cpu.dtb.data_acv 48603 # DTB access violations -system.cpu.dtb.data_hits 183566296 # DTB hits -system.cpu.dtb.data_misses 79046 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 103678274 # DTB read accesses -system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_hits 103600815 # DTB read hits -system.cpu.dtb.read_misses 77459 # DTB read misses -system.cpu.dtb.write_accesses 79967068 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 79965481 # DTB write hits -system.cpu.dtb.write_misses 1587 # DTB write misses -system.cpu.fetch.Branches 56786170 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 58423687 # Number of cache lines fetched -system.cpu.fetch.Cycles 93710532 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1318185 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 502037270 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 304 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 5229387 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.251238 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 58423687 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 41692920 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.221154 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 225887179 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.222513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.113255 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 132176647 58.51% 58.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 9507177 4.21% 62.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 8947595 3.96% 66.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6461834 2.86% 69.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13588400 6.02% 75.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8169586 3.62% 79.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6674990 2.96% 82.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2889669 1.28% 83.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 37471281 16.59% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 225887179 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 159270832 # number of floating regfile reads -system.cpu.fp_regfile_writes 104392422 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 58423687 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 32309.424084 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 30830.816483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 58418912 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 154277500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000082 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4775 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 868 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120456000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000067 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3907 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 14952.370617 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 58423687 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 32309.424084 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 30830.816483 # average overall mshr miss latency -system.cpu.icache.demand_hits 58418912 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 154277500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000082 # miss rate for demand accesses -system.cpu.icache.demand_misses 4775 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 868 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120456000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000067 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3907 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1823.959859 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.890605 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 58423687 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 32309.424084 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 30830.816483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 58418912 # number of overall hits -system.cpu.icache.overall_miss_latency 154277500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000082 # miss rate for overall accesses -system.cpu.icache.overall_misses 4775 # number of overall misses -system.cpu.icache.overall_mshr_hits 868 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120456000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000067 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3907 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1986 # number of replacements -system.cpu.icache.sampled_refs 3907 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1823.959859 # Cycle average of tags in use -system.cpu.icache.total_refs 58418912 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 138291 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 5625617 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 48687009 # Number of branches executed -system.cpu.iew.exec_nop 26082950 # number of nop insts executed -system.cpu.iew.exec_rate 1.805331 # Inst execution rate -system.cpu.iew.exec_refs 183693980 # number of memory reference insts executed -system.cpu.iew.exec_stores 79967080 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 1911401 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 106982646 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 6012421 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 86376940 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 454930236 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 103726900 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9802128 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 408050842 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 63 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 51 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9813191 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 192371 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 10208559 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 208520 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 5629 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 192417 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 12228157 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 12856211 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 5629 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 886790 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4738827 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 258989364 # num instructions consuming a value -system.cpu.iew.wb_count 404042671 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.726642 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 188192474 # num instructions producing a value -system.cpu.iew.wb_rate 1.787598 # insts written-back per cycle -system.cpu.iew.wb_sent 405020447 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 406883956 # number of integer regfile reads -system.cpu.int_regfile_writes 173490032 # number of integer regfile writes -system.cpu.ipc 1.661648 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.661648 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 165161738 39.53% 39.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2124398 0.51% 40.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 40.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33524704 8.02% 48.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7711996 1.85% 49.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2967896 0.71% 50.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16674434 3.99% 54.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1571336 0.38% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105669831 25.29% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 82413056 19.72% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 417852970 # Type of FU issued -system.cpu.iq.fp_alu_accesses 175354000 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 344883249 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 164390765 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 192579711 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 10358398 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024790 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4298 0.04% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 768 0.01% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 7 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 10130 0.10% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1743113 16.83% 16.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 627758 6.06% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5427565 52.40% 75.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2544759 24.57% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 252823787 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 727796795 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 239651906 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 283872417 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 428847047 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 417852970 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 47599271 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 728527 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 28893091 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 225887179 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.849830 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.928832 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 80384230 35.59% 35.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 40475639 17.92% 53.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 30160734 13.35% 66.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 26305410 11.65% 78.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21278104 9.42% 87.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14868616 6.58% 94.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9130443 4.04% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2370545 1.05% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 913458 0.40% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 225887179 # Number of insts issued each cycle -system.cpu.iq.rate 1.848699 # Inst issue rate -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 58423991 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 58423687 # ITB hits -system.cpu.itb.fetch_misses 304 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 3201 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.558495 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31458.559133 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 64 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 108554500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.980006 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 3137 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 98685500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980006 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 3137 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 4888 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34349.065531 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31163.354625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 661 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 145193500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.864771 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4227 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 131727500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864771 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4227 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 664 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 664 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.153637 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 10 # number of replacements +system.cpu.l2cache.tagsinuse 4007.918811 # Cycle average of tags in use +system.cpu.l2cache.total_refs 828 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.170827 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 3630.264414 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 377.654397 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.110787 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.011525 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 755 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 662 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 62 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 817 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 817 # number of overall hits +system.cpu.l2cache.ReadReq_misses 4306 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 3131 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 7437 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 7437 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 148211500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 108422000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 256633500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 256633500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 5061 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 662 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 3193 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 8254 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8254 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.850820 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.980583 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.901018 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.901018 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34419.763121 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34628.553178 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34507.664381 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34507.664381 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8089 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34457.903313 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31289.109180 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 725 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 253748000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.910372 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7364 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 230413000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.910372 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7364 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 3557.826949 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 379.777727 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.108576 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011590 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 8089 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34457.903313 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31289.109180 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 725 # number of overall hits -system.cpu.l2cache.overall_miss_latency 253748000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.910372 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7364 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 230413000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.910372 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7364 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 4306 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 7437 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 7437 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 14 # number of replacements -system.cpu.l2cache.sampled_refs 4771 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 134349000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 98553500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 232902500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 232902500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.850820 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980583 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.901018 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.901018 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31200.418021 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31476.684765 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31316.727175 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31316.727175 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3937.604676 # Cycle average of tags in use -system.cpu.l2cache.total_refs 733 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 7819910 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6085624 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 106982646 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 86376940 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 350572 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.numCycles 226025470 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 3360184 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 259532333 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 311 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 122116498 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 1529212 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 625408393 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 477751875 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 306658733 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 88296359 # Number of cycles rename is running -system.cpu.rename.SquashCycles 9813191 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 1960754 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 47126400 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 292973848 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 332434545 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 340193 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 36156 # count of serializing insts renamed -system.cpu.rename.skidInsts 5383709 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 253 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 654965356 # The number of ROB reads -system.cpu.rob.rob_writes 919674888 # The number of ROB writes -system.cpu.timesIdled 3011 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini index b2f50f12f..00bbabd01 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/30.eon/ref/arm/linux/o3-timing/simerr index 0de362399..bf930ad43 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simerr +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simerr @@ -1,5 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout index 62ab94a46..fb668f921 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout @@ -1,16 +1,10 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 19:29:23 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 9 2011 02:03:43 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -18,5 +12,5 @@ Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.110000 -Exiting @ tick 117852123500 because target called exit() +OO-style eon Time= 0.100000 +Exiting @ tick 108112565000 because target called exit() diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt index 48dd38840..467f5453a 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.117852 # Number of seconds simulated -sim_ticks 117852123500 # Number of ticks simulated +sim_seconds 0.108113 # Number of seconds simulated +sim_ticks 108112565000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49475 # Simulator instruction rate (inst/s) -host_tick_rate 16703679 # Simulator tick rate (ticks/s) -host_mem_usage 264264 # Number of bytes of host memory used -host_seconds 7055.46 # Real time elapsed on the host -sim_insts 349066258 # Number of instructions simulated +host_inst_rate 68175 # Simulator instruction rate (inst/s) +host_tick_rate 21114970 # Simulator tick rate (ticks/s) +host_mem_usage 266872 # Number of bytes of host memory used +host_seconds 5120.19 # Real time elapsed on the host +sim_insts 349066124 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,103 +51,106 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 235704248 # number of cpu cycles simulated +system.cpu.numCycles 216225131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 37732885 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20795463 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3471100 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 27302215 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 21001151 # Number of BTB hits +system.cpu.BPredUnit.lookups 38871530 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21265030 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3261176 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 27909151 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 21653043 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 7420100 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 72463 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 39991725 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 328152707 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37732885 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 28421251 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 76800425 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3608252 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 39991725 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 624732 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 235576888 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.817631 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.040837 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 7689864 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 61658 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 44557213 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 344579360 # Number of instructions fetch has processed +system.cpu.fetch.Branches 38871530 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 29342907 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80636459 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11681756 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 82619379 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 192 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 42088076 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 916191 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 216112788 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.095569 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.185948 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 159366483 67.65% 67.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 9270231 3.94% 71.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5914286 2.51% 74.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6643493 2.82% 76.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5462624 2.32% 79.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4799627 2.04% 81.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3754754 1.59% 82.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4137731 1.76% 84.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36227659 15.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 136175266 63.01% 63.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 9565429 4.43% 67.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6238703 2.89% 70.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6748883 3.12% 73.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5364932 2.48% 75.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4989535 2.31% 78.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3875216 1.79% 80.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4307528 1.99% 82.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 38847296 17.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 235576888 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.160086 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.392222 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 84492760 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 69387883 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 73181829 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1548924 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6965492 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7488186 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 73175 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 420043685 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 215754 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6965492 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 90152933 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 976284 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 57875196 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 69216447 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10390536 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 409431138 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 10006 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5114847 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 42 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 449313195 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2409887049 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1322854173 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1087032876 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384568949 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 64744241 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3898927 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3897858 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35694607 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106772052 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 90018438 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11281294 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21363407 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384862513 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3813526 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 372770888 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1408906 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 37984896 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 125485450 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 258042 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 235576888 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.582375 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.822791 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 216112788 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.179773 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.593614 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 53033788 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 77116773 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 73749422 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3985890 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8226915 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7647714 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 72935 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 439814331 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 207402 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8226915 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 61196526 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1203573 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 59638529 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 69748798 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 16098447 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 424223689 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 22825 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 9278494 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 99 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 462213475 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2492907388 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1378161419 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1114745969 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384568743 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 77644727 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3986897 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4043470 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 51924156 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 109846529 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 95332472 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14399866 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29809960 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 399729408 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3865767 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 378419662 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1473555 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 54144389 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 177169340 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 310299 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 216112788 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.751029 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.895618 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 95699423 40.62% 40.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 48065676 20.40% 61.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 27569248 11.70% 72.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20762200 8.81% 81.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21955543 9.32% 90.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12942689 5.49% 96.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5977724 2.54% 98.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1956925 0.83% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 647460 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82036681 37.96% 37.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 39071702 18.08% 56.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 28236809 13.07% 69.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20423013 9.45% 78.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 23529038 10.89% 89.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 13145418 6.08% 95.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6683366 3.09% 98.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2232223 1.03% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 754538 0.35% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 235576888 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 216112788 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2414 0.02% 0.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2198 0.02% 0.02% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5043 0.04% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available @@ -167,181 +170,181 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.06% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 11301 0.09% 0.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 9996 0.08% 0.14% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 197 0.00% 0.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 1510 0.01% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 142649 1.07% 1.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 1224 0.01% 1.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 303363 2.28% 3.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7115466 53.58% 57.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5697057 42.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 2604 0.02% 0.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 194 0.00% 0.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 114242 0.95% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 418 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 276715 2.30% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7458735 61.87% 65.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4186007 34.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126467737 33.93% 33.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2147032 0.58% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6836061 1.83% 36.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8620472 2.31% 38.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3526603 0.95% 39.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1580695 0.42% 40.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21030277 5.64% 45.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7283358 1.95% 47.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7262499 1.95% 49.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102234129 27.43% 77.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85606734 22.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 130620873 34.52% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2147251 0.57% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 20 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6800768 1.80% 36.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8475274 2.24% 39.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3501119 0.93% 40.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1584837 0.42% 40.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21128819 5.58% 46.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7289356 1.93% 47.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7313976 1.93% 49.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175288 0.05% 49.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 102741469 27.15% 77.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 86640612 22.90% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 372770888 # Type of FU issued -system.cpu.iq.rate 1.581520 # Inst issue rate -system.cpu.iq.fu_busy_cnt 13280227 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035626 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 746488455 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 293551634 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 247041034 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249319342 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 133204458 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118172579 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 258240891 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 127810224 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4605348 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 378419662 # Type of FU issued +system.cpu.iq.rate 1.750119 # Inst issue rate +system.cpu.iq.fu_busy_cnt 12056154 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.031859 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 736575285 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 322046718 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 251010826 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249906536 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 135772025 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118653498 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262435143 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128040673 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5198793 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12123008 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25231 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 199737 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7642570 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 15197510 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2287 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 168315 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12956623 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 301 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 168 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 309 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6965492 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10869 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 480 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 388723243 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6854795 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106772052 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 90018438 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3802280 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 54 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 341 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 199737 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3305937 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 361135 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3667072 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 368528754 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101011008 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4242134 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8226915 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 19822 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 465 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 403642432 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2591477 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 109846529 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 95332472 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3854525 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 191 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 168315 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3199953 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 312751 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3512704 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 372398400 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101298405 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6021262 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 47204 # number of nop insts executed -system.cpu.iew.exec_refs 185554303 # number of memory reference insts executed -system.cpu.iew.exec_branches 31933479 # Number of branches executed -system.cpu.iew.exec_stores 84543295 # Number of stores executed -system.cpu.iew.exec_rate 1.563522 # Inst execution rate -system.cpu.iew.wb_sent 365991200 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 365213613 # cumulative count of insts written-back -system.cpu.iew.wb_producers 165367337 # num instructions producing a value -system.cpu.iew.wb_consumers 317313225 # num instructions consuming a value +system.cpu.iew.exec_nop 47257 # number of nop insts executed +system.cpu.iew.exec_refs 186410418 # number of memory reference insts executed +system.cpu.iew.exec_branches 32413413 # Number of branches executed +system.cpu.iew.exec_stores 85112013 # Number of stores executed +system.cpu.iew.exec_rate 1.722272 # Inst execution rate +system.cpu.iew.wb_sent 370241650 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 369664324 # cumulative count of insts written-back +system.cpu.iew.wb_producers 175377527 # num instructions producing a value +system.cpu.iew.wb_consumers 344318453 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.549457 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.521149 # average fanout of values written-back +system.cpu.iew.wb_rate 1.709627 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.509347 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 349066870 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 39653224 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3555484 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3440231 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 228611397 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.526901 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.127678 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 349066736 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 54571176 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3555468 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 3230397 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 207885874 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.679127 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.249386 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102653839 44.90% 44.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 52967573 23.17% 68.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 21494828 9.40% 77.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 16426131 7.19% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11610822 5.08% 89.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6946497 3.04% 92.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3261718 1.43% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2914745 1.27% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10335244 4.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 88802662 42.72% 42.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 47260336 22.73% 65.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19727320 9.49% 74.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 15331284 7.37% 82.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11254360 5.41% 87.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7570851 3.64% 91.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3388756 1.63% 93.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3248763 1.56% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11301542 5.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 228611397 # Number of insts commited each cycle -system.cpu.commit.count 349066870 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 207885874 # Number of insts commited each cycle +system.cpu.commit.count 349066736 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177024911 # Number of memory references committed -system.cpu.commit.loads 94649043 # Number of loads committed +system.cpu.commit.refs 177024867 # Number of memory references committed +system.cpu.commit.loads 94649018 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30521922 # Number of branches committed +system.cpu.commit.branches 30521897 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279586109 # Number of committed integer instructions. +system.cpu.commit.int_insts 279586001 # Number of committed integer instructions. system.cpu.commit.function_calls 6225114 # Number of function calls committed. -system.cpu.commit.bw_lim_events 10335244 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 11301542 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 606993724 # The number of ROB reads -system.cpu.rob.rob_writes 784416922 # The number of ROB writes -system.cpu.timesIdled 2785 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 127360 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 349066258 # Number of Instructions Simulated -system.cpu.committedInsts_total 349066258 # Number of Instructions Simulated -system.cpu.cpi 0.675242 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.675242 # CPI: Total CPI of All Threads -system.cpu.ipc 1.480950 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.480950 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1759160975 # number of integer regfile reads -system.cpu.int_regfile_writes 232094825 # number of integer regfile writes -system.cpu.fp_regfile_reads 189729002 # number of floating regfile reads -system.cpu.fp_regfile_writes 134274190 # number of floating regfile writes -system.cpu.misc_regfile_reads 986066945 # number of misc regfile reads -system.cpu.misc_regfile_writes 34422257 # number of misc regfile writes -system.cpu.icache.replacements 13781 # number of replacements -system.cpu.icache.tagsinuse 1824.800983 # Cycle average of tags in use -system.cpu.icache.total_refs 39975644 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15643 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2555.497283 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 600219721 # The number of ROB reads +system.cpu.rob.rob_writes 815506085 # The number of ROB writes +system.cpu.timesIdled 2585 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 112343 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 349066124 # Number of Instructions Simulated +system.cpu.committedInsts_total 349066124 # Number of Instructions Simulated +system.cpu.cpi 0.619439 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.619439 # CPI: Total CPI of All Threads +system.cpu.ipc 1.614364 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.614364 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1775936880 # number of integer regfile reads +system.cpu.int_regfile_writes 235580324 # number of integer regfile writes +system.cpu.fp_regfile_reads 189945628 # number of floating regfile reads +system.cpu.fp_regfile_writes 134544688 # number of floating regfile writes +system.cpu.misc_regfile_reads 1009447373 # number of misc regfile reads +system.cpu.misc_regfile_writes 34422229 # number of misc regfile writes +system.cpu.icache.replacements 14157 # number of replacements +system.cpu.icache.tagsinuse 1842.318723 # Cycle average of tags in use +system.cpu.icache.total_refs 42071371 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16032 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2624.212263 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1824.800983 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.891016 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 39975644 # number of ReadReq hits -system.cpu.icache.demand_hits 39975644 # number of demand (read+write) hits -system.cpu.icache.overall_hits 39975644 # number of overall hits -system.cpu.icache.ReadReq_misses 16081 # number of ReadReq misses -system.cpu.icache.demand_misses 16081 # number of demand (read+write) misses -system.cpu.icache.overall_misses 16081 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 189840000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 189840000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 189840000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 39991725 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 39991725 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 39991725 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000402 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000402 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000402 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 11805.235993 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 11805.235993 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 11805.235993 # average overall miss latency +system.cpu.icache.occ_blocks::0 1842.318723 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.899570 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 42071371 # number of ReadReq hits +system.cpu.icache.demand_hits 42071371 # number of demand (read+write) hits +system.cpu.icache.overall_hits 42071371 # number of overall hits +system.cpu.icache.ReadReq_misses 16705 # number of ReadReq misses +system.cpu.icache.demand_misses 16705 # number of demand (read+write) misses +system.cpu.icache.overall_misses 16705 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 202344500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 202344500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 202344500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 42088076 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 42088076 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 42088076 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000397 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000397 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000397 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 12112.810536 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 12112.810536 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 12112.810536 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,142 +354,142 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 435 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 435 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 435 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 15646 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 15646 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 15646 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 669 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 669 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 669 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 16036 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 16036 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 16036 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 131146500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 131146500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 131146500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 136366000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 136366000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 136366000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000391 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000391 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000391 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8382.110444 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8382.110444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8382.110444 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000381 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000381 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000381 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8503.741581 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8503.741581 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8503.741581 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1396 # number of replacements -system.cpu.dcache.tagsinuse 3097.520126 # Cycle average of tags in use -system.cpu.dcache.total_refs 178371323 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4582 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38928.704278 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1406 # number of replacements +system.cpu.dcache.tagsinuse 3100.332801 # Cycle average of tags in use +system.cpu.dcache.total_refs 178043182 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4595 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38747.156039 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3097.520126 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.756230 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 96315033 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 82033723 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 11410 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 11146 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 178348756 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 178348756 # number of overall hits -system.cpu.dcache.ReadReq_misses 3256 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 18976 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 3100.332801 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.756917 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 95986293 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 82033252 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 12491 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 11132 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 178019545 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 178019545 # number of overall hits +system.cpu.dcache.ReadReq_misses 3385 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 19442 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 22232 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 22232 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 108888000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 618616000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 22827 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 22827 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 112128500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 646930500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 727504000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 727504000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 96318289 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 11412 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 11146 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 178370988 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 178370988 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000034 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000231 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000175 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000125 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33442.260442 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 32599.915683 # average WriteReq miss latency +system.cpu.dcache.demand_miss_latency 759059000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 759059000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 95989678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 82052694 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 12493 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 11132 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 178042372 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 178042372 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000035 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.000237 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000160 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33125.110783 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33274.894558 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 32723.281756 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 32723.281756 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 33252.683226 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33252.683226 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 288500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 308500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26227.272727 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28045.454545 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1019 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1507 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 16140 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 1025 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1630 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 16598 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 17647 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 17647 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1749 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 2836 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4585 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4585 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 18228 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 18228 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1755 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 2844 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 4599 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 4599 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 54106000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 100544000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 154650000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 154650000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 53650500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 101058500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 154709000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 154709000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30935.391652 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35452.750353 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33729.552890 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33729.552890 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30570.085470 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35533.931083 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33639.704284 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33639.704284 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 54 # number of replacements -system.cpu.l2cache.tagsinuse 3793.062863 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13102 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5236 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.502292 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 59 # number of replacements +system.cpu.l2cache.tagsinuse 3910.187993 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13367 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5367 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.490591 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3424.878969 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 368.183894 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.104519 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011236 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 13017 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1019 # number of Writeback hits +system.cpu.l2cache.occ_blocks::0 3537.549748 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 372.638245 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.107957 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.011372 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 13284 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1025 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 17 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 13034 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 13034 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4374 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 2816 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7190 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7190 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 150210000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 96886500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 247096500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 247096500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 17391 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1019 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 2833 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 20224 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 20224 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.251509 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_hits 13301 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 13301 # number of overall hits +system.cpu.l2cache.ReadReq_misses 4501 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 2824 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 7325 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 7325 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 154458500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 97367500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 251826000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 251826000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 17785 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1025 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 2841 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 20626 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 20626 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.253078 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.993999 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.355518 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.355518 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34341.563786 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34405.717330 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34366.689847 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34366.689847 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate 0.994016 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.355134 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.355134 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34316.485226 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34478.576487 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34378.976109 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34378.976109 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -496,31 +499,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 51 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4323 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 2816 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7139 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7139 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 54 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 4447 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 2824 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 7271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 7271 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 134686000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 88056000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 222742000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 222742000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 138555000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 88338500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 226893500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 226893500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.248577 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250042 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993999 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.352996 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.352996 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31155.678927 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994016 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.352516 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.352516 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.959748 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31269.886364 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31200.728393 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31200.728393 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31281.338527 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.267501 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.267501 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |