diff options
Diffstat (limited to 'tests/long/30.eon/ref')
14 files changed, 426 insertions, 572 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 7d8c8259e..29e352b0e 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out index 96829f8a9..c04c0d11b 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out @@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index bca3fa536..ce046cea7 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 36573856 # Number of BTB hits -global.BPredUnit.BTBLookups 48300104 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1110 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 6040473 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 37489973 # Number of conditional branches predicted -global.BPredUnit.lookups 66376995 # Number of BP lookups -global.BPredUnit.usedRAS 13616030 # Number of times the RAS was used to get a target. -host_inst_rate 78938 # Simulator instruction rate (inst/s) -host_mem_usage 153528 # Number of bytes of host memory used -host_seconds 4757.83 # Real time elapsed on the host -host_tick_rate 66128 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 89962751 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 64024234 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 131935591 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 95765344 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 38358431 # Number of BTB hits +global.BPredUnit.BTBLookups 50162851 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1146 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 6112182 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 38942362 # Number of conditional branches predicted +global.BPredUnit.lookups 68824046 # Number of BP lookups +global.BPredUnit.usedRAS 14094584 # Number of times the RAS was used to get a target. +host_inst_rate 88313 # Simulator instruction rate (inst/s) +host_mem_usage 157144 # Number of bytes of host memory used +host_seconds 4252.75 # Real time elapsed on the host +host_tick_rate 26084457 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 79078987 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 58020753 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 131723270 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 96432918 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 375574675 # Number of instructions simulated -sim_seconds 0.000315 # Number of seconds simulated -sim_ticks 314625027 # Number of ticks simulated -system.cpu.commit.COM:branches 44587523 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 13381546 # number cycles where commit BW limit reached +sim_insts 375574812 # Number of instructions simulated +sim_seconds 0.110931 # Number of seconds simulated +sim_ticks 110930737500 # Number of ticks simulated +system.cpu.commit.COM:branches 44587533 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 15191652 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 276331431 +system.cpu.commit.COM:committed_per_cycle.samples 203296876 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 148231465 5364.26% - 1 40756250 1474.90% - 2 28135615 1018.18% - 3 18140880 656.49% - 4 10622787 384.42% - 5 8112500 293.58% - 6 5544405 200.64% - 7 3405983 123.26% - 8 13381546 484.26% + 0 83055980 4085.45% + 1 37801777 1859.44% + 2 20090473 988.23% + 3 18525905 911.27% + 4 11216575 551.73% + 5 8853752 435.51% + 6 5489461 270.02% + 7 3071301 151.07% + 8 15191652 747.26% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 398664447 # Number of instructions committed -system.cpu.commit.COM:loads 100651988 # Number of loads committed +system.cpu.commit.COM:count 398664587 # Number of instructions committed +system.cpu.commit.COM:loads 100651995 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 174183388 # Number of memory references committed +system.cpu.commit.COM:refs 174183397 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 6036288 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 398664447 # The number of committed instructions +system.cpu.commit.branchMispredicts 6107953 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 398664587 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 118579541 # The number of squashed insts skipped by commit -system.cpu.committedInsts 375574675 # Number of Instructions Simulated -system.cpu.committedInsts_total 375574675 # Number of Instructions Simulated -system.cpu.cpi 0.837716 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.837716 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 96374626 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5603.456853 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5219.612576 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 96372656 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11038810 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1970 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 984 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5146538 # number of ReadReq MSHR miss cycles +system.cpu.commit.commitSquashedInsts 122897297 # The number of squashed insts skipped by commit +system.cpu.committedInsts 375574812 # Number of Instructions Simulated +system.cpu.committedInsts_total 375574812 # Number of Instructions Simulated +system.cpu.cpi 0.590725 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.590725 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 96817111 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4478.552279 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3669.007021 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 96815619 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 6682000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1492 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 495 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3658000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 986 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 6647.641993 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6867.316020 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73501543 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 127528364 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 19184 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 15988 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 21947942 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_misses 997 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 4580.037179 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3751.017852 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73511046 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 44348500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000132 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 9683 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6490 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 11977000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3196 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 2800 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 3193 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40620.324964 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 19 # number of cycles access was blocked +system.cpu.dcache.avg_refs 40650.755370 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 53200 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 169895353 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 6550.400586 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 6478.833094 # average overall mshr miss latency -system.cpu.dcache.demand_hits 169874199 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 138567174 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000125 # miss rate for demand accesses -system.cpu.dcache.demand_misses 21154 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 16972 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 27094480 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 170337840 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4566.487696 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3731.503580 # average overall mshr miss latency +system.cpu.dcache.demand_hits 170326665 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 51030500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000066 # miss rate for demand accesses +system.cpu.dcache.demand_misses 11175 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6985 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 15635000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4190 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 169895353 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 6550.400586 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 6478.833094 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 170337840 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4566.487696 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3731.503580 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 169874199 # number of overall hits -system.cpu.dcache.overall_miss_latency 138567174 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000125 # miss rate for overall accesses -system.cpu.dcache.overall_misses 21154 # number of overall misses -system.cpu.dcache.overall_mshr_hits 16972 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 27094480 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 170326665 # number of overall hits +system.cpu.dcache.overall_miss_latency 51030500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000066 # miss rate for overall accesses +system.cpu.dcache.overall_misses 11175 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6985 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 15635000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4190 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 786 # number of replacements -system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 787 # number of replacements +system.cpu.dcache.sampled_refs 4190 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3211.654167 # Cycle average of tags in use -system.cpu.dcache.total_refs 169874199 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3304.118717 # Cycle average of tags in use +system.cpu.dcache.total_refs 170326665 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 639 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 32658535 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4257 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 11810746 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 562730439 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 143183566 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 99541453 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 18560140 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 12611 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 947878 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 66376995 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 68531131 # Number of cache lines fetched -system.cpu.fetch.Cycles 171584130 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1722712 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 577337575 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6483468 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.225089 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 68531131 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 50189886 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.957796 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 642 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 19129336 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4391 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 12122968 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 582055742 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 80258799 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 100428895 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 18564601 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 12469 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 3479847 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 68824046 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 70113587 # Number of cache lines fetched +system.cpu.fetch.Cycles 177754526 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1413 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 605291130 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 6551564 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.310212 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 70113587 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 52453015 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.728239 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 294891572 +system.cpu.fetch.rateDist.samples 221861478 system.cpu.fetch.rateDist.min_value 0 - 0 191838575 6505.39% - 1 8000057 271.29% - 2 8353997 283.29% - 3 6793291 230.37% - 4 15387795 521.81% - 5 8442060 286.28% - 6 8794810 298.24% - 7 2528585 85.75% - 8 44752402 1517.59% + 0 114220541 5148.28% + 1 8239331 371.37% + 2 8549373 385.35% + 3 6969058 314.12% + 4 16046109 723.25% + 5 8875051 400.03% + 6 9195050 414.45% + 7 2819832 127.10% + 8 46947133 2116.06% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 68531131 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4689.224645 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3850.973049 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 68526132 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 23441434 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000073 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4999 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1103 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 15003391 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000057 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 70113587 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3851.773227 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2889.186432 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 70109583 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15422500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000057 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4004 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 83 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11328500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000056 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3921 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 17588.842916 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 17880.536343 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 68531131 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4689.224645 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3850.973049 # average overall mshr miss latency -system.cpu.icache.demand_hits 68526132 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 23441434 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000073 # miss rate for demand accesses -system.cpu.icache.demand_misses 4999 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1103 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15003391 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000057 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 70113587 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3851.773227 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2889.186432 # average overall mshr miss latency +system.cpu.icache.demand_hits 70109583 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15422500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000057 # miss rate for demand accesses +system.cpu.icache.demand_misses 4004 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 83 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11328500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000056 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3921 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 68531131 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4689.224645 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3850.973049 # average overall mshr miss latency +system.cpu.icache.overall_accesses 70113587 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3851.773227 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2889.186432 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 68526132 # number of overall hits -system.cpu.icache.overall_miss_latency 23441434 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000073 # miss rate for overall accesses -system.cpu.icache.overall_misses 4999 # number of overall misses -system.cpu.icache.overall_mshr_hits 1103 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15003391 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000057 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses +system.cpu.icache.overall_hits 70109583 # number of overall hits +system.cpu.icache.overall_miss_latency 15422500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000057 # miss rate for overall accesses +system.cpu.icache.overall_misses 4004 # number of overall misses +system.cpu.icache.overall_mshr_hits 83 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11328500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000056 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3921 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1976 # number of replacements -system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1998 # number of replacements +system.cpu.icache.sampled_refs 3921 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1786.777118 # Cycle average of tags in use -system.cpu.icache.total_refs 68526132 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1828.295849 # Cycle average of tags in use +system.cpu.icache.total_refs 70109583 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 19733456 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 52475714 # Number of branches executed -system.cpu.iew.EXEC:nop 28200659 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.439607 # Inst execution rate -system.cpu.iew.EXEC:refs 190729803 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 78992420 # Number of stores executed +system.cpu.idleCycles -2 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 52992725 # Number of branches executed +system.cpu.iew.EXEC:nop 29946505 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.944645 # Inst execution rate +system.cpu.iew.EXEC:refs 194719104 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 80042784 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 302582293 # num instructions consuming a value -system.cpu.iew.WB:count 419651187 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.683002 # average fanout of values written-back +system.cpu.iew.WB:consumers 297392817 # num instructions consuming a value +system.cpu.iew.WB:count 427980775 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.704330 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 206664160 # num instructions producing a value -system.cpu.iew.WB:rate 1.423069 # insts written-back per cycle -system.cpu.iew.WB:sent 420984328 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6525670 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4581779 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 131935591 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 243 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 8433935 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 95765344 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 517242480 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 111737383 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7591261 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 424527920 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 366722 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 209462789 # num instructions producing a value +system.cpu.iew.WB:rate 1.929045 # insts written-back per cycle +system.cpu.iew.WB:sent 430386834 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6770153 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2285856 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 131723270 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 248 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 6165269 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 96432918 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 521561792 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 114676320 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 13198323 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 431441879 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 131901 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 32377 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 18560140 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 737234 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 25295 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 18564601 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 554549 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 8882 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 8984961 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 39727 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 10646448 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 56371 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 675434 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 175954 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 31283603 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 22233944 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 675434 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1009222 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5516448 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.193722 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.193722 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 432119181 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 636490 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 215134 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 31071275 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 22901516 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 636490 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1000963 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5769190 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.692835 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.692835 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 444640202 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 33581 0.01% # Type of FU issued - IntAlu 171100299 39.60% # Type of FU issued - IntMult 2148839 0.50% # Type of FU issued + IntAlu 177043734 39.82% # Type of FU issued + IntMult 2204532 0.50% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 35472672 8.21% # Type of FU issued - FloatCmp 7906658 1.83% # Type of FU issued - FloatCvt 2966336 0.69% # Type of FU issued - FloatMult 16725823 3.87% # Type of FU issued - FloatDiv 1566508 0.36% # Type of FU issued + FloatAdd 36105087 8.12% # Type of FU issued + FloatCmp 7997969 1.80% # Type of FU issued + FloatCvt 3013999 0.68% # Type of FU issued + FloatMult 17176525 3.86% # Type of FU issued + FloatDiv 1578480 0.36% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 113251606 26.21% # Type of FU issued - MemWrite 80946859 18.73% # Type of FU issued + MemRead 116850777 26.28% # Type of FU issued + MemWrite 82635518 18.58% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 9237965 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.021378 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 12556872 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.028241 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 31984 0.35% # attempts to use FU when none available + IntAlu 57761 0.46% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 74124 0.80% # attempts to use FU when none available - FloatCmp 35886 0.39% # attempts to use FU when none available - FloatCvt 5384 0.06% # attempts to use FU when none available - FloatMult 1393766 15.09% # attempts to use FU when none available - FloatDiv 1142138 12.36% # attempts to use FU when none available + FloatAdd 28133 0.22% # attempts to use FU when none available + FloatCmp 21849 0.17% # attempts to use FU when none available + FloatCvt 3461 0.03% # attempts to use FU when none available + FloatMult 3478872 27.70% # attempts to use FU when none available + FloatDiv 916669 7.30% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 5413419 58.60% # attempts to use FU when none available - MemWrite 1141264 12.35% # attempts to use FU when none available + MemRead 6621449 52.73% # attempts to use FU when none available + MemWrite 1428678 11.38% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 294891572 +system.cpu.iq.ISSUE:issued_per_cycle.samples 221861478 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 116554693 3952.46% - 1 58404803 1980.55% - 2 49059967 1663.66% - 3 31805455 1078.55% - 4 23494336 796.71% - 5 9548381 323.79% - 6 4038173 136.94% - 7 1656320 56.17% - 8 329444 11.17% + 0 66879354 3014.46% + 1 37689855 1698.80% + 2 36617552 1650.47% + 3 29239458 1317.92% + 4 27293259 1230.19% + 5 13755301 620.00% + 6 5789291 260.94% + 7 3467682 156.30% + 8 1129726 50.92% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.465349 # Inst issue rate -system.cpu.iq.iqInstsAdded 489041578 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 432119181 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 243 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 113088119 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1629891 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 97430194 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 8078 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4922.926872 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2406.841240 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 721 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 36217973 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.910745 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 7357 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 17707131 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.910745 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 7357 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 639 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 639 # number of Writeback hits +system.cpu.iq.ISSUE:rate 2.004134 # Inst issue rate +system.cpu.iq.iqInstsAdded 491615039 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 444640202 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 248 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 114649126 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1134366 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 83844967 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 8108 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3327.551159 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1909.064236 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 729 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 24554000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.910089 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 7379 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 14086985 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.910089 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 7379 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 642 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 642 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.184858 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.185798 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8078 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4922.926872 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2406.841240 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 721 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 36217973 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.910745 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7357 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 8108 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3327.551159 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1909.064236 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 729 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 24554000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.910089 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7379 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17707131 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.910745 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7357 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 14086985 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.910089 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7379 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8717 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4922.926872 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2406.841240 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 8750 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3327.551159 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1909.064236 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1360 # number of overall hits -system.cpu.l2cache.overall_miss_latency 36217973 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.843983 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7357 # number of overall misses +system.cpu.l2cache.overall_hits 1371 # number of overall hits +system.cpu.l2cache.overall_miss_latency 24554000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.843314 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7379 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17707131 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.843983 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7357 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 14086985 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.843314 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7379 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -383,31 +383,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 7357 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 7379 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6462.850486 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1360 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 6669.459869 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1371 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 294891572 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14686909 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 259532206 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2446116 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 148616326 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 11769281 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 32 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 721460314 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 549210935 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 355537016 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 94743971 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 18560140 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 15563294 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 96004810 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 2720932 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 38133 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 34543353 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 264 # count of temporary serializing insts renamed -system.cpu.timesIdled 6492 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.numCycles 221861478 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 6569281 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 259532333 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1971772 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 86889182 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 8681438 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 731270765 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 559458182 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 360795698 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 96896401 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 18564601 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 12635219 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 101263365 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 306794 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 37801 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 32486829 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 267 # count of temporary serializing insts renamed +system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout index 039e2d4ce..68b00def4 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.000000 +OO-style eon Time= 0.100000 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini index 088cd1a9f..ba3b61431 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -53,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -74,7 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic egid=100 env= euid=100 @@ -100,14 +59,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out index bec900d0f..de3317258 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -49,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -57,51 +55,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt index a308f5e36..3892be109 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 841426 # Simulator instruction rate (inst/s) -host_mem_usage 147172 # Number of bytes of host memory used -host_seconds 473.80 # Real time elapsed on the host -host_tick_rate 841425 # Simulator tick rate (ticks/s) +host_inst_rate 844104 # Simulator instruction rate (inst/s) +host_mem_usage 151076 # Number of bytes of host memory used +host_seconds 472.29 # Real time elapsed on the host +host_tick_rate 422051705 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 398664450 # Number of instructions simulated -sim_seconds 0.000399 # Number of seconds simulated -sim_ticks 398664449 # Number of ticks simulated +sim_insts 398664597 # Number of instructions simulated +sim_seconds 0.199332 # Number of seconds simulated +sim_ticks 199332298000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 398664450 # number of cpu cycles simulated -system.cpu.num_insts 398664450 # Number of instructions executed -system.cpu.num_refs 174183390 # Number of memory references +system.cpu.numCycles 398664597 # number of cpu cycles simulated +system.cpu.num_insts 398664597 # Number of instructions executed +system.cpu.num_refs 174183399 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr index 1d6957eca..4bb0d9bbe 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr @@ -1,9 +1,11 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data +warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout index 039e2d4ce..5f057b8dd 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.000000 +OO-style eon Time= 0.183333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index 452538e49..bc260bf15 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -182,11 +156,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin output=cout diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out index 602da9705..0a9655414 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -27,11 +24,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -50,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -179,23 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index 328856ce7..552adff15 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 689508 # Simulator instruction rate (inst/s) -host_mem_usage 185012 # Number of bytes of host memory used -host_seconds 578.19 # Real time elapsed on the host -host_tick_rate 1033135 # Simulator tick rate (ticks/s) +host_inst_rate 557007 # Simulator instruction rate (inst/s) +host_mem_usage 156576 # Number of bytes of host memory used +host_seconds 715.73 # Real time elapsed on the host +host_tick_rate 396092779 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 398664450 # Number of instructions simulated -sim_seconds 0.000597 # Number of seconds simulated -sim_ticks 597346012 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 94754482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3956.610526 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2956.610526 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 94753532 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3758780 # number of ReadReq miss cycles +sim_insts 398664597 # Number of instructions simulated +sim_seconds 0.283494 # Number of seconds simulated +sim_ticks 283494379000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3630.526316 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2630.526316 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 94753539 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3449000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2808780 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2499000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3940.471580 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2940.471580 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73517525 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 12617390 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3618.988132 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2618.988132 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73517527 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 11588000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 9415390 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8386000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40527.711224 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40527.713391 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 168275209 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3944.164258 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency -system.cpu.dcache.demand_hits 168271057 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 16376170 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3621.628131 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2621.628131 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168271066 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 15037000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 12224170 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10885000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 168275209 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3944.164258 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 168271057 # number of overall hits -system.cpu.dcache.overall_miss_latency 16376170 # number of overall miss cycles +system.cpu.dcache.overall_accesses 168275218 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3621.628131 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2621.628131 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 168271066 # number of overall hits +system.cpu.dcache.overall_miss_latency 15037000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_misses 4152 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 12224170 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10885000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,54 +76,54 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3222.413784 # Cycle average of tags in use -system.cpu.dcache.total_refs 168271057 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3289.772430 # Cycle average of tags in use +system.cpu.dcache.total_refs 168271066 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 625 # number of writebacks -system.cpu.icache.ReadReq_accesses 398664451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3820.906097 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.906097 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 398660777 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 14038009 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 398664598 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3633.814321 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2633.814321 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 398660925 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13347000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 3674 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10364009 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 9674000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3674 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 108508.649156 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 108538.231691 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 398664451 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3820.906097 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency -system.cpu.icache.demand_hits 398660777 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 14038009 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 398664598 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3633.814321 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2633.814321 # average overall mshr miss latency +system.cpu.icache.demand_hits 398660925 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13347000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses -system.cpu.icache.demand_misses 3674 # number of demand (read+write) misses +system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10364009 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 9674000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3674 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 398664451 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3820.906097 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 398660777 # number of overall hits -system.cpu.icache.overall_miss_latency 14038009 # number of overall miss cycles +system.cpu.icache.overall_accesses 398664598 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3633.814321 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2633.814321 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 398660925 # number of overall hits +system.cpu.icache.overall_miss_latency 13347000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses -system.cpu.icache.overall_misses 3674 # number of overall misses +system.cpu.icache.overall_misses 3673 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10364009 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 9674000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3674 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -135,60 +135,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1770 # number of replacements -system.cpu.icache.sampled_refs 3674 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1769 # number of replacements +system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1765.882838 # Cycle average of tags in use -system.cpu.icache.total_refs 398660777 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1795.510184 # Cycle average of tags in use +system.cpu.icache.total_refs 398660925 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 7826 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2983.265505 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.984530 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 7825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2707.276275 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1705.023697 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 21404930 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.916816 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 7175 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13811764 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916816 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 7175 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 19422000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.916805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 7174 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12231840 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 7174 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.177840 # Average number of references to valid blocks. +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.177865 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 7826 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2983.265505 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2707.276275 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1705.023697 # average overall mshr miss latency system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 21404930 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.916816 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7175 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 19422000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.916805 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7174 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 13811764 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.916816 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7175 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 12231840 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.916805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7174 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8451 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2983.265505 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_accesses 8450 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2707.276275 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1705.023697 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1276 # number of overall hits -system.cpu.l2cache.overall_miss_latency 21404930 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.849012 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7175 # number of overall misses +system.cpu.l2cache.overall_miss_latency 19422000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.848994 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7174 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13811764 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.849012 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7175 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 12231840 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.848994 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -201,16 +201,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 7175 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 7174 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6344.042673 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 6483.699084 # Cycle average of tags in use system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 597346012 # number of cpu cycles simulated -system.cpu.num_insts 398664450 # Number of instructions executed -system.cpu.num_refs 174183390 # Number of memory references +system.cpu.numCycles 283494379000 # number of cpu cycles simulated +system.cpu.num_insts 398664597 # Number of instructions executed +system.cpu.num_refs 174183399 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr index 8534c55aa..4bb0d9bbe 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr @@ -1,10 +1,11 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data +warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout index 039e2d4ce..1e8a0ac6f 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.000000 +OO-style eon Time= 0.283333 |