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-rw-r--r--tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini4
-rwxr-xr-xtests/long/30.eon/ref/arm/linux/simple-atomic/simout10
-rw-r--r--tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt32
-rw-r--r--tests/long/30.eon/ref/arm/linux/simple-timing/config.ini2
-rwxr-xr-xtests/long/30.eon/ref/arm/linux/simple-timing/simout8
-rw-r--r--tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt32
6 files changed, 68 insertions, 20 deletions
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
index 0795e438f..ac380ff0f 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -52,12 +52,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
index fa8b8a100..f5391da34 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 24 2010 15:34:40
-M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
-M5 started Aug 24 2010 15:34:42
-M5 executing on zizzer
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
+M5 compiled Oct 11 2010 18:37:23
+M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
+M5 started Oct 11 2010 19:19:59
+M5 executing on aus-bc3-b4
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
index dc953ce33..4b61fce38 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -1,16 +1,28 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2356342 # Simulator instruction rate (inst/s)
-host_mem_usage 210592 # Number of bytes of host memory used
-host_seconds 146.32 # Real time elapsed on the host
-host_tick_rate 1436586032 # Simulator tick rate (ticks/s)
+host_inst_rate 2280191 # Simulator instruction rate (inst/s)
+host_mem_usage 262416 # Number of bytes of host memory used
+host_seconds 151.21 # Real time elapsed on the host
+host_tick_rate 1390158822 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 344777955 # Number of instructions simulated
sim_seconds 0.210200 # Number of seconds simulated
sim_ticks 210200321500 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@@ -19,8 +31,20 @@ system.cpu.dtb.write_hits 0 # DT
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
index ff00126d1..3b627362e 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/eon
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
index 691b24bb3..26d019ac6 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Sep 20 2010 15:04:50
-M5 revision 0c4a7d867247 7686 default qtip print-identical tip
-M5 started Sep 20 2010 15:12:46
-M5 executing on phenom
+M5 compiled Oct 11 2010 18:37:23
+M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
+M5 started Oct 11 2010 19:23:59
+M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
index 0a058648f..9ac8b63de 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1114146 # Simulator instruction rate (inst/s)
-host_mem_usage 205224 # Number of bytes of host memory used
-host_seconds 309.12 # Real time elapsed on the host
-host_tick_rate 1701065680 # Simulator tick rate (ticks/s)
+host_inst_rate 520438 # Simulator instruction rate (inst/s)
+host_mem_usage 270128 # Number of bytes of host memory used
+host_seconds 661.75 # Real time elapsed on the host
+host_tick_rate 794599336 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 344399678 # Number of instructions simulated
sim_seconds 0.525826 # Number of seconds simulated
@@ -74,8 +74,20 @@ system.cpu.dcache.total_refs 176645818 # To
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 998 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@@ -139,8 +151,20 @@ system.cpu.icache.warmup_cycle 0 # Cy
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses