diff options
Diffstat (limited to 'tests/long/40.perlbmk/ref/alpha/linux')
10 files changed, 3030 insertions, 4972 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini index c3a59fbce..81e1071eb 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -53,352 +51,49 @@ mem_mode=atomic physmem=system.physmem [system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 +type=AtomicSimpleCPU +children=workload clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 +cpu_id=0 defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -predType=tournament -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 +phase=0 +progress_interval=0 +simulate_stalls=false system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 +width=1 workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=262144 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=131072 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.l2cache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=2097152 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=perlbmk -I. -I lib lgred.makerand.pl +cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-atomic +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 -port=system.physmem.port system.cpu.l2cache.mem_side +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory @@ -409,6 +104,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out index f491a3081..e5012d953 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out @@ -19,345 +19,48 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=perlbmk -I. -I lib lgred.makerand.pl +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-atomic system=system - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] -type=DerivO3CPU -clock=1 -numThreads=1 -activity=0 -workload=system.cpu.workload -mem=system.cpu.dcache -checker=null +type=AtomicSimpleCPU max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 defer_registration=false +width=1 function_trace=false function_trace_start=0 - -[system.cpu.icache] -type=BaseCache -size=131072 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.l2cache] -type=BaseCache -size=2097152 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 +simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +99,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt index 5d4f9235a..f553125a6 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,1974 +1,18 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +host_inst_rate 906784 # Simulator instruction rate (inst/s) +host_mem_usage 147280 # Number of bytes of host memory used +host_seconds 2215.51 # Real time elapsed on the host +host_tick_rate 906784 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 -system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +sim_insts 2008987724 # Number of instructions simulated +sim_seconds 0.002009 # Number of seconds simulated +sim_ticks 2008987723 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 2008987724 # number of cpu cycles simulated +system.cpu.num_insts 2008987724 # Number of instructions executed +system.cpu.num_refs 722390480 # Number of memory references +system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr index 8893caac8..9135960d0 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr @@ -1,3 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 +warn: ignoring syscall sigprocmask(1, 0, ...) diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout index fbb329a2f..d4a078b85 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout @@ -1,13 +1,1376 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +1375000: 2038431008 +1374000: 3487365506 +1373000: 4184770123 +1372000: 1943746837 +1371000: 2651673663 +1370000: 1493817016 +1369000: 2894014801 +1368000: 1932092157 +1367000: 1670009799 +1366000: 828662248 +1365000: 1816650195 +1364000: 4173139012 +1363000: 3990577549 +1362000: 1330366815 +1361000: 3316935553 +1360000: 961300001 +1359000: 344963924 +1358000: 1930356625 +1357000: 1640964266 +1356000: 3777883312 +1355000: 1651132665 +1354000: 1971433151 +1353000: 3024027448 +1352000: 1956387036 +1351000: 1490224841 +1350000: 3286956460 +1349000: 2793131848 +1348000: 2529224907 +1347000: 2622295253 +1346000: 1414103189 +1345000: 3861617587 +1344000: 3506378216 +1343000: 1667466720 +1342000: 2899224065 +1341000: 1681491556 +1340000: 1076311729 +1339000: 4066972664 +1338000: 3438059028 +1337000: 2938359730 +1336000: 1214615378 +1335000: 3814432458 +1334000: 2944038793 +1333000: 3428045644 +1332000: 2815822229 +1331000: 1093465585 +1330000: 3012217108 +1329000: 2230916791 +1328000: 208547885 +1327000: 3592585825 +1326000: 3948677052 +1325000: 1817805162 +1324000: 135366494 +1323000: 3309148112 +1322000: 1685035744 +1321000: 3293068577 +1320000: 4097808567 +1319000: 1594097274 +1318000: 2607196971 +1317000: 1763785306 +1316000: 2157394178 +1315000: 2399031328 +1314000: 2954547004 +1313000: 82348686 +1312000: 3120930785 +1311000: 2192747320 +1310000: 1580299400 +1309000: 4085061477 +1308000: 3627048345 +1307000: 3756533178 +1306000: 77997329 +1305000: 1343359499 +1304000: 1124031730 +1303000: 1161755432 +1302000: 1855858423 +1301000: 3985872257 +1300000: 3188250811 +1299000: 3621615933 +1298000: 962624248 +1297000: 447138785 +1296000: 1459144309 +1295000: 3454504226 +1294000: 2154913347 +1293000: 2356291788 +1292000: 458348817 +1291000: 3639562699 +1290000: 3596847973 +1289000: 117168222 +1288000: 3531023849 +1287000: 3135920051 +1286000: 234987844 +1285000: 2048767180 +1284000: 2437301839 +1283000: 522886780 +1282000: 2274133042 +1281000: 1415703448 +1280000: 4145574054 +1279000: 4283494580 +1278000: 3305365779 +1277000: 604711974 +1276000: 2031548723 +1275000: 1809515149 +1274000: 1664703088 +1273000: 4149809153 +1272000: 4045608138 +1271000: 1687605659 +1270000: 1292294527 +1269000: 3120968162 +1268000: 3502898850 +1267000: 371380256 +1266000: 1683884245 +1265000: 1849576817 +1264000: 1559050991 +1263000: 66820972 +1262000: 4023539201 +1261000: 3452295398 +1260000: 4188778026 +1259000: 2008091854 +1258000: 2691158394 +1257000: 2030818206 +1256000: 2715523403 +1255000: 3473414015 +1254000: 138826953 +1253000: 69386516 +1252000: 1174725971 +1251000: 4130510373 +1250000: 1649788328 +1249000: 1589122801 +1248000: 1108688101 +1247000: 2906355484 +1246000: 379539929 +1245000: 914026021 +1244000: 4074858468 +1243000: 505989635 +1242000: 2487288773 +1241000: 1991248111 +1240000: 2415456875 +1239000: 2571192525 +1238000: 2897090536 +1237000: 2761178989 +1236000: 1296601829 +1235000: 594696756 +1234000: 264562726 +1233000: 3630852367 +1232000: 1605618457 +1231000: 2857419452 +1230000: 3028672437 +1229000: 361833758 +1228000: 4046013938 +1227000: 1031775583 +1226000: 3475227831 +1225000: 802168737 +1224000: 3819194009 +1223000: 851157666 +1222000: 2656457905 +1221000: 2579045204 +1220000: 2091024410 +1219000: 4070633834 +1218000: 1926611791 +1217000: 1903813761 +1216000: 3107168794 +1215000: 2975081979 +1214000: 4097089273 +1213000: 328943233 +1212000: 2912404803 +1211000: 181334180 +1210000: 863898367 +1209000: 1894902343 +1208000: 1531985231 +1207000: 1412503751 +1206000: 662457490 +1205000: 3447925432 +1204000: 2320889638 +1203000: 303282255 +1202000: 1568632659 +1201000: 1108711074 +1200000: 953936964 +1199000: 3576987258 +1198000: 466163300 +1197000: 1159551420 +1196000: 529807534 +1195000: 1528979627 +1194000: 1795576953 +1193000: 2050917610 +1192000: 4068219994 +1191000: 3573497288 +1190000: 776005286 +1189000: 2643125982 +1188000: 2240857507 +1187000: 43353719 +1186000: 2474198261 +1185000: 1711347056 +1184000: 3046018343 +1183000: 664346074 +1182000: 3532392595 +1181000: 3145347726 +1180000: 2203928246 +1179000: 4275910811 +1178000: 3260065240 +1177000: 3216083720 +1176000: 3588515377 +1175000: 1432542416 +1174000: 173159992 +1173000: 4115057268 +1172000: 223456174 +1171000: 1192164227 +1170000: 2059254624 +1169000: 279921804 +1168000: 1100495449 +1167000: 264813624 +1166000: 2839280440 +1165000: 301796904 +1164000: 1331933822 +1163000: 647427882 +1162000: 3872813324 +1161000: 2231068824 +1160000: 4222672618 +1159000: 3629229584 +1158000: 2262586804 +1157000: 2837951671 +1156000: 1780662312 +1155000: 31553143 +1154000: 3230861653 +1153000: 1991458597 +1152000: 2277829165 +1151000: 3864184029 +1150000: 630158826 +1149000: 4028889917 +1148000: 1662505287 +1147000: 4121796538 +1146000: 3215277282 +1145000: 2019794999 +1144000: 4124433286 +1143000: 181819953 +1142000: 2704380222 +1141000: 2487909897 +1140000: 1753570204 +1139000: 2337507591 +1138000: 3235449912 +1137000: 3819353806 +1136000: 3435413746 +1135000: 3288196653 +1134000: 2705083758 +1133000: 997301031 +1132000: 1871866706 +1131000: 2298991521 +1130000: 1516060457 +1129000: 3393393053 +1128000: 2795526466 +1127000: 1177801041 +1126000: 4226698729 +1125000: 567826718 +1124000: 2425735007 +1123000: 1090360485 +1122000: 2508061782 +1121000: 3476086116 +1120000: 2952087827 +1119000: 2238445545 +1118000: 2937037425 +1117000: 1773353797 +1116000: 3033333765 +1115000: 3086246055 +1114000: 944390435 +1113000: 2944932895 +1112000: 534683663 +1111000: 2002175399 +1110000: 1876265996 +1109000: 4148000592 +1108000: 3857174625 +1107000: 843045539 +1106000: 307772960 +1105000: 4161975075 +1104000: 3675447412 +1103000: 1232242543 +1102000: 1019583281 +1101000: 1983565552 +1100000: 2490901544 +1099000: 2990982808 +1098000: 1586955629 +1097000: 1629138000 +1096000: 1870655270 +1095000: 2201093764 +1094000: 696079363 +1093000: 1526904315 +1092000: 553848190 +1091000: 4234411636 +1090000: 1027439894 +1089000: 1319115149 +1088000: 1147708285 +1087000: 3364503693 +1086000: 528432422 +1085000: 3289100476 +1084000: 3074065438 +1083000: 3664250869 +1082000: 2950591670 +1081000: 4207904839 +1080000: 3425353965 +1079000: 1069646286 +1078000: 1004956209 +1077000: 2642475281 +1076000: 364759474 +1075000: 2334969932 +1074000: 3907002684 +1073000: 273633783 +1072000: 4113182592 +1071000: 1404306188 +1070000: 3286171051 +1069000: 3531039414 +1068000: 4147513318 +1067000: 2466290219 +1066000: 2089005579 +1065000: 2617563073 +1064000: 3124838472 +1063000: 3731008114 +1062000: 4154022628 +1061000: 3389258714 +1060000: 3915149371 +1059000: 2280932986 +1058000: 2872952978 +1057000: 2381277834 +1056000: 1236179469 +1055000: 3256417375 +1054000: 2700213407 +1053000: 3418122897 +1052000: 3130247908 +1051000: 1897033028 +1050000: 2349143738 +1049000: 3789736749 +1048000: 409522147 +1047000: 3149279018 +1046000: 1323133366 +1045000: 3881472077 +1044000: 3363874422 +1043000: 3931657349 +1042000: 1220007174 +1041000: 3634450249 +1040000: 695184634 +1039000: 529508167 +1038000: 449827627 +1037000: 2817424280 +1036000: 1613482057 +1035000: 2632612792 +1034000: 852422020 +1033000: 4098325966 +1032000: 177298753 +1031000: 2286807874 +1030000: 2745349553 +1029000: 2387386570 +1028000: 2004317534 +1027000: 971343564 +1026000: 1583732447 +1025000: 2340780818 +1024000: 561110245 +1023000: 3012020895 +1022000: 1677066870 +1021000: 3046208682 +1020000: 2695506079 +1019000: 780536149 +1018000: 4225713741 +1017000: 420500410 +1016000: 3642094643 +1015000: 608695027 +1014000: 2161592269 +1013000: 930784800 +1012000: 1924051276 +1011000: 1889733886 +1010000: 1476038251 +1009000: 2908577467 +1008000: 2584082136 +1007000: 1713214537 +1006000: 3374346754 +1005000: 1173203719 +1004000: 1142288559 +1003000: 4195961973 +1002000: 1211260974 +1001000: 474231127 +1000000: 3967090782 +999000: 1543103493 +998000: 1018646803 +997000: 1799037982 +996000: 3416426509 +995000: 3581729971 +994000: 3044504127 +993000: 2975704335 +992000: 280018795 +991000: 330300280 +990000: 3557016064 +989000: 3856724468 +988000: 2124201285 +987000: 3683893247 +986000: 3331663795 +985000: 1980057740 +984000: 2908437859 +983000: 4074086941 +982000: 1162307093 +981000: 3855413476 +980000: 2799155731 +979000: 2477822501 +978000: 497762075 +977000: 1650233426 +976000: 3061573902 +975000: 2224673611 +974000: 868725340 +973000: 1630206962 +972000: 2549398924 +971000: 602424332 +970000: 1172502721 +969000: 2923795552 +968000: 1394164637 +967000: 1088479837 +966000: 898709052 +965000: 3983150961 +964000: 2463803866 +963000: 4181117626 +962000: 2151137820 +961000: 1342513757 +960000: 1507689687 +959000: 3652624918 +958000: 4169721124 +957000: 531022334 +956000: 3161389505 +955000: 1197637232 +954000: 2927231791 +953000: 2552305374 +952000: 2988512039 +951000: 2448639370 +950000: 3560951660 +949000: 948988399 +948000: 2488188856 +947000: 2804177113 +946000: 1991587461 +945000: 2480044082 +944000: 1954588624 +943000: 924231798 +942000: 3269047595 +941000: 2078696579 +940000: 2822989969 +939000: 2295885951 +938000: 1815612561 +937000: 4182254074 +936000: 2753223967 +935000: 2840201908 +934000: 4058383142 +933000: 4270167260 +932000: 1203124158 +931000: 3039861400 +930000: 4247472610 +929000: 2297661055 +928000: 2376159704 +927000: 3861417958 +926000: 1968685250 +925000: 1156966624 +924000: 3568580529 +923000: 866582344 +922000: 2263113297 +921000: 3643523016 +920000: 3252268544 +919000: 2413309783 +918000: 3463124619 +917000: 3965291932 +916000: 1309181143 +915000: 2321282614 +914000: 2286584604 +913000: 3271924727 +912000: 1719841316 +911000: 3966124343 +910000: 607707072 +909000: 61942114 +908000: 903881820 +907000: 4136948835 +906000: 3663861210 +905000: 3251888710 +904000: 227984688 +903000: 495030333 +902000: 863290992 +901000: 3297482717 +900000: 3821175085 +899000: 1679874522 +898000: 2033358728 +897000: 3495513776 +896000: 1613181881 +895000: 1729312232 +894000: 2171317375 +893000: 2508603694 +892000: 151095866 +891000: 1926096901 +890000: 4292888210 +889000: 2716307666 +888000: 737310728 +887000: 4172392976 +886000: 2322084662 +885000: 1034961047 +884000: 665072958 +883000: 368014441 +882000: 1914585160 +881000: 3836900884 +880000: 2073827187 +879000: 1650543625 +878000: 3581099222 +877000: 147580905 +876000: 4009421518 +875000: 3294244820 +874000: 2786720968 +873000: 1682434702 +872000: 620473876 +871000: 742752376 +870000: 385116650 +869000: 3882475387 +868000: 4259210265 +867000: 1329675866 +866000: 539876515 +865000: 2761681036 +864000: 2192063038 +863000: 1512848001 +862000: 3911973718 +861000: 399349760 +860000: 1449497249 +859000: 4241714042 +858000: 18611709 +857000: 1550083097 +856000: 3322762748 +855000: 283796511 +854000: 227907270 +853000: 3162559866 +852000: 1331946455 +851000: 2328467927 +850000: 1640242501 +849000: 3390154083 +848000: 22088346 +847000: 636412590 +846000: 1550672808 +845000: 763937899 +844000: 430123910 +843000: 3413971543 +842000: 900018421 +841000: 3295874222 +840000: 2470678073 +839000: 821401909 +838000: 3923898844 +837000: 429069328 +836000: 2030779868 +835000: 464625222 +834000: 3593024182 +833000: 3564354808 +832000: 2794783695 +831000: 97817593 +830000: 4197446076 +829000: 2367560230 +828000: 2180262123 +827000: 3149571964 +826000: 1364436763 +825000: 21599634 +824000: 448490256 +823000: 3775294409 +822000: 1132631425 +821000: 2046352434 +820000: 3380435217 +819000: 3672496486 +818000: 1634548077 +817000: 2881316258 +816000: 1808599559 +815000: 3298310748 +814000: 3744285741 +813000: 3540737709 +812000: 1143844515 +811000: 3091026783 +810000: 3771757792 +809000: 631375816 +808000: 1353831646 +807000: 3047756240 +806000: 818136890 +805000: 783072818 +804000: 3923416267 +803000: 3233085529 +802000: 674747602 +801000: 758523180 +800000: 2232308489 +799000: 2919643710 +798000: 623631722 +797000: 1302202741 +796000: 1083055596 +795000: 2358048936 +794000: 2836842068 +793000: 1612571734 +792000: 4243459584 +791000: 1585511173 +790000: 1493369943 +789000: 3649557715 +788000: 3223859588 +787000: 4001130195 +786000: 2949323631 +785000: 3887611007 +784000: 4091766333 +783000: 2954277998 +782000: 1281850218 +781000: 771664458 +780000: 2242576209 +779000: 3865479146 +778000: 1885013114 +777000: 2032659742 +776000: 4221167450 +775000: 1962824751 +774000: 209539683 +773000: 262945027 +772000: 452388820 +771000: 2006266573 +770000: 990063860 +769000: 1377951885 +768000: 4240978277 +767000: 2206801004 +766000: 258015097 +765000: 1990217201 +764000: 1336410303 +763000: 1004853228 +762000: 1404152873 +761000: 3356554358 +760000: 4052430907 +759000: 2833671166 +758000: 1561723151 +757000: 1752620777 +756000: 2622547462 +755000: 1843933196 +754000: 3728801998 +753000: 2776832730 +752000: 2626131293 +751000: 1528525830 +750000: 2716112581 +749000: 3306039713 +748000: 915271993 +747000: 4205133363 +746000: 3136321783 +745000: 1203154793 +744000: 3370017183 +743000: 4036456207 +742000: 3377556743 +741000: 3688568185 +740000: 3349738887 +739000: 1606411092 +738000: 331980874 +737000: 744409647 +736000: 3845688101 +735000: 3654026084 +734000: 786733128 +733000: 1938791337 +732000: 843210299 +731000: 622237260 +730000: 2851984401 +729000: 874906210 +728000: 485670931 +727000: 1522238607 +726000: 2167917076 +725000: 2304482464 +724000: 1053513779 +723000: 3535437378 +722000: 2842397393 +721000: 864490421 +720000: 920591184 +719000: 238249003 +718000: 400999105 +717000: 2476588521 +716000: 2501770197 +715000: 2307183887 +714000: 2461504446 +713000: 1055961242 +712000: 2112756603 +711000: 1691285107 +710000: 2318101701 +709000: 1113470660 +708000: 2880817109 +707000: 2105866601 +706000: 1441912219 +705000: 1684930572 +704000: 1652788290 +703000: 2359919145 +702000: 554008403 +701000: 3292620387 +700000: 3528106952 +699000: 3096375697 +698000: 4201459210 +697000: 1450879661 +696000: 3743939389 +695000: 3595614062 +694000: 4101634764 +693000: 364538097 +692000: 4204120947 +691000: 3706729229 +690000: 23134581 +689000: 2585120038 +688000: 488096133 +687000: 3437179533 +686000: 4233790378 +685000: 3093374794 +684000: 4054579709 +683000: 1275606548 +682000: 1966964511 +681000: 354765069 +680000: 3812578933 +679000: 781104418 +678000: 3281747368 +677000: 38547527 +676000: 1005246555 +675000: 74753563 +674000: 676561715 +673000: 1571462591 +672000: 1876054379 +671000: 1899005137 +670000: 4188106842 +669000: 1210903253 +668000: 2909261468 +667000: 3100970839 +666000: 758568698 +665000: 2456763236 +664000: 686978785 +663000: 349808361 +662000: 2804776250 +661000: 2660993423 +660000: 1758165672 +659000: 2116094507 +658000: 473425247 +657000: 563682488 +656000: 1454194093 +655000: 3211379305 +654000: 1298793267 +653000: 3374836733 +652000: 586356525 +651000: 1490379306 +650000: 2444980288 +649000: 47671514 +648000: 568687171 +647000: 452676234 +646000: 2752247721 +645000: 1473254180 +644000: 4189470166 +643000: 2619721788 +642000: 348627393 +641000: 675341258 +640000: 3183922211 +639000: 1266115377 +638000: 2331844572 +637000: 250721255 +636000: 4017517385 +635000: 1279621530 +634000: 1500904407 +633000: 2495457137 +632000: 1919479114 +631000: 1900388354 +630000: 370039669 +629000: 1207459690 +628000: 2314286843 +627000: 80099285 +626000: 2465533600 +625000: 1056979505 +624000: 4289445503 +623000: 1234007489 +622000: 2015973003 +621000: 2281387627 +620000: 1115405564 +619000: 1407699260 +618000: 3940256761 +617000: 3639431367 +616000: 3498942818 +615000: 2982957031 +614000: 3800830694 +613000: 1454837486 +612000: 158454584 +611000: 3414923339 +610000: 3752581462 +609000: 195868045 +608000: 3165948362 +607000: 2335822431 +606000: 3229210414 +605000: 1963422803 +604000: 2355005929 +603000: 2009365872 +602000: 1343084455 +601000: 2935056539 +600000: 2354171524 +599000: 3621510708 +598000: 3992266416 +597000: 682368260 +596000: 3290472265 +595000: 2215475388 +594000: 258049456 +593000: 365234760 +592000: 291875022 +591000: 3307168950 +590000: 2233802778 +589000: 1944100586 +588000: 7070250 +587000: 882601802 +586000: 1231725137 +585000: 4169259917 +584000: 2123453163 +583000: 631823798 +582000: 2039925673 +581000: 2238172862 +580000: 1479379031 +579000: 2363652063 +578000: 3186953219 +577000: 1893181853 +576000: 2598096173 +575000: 938779920 +574000: 927622241 +573000: 3105026014 +572000: 2412852365 +571000: 644810722 +570000: 3576393744 +569000: 2625468928 +568000: 2167447563 +567000: 3391359662 +566000: 3178493511 +565000: 24044406 +564000: 3298992941 +563000: 2054886551 +562000: 42479754 +561000: 2681525651 +560000: 1110769583 +559000: 2140540905 +558000: 780964175 +557000: 1320986796 +556000: 3624725635 +555000: 2920977559 +554000: 4017386186 +553000: 1800018968 +552000: 2137743255 +551000: 2282561617 +550000: 1466333871 +549000: 2567190002 +548000: 3280136825 +547000: 1761114084 +546000: 413841088 +545000: 829808286 +544000: 283842712 +543000: 3524860517 +542000: 1853927454 +541000: 3087398009 +540000: 2535138654 +539000: 2224833733 +538000: 1673737994 +537000: 3963575809 +536000: 289926670 +535000: 2411609896 +534000: 1866933324 +533000: 259728174 +532000: 786327819 +531000: 870136645 +530000: 3603849411 +529000: 1687141824 +528000: 2973109656 +527000: 2120372902 +526000: 3554894341 +525000: 369365218 +524000: 2336210870 +523000: 1352671703 +522000: 4093185231 +521000: 44309897 +520000: 1308207751 +519000: 1489447779 +518000: 497784082 +517000: 2370135551 +516000: 2393982064 +515000: 3453216376 +514000: 349616264 +513000: 1057922348 +512000: 2061823561 +511000: 2221803921 +510000: 2518047997 +509000: 2783356981 +508000: 3842023593 +507000: 3105321997 +506000: 3540124104 +505000: 334821209 +504000: 2867156116 +503000: 3824184936 +502000: 2432119674 +501000: 3759474841 +500000: 3381305904 +499000: 3106640260 +498000: 4241569809 +497000: 2499659818 +496000: 3971155346 +495000: 2297624439 +494000: 3455216298 +493000: 2152855317 +492000: 3915728702 +491000: 1087687366 +490000: 3976823873 +489000: 1813936857 +488000: 2803197060 +487000: 4026575712 +486000: 3867909271 +485000: 644795069 +484000: 1051897856 +483000: 3091023530 +482000: 558963440 +481000: 2516346710 +480000: 2405618228 +479000: 1595155902 +478000: 1699460683 +477000: 645434559 +476000: 1457238083 +475000: 101746166 +474000: 1054127445 +473000: 1703635926 +472000: 3228750510 +471000: 2570095523 +470000: 2671516672 +469000: 219569232 +468000: 245973042 +467000: 1785352151 +466000: 1828704556 +465000: 2993350381 +464000: 1802995474 +463000: 3689392931 +462000: 2612188341 +461000: 1970287287 +460000: 179729165 +459000: 1971694777 +458000: 3031333568 +457000: 844564594 +456000: 979968160 +455000: 2169589334 +454000: 2315813244 +453000: 2333801403 +452000: 27632567 +451000: 3752181065 +450000: 3965825733 +449000: 969798494 +448000: 1028884180 +447000: 1127216392 +446000: 2477366335 +445000: 3752023316 +444000: 1679036165 +443000: 4241934865 +442000: 3360200587 +441000: 3533494907 +440000: 1888455616 +439000: 2668699748 +438000: 2728196631 +437000: 31348508 +436000: 2192326452 +435000: 286955043 +434000: 4097630027 +433000: 1185622743 +432000: 2870795553 +431000: 2246074692 +430000: 14797454 +429000: 2606207217 +428000: 2143322684 +427000: 1289559127 +426000: 3922285071 +425000: 590638427 +424000: 1098669098 +423000: 1597510568 +422000: 1623191243 +421000: 558862770 +420000: 3846690181 +419000: 3187756225 +418000: 2520849981 +417000: 492022774 +416000: 1621927303 +415000: 2828836994 +414000: 2840605981 +413000: 4260845378 +412000: 2200645444 +411000: 393061550 +410000: 3334889686 +409000: 1926958198 +408000: 2939424440 +407000: 4207748941 +406000: 4155428743 +405000: 89797563 +404000: 427509452 +403000: 1154877029 +402000: 4023324583 +401000: 359413604 +400000: 964788206 +399000: 3843097093 +398000: 1871599521 +397000: 2361845870 +396000: 4103568192 +395000: 622493054 +394000: 954921337 +393000: 3664395297 +392000: 2429042528 +391000: 1361036260 +390000: 1944048082 +389000: 1452288555 +388000: 1619598577 +387000: 481096019 +386000: 3719595713 +385000: 1840199850 +384000: 421723640 +383000: 2976677668 +382000: 618336385 +381000: 1777037748 +380000: 901802032 +379000: 621392881 +378000: 3857241587 +377000: 3115040335 +376000: 3173790487 +375000: 2517831056 +374000: 4125976072 +373000: 2294107866 +372000: 4127359945 +371000: 333946663 +370000: 3307391606 +369000: 4268094300 +368000: 91056295 +367000: 882600429 +366000: 730521557 +365000: 3957048081 +364000: 2139992409 +363000: 3504327478 +362000: 2637042137 +361000: 2718540805 +360000: 903036675 +359000: 1858031956 +358000: 1868403889 +357000: 2677157063 +356000: 1865569815 +355000: 224528281 +354000: 3144318856 +353000: 1968806079 +352000: 2836077060 +351000: 1981309964 +350000: 3105869514 +349000: 3793296439 +348000: 1267294125 +347000: 1962520375 +346000: 2150839102 +345000: 3811064048 +344000: 1298671776 +343000: 2150950779 +342000: 3522997671 +341000: 1378798782 +340000: 2213936395 +339000: 2117978968 +338000: 2444486361 +337000: 3928234621 +336000: 1645335376 +335000: 540013781 +334000: 1103798645 +333000: 1723781016 +332000: 1805323374 +331000: 3590394804 +330000: 4178797476 +329000: 3350975600 +328000: 1556948383 +327000: 2282601074 +326000: 1709618426 +325000: 637957139 +324000: 2719080929 +323000: 1847444832 +322000: 547261068 +321000: 581409575 +320000: 586567018 +319000: 1579880779 +318000: 1049735969 +317000: 3233747918 +316000: 351376358 +315000: 3446473138 +314000: 2099035319 +313000: 2827833754 +312000: 2717063452 +311000: 2212978977 +310000: 1583494069 +309000: 3119642323 +308000: 2946038826 +307000: 167580491 +306000: 3916319765 +305000: 3480693946 +304000: 2709010304 +303000: 3265576420 +302000: 3439318492 +301000: 1896109937 +300000: 339896540 +299000: 313850585 +298000: 2600289987 +297000: 4060531515 +296000: 3894455718 +295000: 3183544633 +294000: 1551799240 +293000: 3574197425 +292000: 2380783887 +291000: 3130665581 +290000: 1135162832 +289000: 3460550191 +288000: 3366619355 +287000: 501626025 +286000: 1070097358 +285000: 1023235560 +284000: 925313877 +283000: 3758987940 +282000: 1935539406 +281000: 3727463323 +280000: 4040081802 +279000: 2462105177 +278000: 322183212 +277000: 2437872102 +276000: 1085894622 +275000: 2118601354 +274000: 1720719726 +273000: 56294175 +272000: 2046218040 +271000: 2871320919 +270000: 3111863367 +269000: 726835633 +268000: 916866344 +267000: 1208374677 +266000: 2914608557 +265000: 449456198 +264000: 2645640532 +263000: 997311800 +262000: 2872564998 +261000: 1964496124 +260000: 2802080932 +259000: 387636194 +258000: 3813984224 +257000: 1921258264 +256000: 1414333533 +255000: 997845727 +254000: 3671258247 +253000: 3244313331 +252000: 44297738 +251000: 1055697350 +250000: 403951609 +249000: 3558182356 +248000: 3441722116 +247000: 3598259825 +246000: 2495236386 +245000: 4150113079 +244000: 4092477475 +243000: 1352323466 +242000: 4228179784 +241000: 3509286314 +240000: 1117669666 +239000: 1821539001 +238000: 2685425558 +237000: 3282158412 +236000: 976807931 +235000: 1960913234 +234000: 675404937 +233000: 2016845981 +232000: 3778769531 +231000: 1321297859 +230000: 84609577 +229000: 2736973360 +228000: 1143462599 +227000: 1152334102 +226000: 2661675401 +225000: 3384049744 +224000: 3321570349 +223000: 2151575803 +222000: 2950365334 +221000: 2791341163 +220000: 2912181889 +219000: 700726300 +218000: 3236687629 +217000: 384678680 +216000: 3027284798 +215000: 2124466541 +214000: 1634885735 +213000: 3025139089 +212000: 1913485355 +211000: 2451444114 +210000: 1597224573 +209000: 2863042887 +208000: 1462999033 +207000: 853998677 +206000: 1532111742 +205000: 3533822378 +204000: 1057056422 +203000: 2585913344 +202000: 1776380902 +201000: 2652271540 +200000: 2500553547 +199000: 3943435104 +198000: 615742187 +197000: 2089667313 +196000: 1649690458 +195000: 582691711 +194000: 1197398266 +193000: 2682453813 +192000: 1739971049 +191000: 1543584807 +190000: 4224852565 +189000: 2330603128 +188000: 2738873539 +187000: 2462336661 +186000: 538134005 +185000: 618406175 +184000: 3258203829 +183000: 3565635398 +182000: 2437456159 +181000: 1103703144 +180000: 3142082412 +179000: 3635072449 +178000: 2831183465 +177000: 3067391696 +176000: 4243880329 +175000: 3847103503 +174000: 1886736895 +173000: 3994782354 +172000: 2180961421 +171000: 2657714328 +170000: 1783032069 +169000: 3288794122 +168000: 4214505744 +167000: 3893811403 +166000: 301673242 +165000: 1008606441 +164000: 4241744599 +163000: 4077366883 +162000: 947408771 +161000: 2893412067 +160000: 4239854096 +159000: 837488883 +158000: 1035341013 +157000: 2979612216 +156000: 622879904 +155000: 2239033946 +154000: 1793603359 +153000: 3403674755 +152000: 1757769702 +151000: 3104338771 +150000: 4050901279 +149000: 1064027760 +148000: 1232980113 +147000: 1940798204 +146000: 1520506974 +145000: 1602654645 +144000: 3827165041 +143000: 2333560581 +142000: 1078945096 +141000: 4164769913 +140000: 1004088705 +139000: 1918334274 +138000: 2376094733 +137000: 2114404244 +136000: 610887654 +135000: 2061314834 +134000: 2934949429 +133000: 1384359308 +132000: 2214638498 +131000: 4091637905 +130000: 1178600936 +129000: 3673332079 +128000: 335936353 +127000: 1680711257 +126000: 1535342908 +125000: 1797602927 +124000: 1277174958 +123000: 3114077321 +122000: 149498793 +121000: 864366602 +120000: 104510626 +119000: 1518395286 +118000: 3111302078 +117000: 3110116836 +116000: 3233967498 +115000: 1017896311 +114000: 692827001 +113000: 3779537224 +112000: 2905474934 +111000: 3465999202 +110000: 1915694049 +109000: 2628022627 +108000: 875271541 +107000: 2022225002 +106000: 1671971011 +105000: 3334748297 +104000: 1332184097 +103000: 1555681497 +102000: 3406253965 +101000: 4045141299 +100000: 3058680000 +99000: 555036606 +98000: 46275609 +97000: 3853135904 +96000: 4229006385 +95000: 4108164708 +94000: 2566945975 +93000: 3797900910 +92000: 3355992329 +91000: 1635484145 +90000: 1382023482 +89000: 3690432221 +88000: 1892056918 +87000: 1120722079 +86000: 2675052236 +85000: 4165748502 +84000: 10230467 +83000: 4138070209 +82000: 1570296924 +81000: 3126342757 +80000: 598265835 +79000: 541475291 +78000: 2784920265 +77000: 4169891577 +76000: 1101249184 +75000: 2090307927 +74000: 3780559777 +73000: 19873425 +72000: 1118190767 +71000: 3485912405 +70000: 1322638834 +69000: 1096526516 +68000: 1370553703 +67000: 3631120381 +66000: 1806420191 +65000: 2701118072 +64000: 483879470 +63000: 2124403158 +62000: 1877513812 +61000: 1289006766 +60000: 3733667461 +59000: 3457358686 +58000: 732502949 +57000: 3971773677 +56000: 883589946 +55000: 290212168 +54000: 2244967385 +53000: 3848247179 +52000: 2228476206 +51000: 2372703555 +50000: 1200411530 +49000: 2060190456 +48000: 2511902942 +47000: 4007272287 +46000: 2854231300 +45000: 2518671311 +44000: 815143404 +43000: 1972543143 +42000: 3063716128 +41000: 3326571310 +40000: 3180391453 +39000: 2568545510 +38000: 573110821 +37000: 3814257324 +36000: 4163248735 +35000: 943584186 +34000: 387069186 +33000: 3519377243 +32000: 3861206003 +31000: 2378381393 +30000: 3259365221 +29000: 3960625204 +28000: 3476394666 +27000: 1995310421 +26000: 1884341166 +25000: 3181801013 +24000: 116492838 +23000: 3276567587 +22000: 3693343729 +21000: 2595820568 +20000: 2397879436 +19000: 2692679578 +18000: 2368648652 +17000: 3098196844 +16000: 3913788179 +15000: 1240694507 +14000: 1586030084 +13000: 1211450031 +12000: 3458253062 +11000: 1804606651 +10000: 2128587109 +9000: 1894810186 +8000: 2221431098 +7000: 113605713 +6000: 4020003580 +5000: 2988041351 +4000: 2310084217 +3000: 1475476779 +2000: 760651391 +1000: 4031656975 +0: 2206428413 diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini index c3a59fbce..fa4ee72da 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -53,73 +51,20 @@ mem_mode=atomic physmem=system.physmem [system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 +cpu_id=0 defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -predType=tournament -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 +phase=0 +progress_interval=0 system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -131,7 +76,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -164,143 +108,6 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - [system.cpu.icache] type=BaseCache adaptive_compression=false @@ -308,7 +115,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -348,7 +154,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -384,20 +189,33 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=perlbmk -I. -I lib lgred.makerand.pl +cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -409,6 +227,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out index f491a3081..ea12fcb9a 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out @@ -19,19 +19,54 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=perlbmk -I. -I lib lgred.makerand.pl +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 -[system.cpu.dcache] +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] type=BaseCache -size=262144 +size=131072 assoc=2 block_size=64 latency=1 @@ -39,7 +74,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -68,214 +102,9 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu] -type=DerivO3CPU -clock=1 -numThreads=1 -activity=0 -workload=system.cpu.workload -mem=system.cpu.dcache -checker=null -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 -defer_registration=false -function_trace=false -function_trace_start=0 - -[system.cpu.icache] +[system.cpu.dcache] type=BaseCache -size=131072 +size=262144 assoc=2 block_size=64 latency=1 @@ -283,7 +112,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -322,7 +150,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -351,13 +178,10 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.toL2Bus] -type=Bus -bus_id=0 - [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +220,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt index 5d4f9235a..4d20e663a 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,112 +1,67 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +host_inst_rate 502967 # Simulator instruction rate (inst/s) +host_mem_usage 217744 # Number of bytes of host memory used +host_seconds 3994.27 # Real time elapsed on the host +host_tick_rate 1895851 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +sim_insts 2008987724 # Number of instructions simulated +sim_seconds 0.007573 # Number of seconds simulated +sim_ticks 7572549003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 511070058 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3107.171711 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171711 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 509611866 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4530852932 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3072660932 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 210794909 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3884.294897 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.294897 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 210722955 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 279490555 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 71954 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 207536555 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71954 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 470.762150 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 721864967 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3143.715362 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2143.715362 # average overall mshr miss latency +system.cpu.dcache.demand_hits 720334821 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4810343487 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1530146 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3280197487 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1530146 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 721864967 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3143.715362 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2143.715362 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 720334821 # number of overall hits +system.cpu.dcache.overall_miss_latency 4810343487 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1530146 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3280197487 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1530146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1526050 # number of replacements +system.cpu.dcache.sampled_refs 1530146 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 -system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 4087.472566 # Cycle average of tags in use +system.cpu.dcache.total_refs 720334821 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35194000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 74591 # number of writebacks +system.cpu.icache.ReadReq_accesses 2008987725 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3103.752500 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.752500 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2008977127 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 32893569 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 10598 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 22295569 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10598 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 189561.910455 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 2008987725 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3103.752500 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2103.752500 # average overall mshr miss latency +system.cpu.icache.demand_hits 2008977127 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 32893569 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses +system.cpu.icache.demand_misses 10598 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 22295569 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10598 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_accesses 2008987725 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3103.752500 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2103.752500 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_hits 2008977127 # number of overall hits +system.cpu.icache.overall_miss_latency 32893569 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses +system.cpu.icache.overall_misses 10598 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 22295569 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10598 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,1726 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.replacements 9048 # number of replacements +system.cpu.icache.sampled_refs 10598 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1472.251444 # Cycle average of tags in use +system.cpu.icache.total_refs 2008977127 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 1540744 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2153.831026 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1111.660796 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 3245534743 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1506866 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1675123857 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1506866 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 74591 # number of WriteReqNoAck|Writeback accesses(hits+misses) +system.cpu.l2cache.WriteReqNoAck|Writeback_hits 73517 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.014399 # miss rate for WriteReqNoAck|Writeback accesses +system.cpu.l2cache.WriteReqNoAck|Writeback_misses 1074 # number of WriteReqNoAck|Writeback misses +system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.014399 # mshr miss rate for WriteReqNoAck|Writeback accesses +system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 1074 # number of WriteReqNoAck|Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.071270 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 1540744 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2153.831026 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1111.660796 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3245534743 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1506866 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1675123857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1506866 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 1615335 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2152.297003 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1111.660796 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_hits 107395 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3245534743 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.933515 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1507940 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1675123857 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.932850 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1506866 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -1946,29 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1474098 # number of replacements +system.cpu.l2cache.sampled_refs 1506866 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.l2cache.tagsinuse 32444.673070 # Cycle average of tags in use +system.cpu.l2cache.total_refs 107395 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 164218000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 66806 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 7572549003 # number of cpu cycles simulated +system.cpu.num_insts 2008987724 # Number of instructions executed +system.cpu.num_refs 722390480 # Number of memory references +system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr index 8893caac8..9135960d0 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr @@ -1,3 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 +warn: ignoring syscall sigprocmask(1, 0, ...) diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout index fbb329a2f..d4a078b85 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout @@ -1,13 +1,1376 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +1375000: 2038431008 +1374000: 3487365506 +1373000: 4184770123 +1372000: 1943746837 +1371000: 2651673663 +1370000: 1493817016 +1369000: 2894014801 +1368000: 1932092157 +1367000: 1670009799 +1366000: 828662248 +1365000: 1816650195 +1364000: 4173139012 +1363000: 3990577549 +1362000: 1330366815 +1361000: 3316935553 +1360000: 961300001 +1359000: 344963924 +1358000: 1930356625 +1357000: 1640964266 +1356000: 3777883312 +1355000: 1651132665 +1354000: 1971433151 +1353000: 3024027448 +1352000: 1956387036 +1351000: 1490224841 +1350000: 3286956460 +1349000: 2793131848 +1348000: 2529224907 +1347000: 2622295253 +1346000: 1414103189 +1345000: 3861617587 +1344000: 3506378216 +1343000: 1667466720 +1342000: 2899224065 +1341000: 1681491556 +1340000: 1076311729 +1339000: 4066972664 +1338000: 3438059028 +1337000: 2938359730 +1336000: 1214615378 +1335000: 3814432458 +1334000: 2944038793 +1333000: 3428045644 +1332000: 2815822229 +1331000: 1093465585 +1330000: 3012217108 +1329000: 2230916791 +1328000: 208547885 +1327000: 3592585825 +1326000: 3948677052 +1325000: 1817805162 +1324000: 135366494 +1323000: 3309148112 +1322000: 1685035744 +1321000: 3293068577 +1320000: 4097808567 +1319000: 1594097274 +1318000: 2607196971 +1317000: 1763785306 +1316000: 2157394178 +1315000: 2399031328 +1314000: 2954547004 +1313000: 82348686 +1312000: 3120930785 +1311000: 2192747320 +1310000: 1580299400 +1309000: 4085061477 +1308000: 3627048345 +1307000: 3756533178 +1306000: 77997329 +1305000: 1343359499 +1304000: 1124031730 +1303000: 1161755432 +1302000: 1855858423 +1301000: 3985872257 +1300000: 3188250811 +1299000: 3621615933 +1298000: 962624248 +1297000: 447138785 +1296000: 1459144309 +1295000: 3454504226 +1294000: 2154913347 +1293000: 2356291788 +1292000: 458348817 +1291000: 3639562699 +1290000: 3596847973 +1289000: 117168222 +1288000: 3531023849 +1287000: 3135920051 +1286000: 234987844 +1285000: 2048767180 +1284000: 2437301839 +1283000: 522886780 +1282000: 2274133042 +1281000: 1415703448 +1280000: 4145574054 +1279000: 4283494580 +1278000: 3305365779 +1277000: 604711974 +1276000: 2031548723 +1275000: 1809515149 +1274000: 1664703088 +1273000: 4149809153 +1272000: 4045608138 +1271000: 1687605659 +1270000: 1292294527 +1269000: 3120968162 +1268000: 3502898850 +1267000: 371380256 +1266000: 1683884245 +1265000: 1849576817 +1264000: 1559050991 +1263000: 66820972 +1262000: 4023539201 +1261000: 3452295398 +1260000: 4188778026 +1259000: 2008091854 +1258000: 2691158394 +1257000: 2030818206 +1256000: 2715523403 +1255000: 3473414015 +1254000: 138826953 +1253000: 69386516 +1252000: 1174725971 +1251000: 4130510373 +1250000: 1649788328 +1249000: 1589122801 +1248000: 1108688101 +1247000: 2906355484 +1246000: 379539929 +1245000: 914026021 +1244000: 4074858468 +1243000: 505989635 +1242000: 2487288773 +1241000: 1991248111 +1240000: 2415456875 +1239000: 2571192525 +1238000: 2897090536 +1237000: 2761178989 +1236000: 1296601829 +1235000: 594696756 +1234000: 264562726 +1233000: 3630852367 +1232000: 1605618457 +1231000: 2857419452 +1230000: 3028672437 +1229000: 361833758 +1228000: 4046013938 +1227000: 1031775583 +1226000: 3475227831 +1225000: 802168737 +1224000: 3819194009 +1223000: 851157666 +1222000: 2656457905 +1221000: 2579045204 +1220000: 2091024410 +1219000: 4070633834 +1218000: 1926611791 +1217000: 1903813761 +1216000: 3107168794 +1215000: 2975081979 +1214000: 4097089273 +1213000: 328943233 +1212000: 2912404803 +1211000: 181334180 +1210000: 863898367 +1209000: 1894902343 +1208000: 1531985231 +1207000: 1412503751 +1206000: 662457490 +1205000: 3447925432 +1204000: 2320889638 +1203000: 303282255 +1202000: 1568632659 +1201000: 1108711074 +1200000: 953936964 +1199000: 3576987258 +1198000: 466163300 +1197000: 1159551420 +1196000: 529807534 +1195000: 1528979627 +1194000: 1795576953 +1193000: 2050917610 +1192000: 4068219994 +1191000: 3573497288 +1190000: 776005286 +1189000: 2643125982 +1188000: 2240857507 +1187000: 43353719 +1186000: 2474198261 +1185000: 1711347056 +1184000: 3046018343 +1183000: 664346074 +1182000: 3532392595 +1181000: 3145347726 +1180000: 2203928246 +1179000: 4275910811 +1178000: 3260065240 +1177000: 3216083720 +1176000: 3588515377 +1175000: 1432542416 +1174000: 173159992 +1173000: 4115057268 +1172000: 223456174 +1171000: 1192164227 +1170000: 2059254624 +1169000: 279921804 +1168000: 1100495449 +1167000: 264813624 +1166000: 2839280440 +1165000: 301796904 +1164000: 1331933822 +1163000: 647427882 +1162000: 3872813324 +1161000: 2231068824 +1160000: 4222672618 +1159000: 3629229584 +1158000: 2262586804 +1157000: 2837951671 +1156000: 1780662312 +1155000: 31553143 +1154000: 3230861653 +1153000: 1991458597 +1152000: 2277829165 +1151000: 3864184029 +1150000: 630158826 +1149000: 4028889917 +1148000: 1662505287 +1147000: 4121796538 +1146000: 3215277282 +1145000: 2019794999 +1144000: 4124433286 +1143000: 181819953 +1142000: 2704380222 +1141000: 2487909897 +1140000: 1753570204 +1139000: 2337507591 +1138000: 3235449912 +1137000: 3819353806 +1136000: 3435413746 +1135000: 3288196653 +1134000: 2705083758 +1133000: 997301031 +1132000: 1871866706 +1131000: 2298991521 +1130000: 1516060457 +1129000: 3393393053 +1128000: 2795526466 +1127000: 1177801041 +1126000: 4226698729 +1125000: 567826718 +1124000: 2425735007 +1123000: 1090360485 +1122000: 2508061782 +1121000: 3476086116 +1120000: 2952087827 +1119000: 2238445545 +1118000: 2937037425 +1117000: 1773353797 +1116000: 3033333765 +1115000: 3086246055 +1114000: 944390435 +1113000: 2944932895 +1112000: 534683663 +1111000: 2002175399 +1110000: 1876265996 +1109000: 4148000592 +1108000: 3857174625 +1107000: 843045539 +1106000: 307772960 +1105000: 4161975075 +1104000: 3675447412 +1103000: 1232242543 +1102000: 1019583281 +1101000: 1983565552 +1100000: 2490901544 +1099000: 2990982808 +1098000: 1586955629 +1097000: 1629138000 +1096000: 1870655270 +1095000: 2201093764 +1094000: 696079363 +1093000: 1526904315 +1092000: 553848190 +1091000: 4234411636 +1090000: 1027439894 +1089000: 1319115149 +1088000: 1147708285 +1087000: 3364503693 +1086000: 528432422 +1085000: 3289100476 +1084000: 3074065438 +1083000: 3664250869 +1082000: 2950591670 +1081000: 4207904839 +1080000: 3425353965 +1079000: 1069646286 +1078000: 1004956209 +1077000: 2642475281 +1076000: 364759474 +1075000: 2334969932 +1074000: 3907002684 +1073000: 273633783 +1072000: 4113182592 +1071000: 1404306188 +1070000: 3286171051 +1069000: 3531039414 +1068000: 4147513318 +1067000: 2466290219 +1066000: 2089005579 +1065000: 2617563073 +1064000: 3124838472 +1063000: 3731008114 +1062000: 4154022628 +1061000: 3389258714 +1060000: 3915149371 +1059000: 2280932986 +1058000: 2872952978 +1057000: 2381277834 +1056000: 1236179469 +1055000: 3256417375 +1054000: 2700213407 +1053000: 3418122897 +1052000: 3130247908 +1051000: 1897033028 +1050000: 2349143738 +1049000: 3789736749 +1048000: 409522147 +1047000: 3149279018 +1046000: 1323133366 +1045000: 3881472077 +1044000: 3363874422 +1043000: 3931657349 +1042000: 1220007174 +1041000: 3634450249 +1040000: 695184634 +1039000: 529508167 +1038000: 449827627 +1037000: 2817424280 +1036000: 1613482057 +1035000: 2632612792 +1034000: 852422020 +1033000: 4098325966 +1032000: 177298753 +1031000: 2286807874 +1030000: 2745349553 +1029000: 2387386570 +1028000: 2004317534 +1027000: 971343564 +1026000: 1583732447 +1025000: 2340780818 +1024000: 561110245 +1023000: 3012020895 +1022000: 1677066870 +1021000: 3046208682 +1020000: 2695506079 +1019000: 780536149 +1018000: 4225713741 +1017000: 420500410 +1016000: 3642094643 +1015000: 608695027 +1014000: 2161592269 +1013000: 930784800 +1012000: 1924051276 +1011000: 1889733886 +1010000: 1476038251 +1009000: 2908577467 +1008000: 2584082136 +1007000: 1713214537 +1006000: 3374346754 +1005000: 1173203719 +1004000: 1142288559 +1003000: 4195961973 +1002000: 1211260974 +1001000: 474231127 +1000000: 3967090782 +999000: 1543103493 +998000: 1018646803 +997000: 1799037982 +996000: 3416426509 +995000: 3581729971 +994000: 3044504127 +993000: 2975704335 +992000: 280018795 +991000: 330300280 +990000: 3557016064 +989000: 3856724468 +988000: 2124201285 +987000: 3683893247 +986000: 3331663795 +985000: 1980057740 +984000: 2908437859 +983000: 4074086941 +982000: 1162307093 +981000: 3855413476 +980000: 2799155731 +979000: 2477822501 +978000: 497762075 +977000: 1650233426 +976000: 3061573902 +975000: 2224673611 +974000: 868725340 +973000: 1630206962 +972000: 2549398924 +971000: 602424332 +970000: 1172502721 +969000: 2923795552 +968000: 1394164637 +967000: 1088479837 +966000: 898709052 +965000: 3983150961 +964000: 2463803866 +963000: 4181117626 +962000: 2151137820 +961000: 1342513757 +960000: 1507689687 +959000: 3652624918 +958000: 4169721124 +957000: 531022334 +956000: 3161389505 +955000: 1197637232 +954000: 2927231791 +953000: 2552305374 +952000: 2988512039 +951000: 2448639370 +950000: 3560951660 +949000: 948988399 +948000: 2488188856 +947000: 2804177113 +946000: 1991587461 +945000: 2480044082 +944000: 1954588624 +943000: 924231798 +942000: 3269047595 +941000: 2078696579 +940000: 2822989969 +939000: 2295885951 +938000: 1815612561 +937000: 4182254074 +936000: 2753223967 +935000: 2840201908 +934000: 4058383142 +933000: 4270167260 +932000: 1203124158 +931000: 3039861400 +930000: 4247472610 +929000: 2297661055 +928000: 2376159704 +927000: 3861417958 +926000: 1968685250 +925000: 1156966624 +924000: 3568580529 +923000: 866582344 +922000: 2263113297 +921000: 3643523016 +920000: 3252268544 +919000: 2413309783 +918000: 3463124619 +917000: 3965291932 +916000: 1309181143 +915000: 2321282614 +914000: 2286584604 +913000: 3271924727 +912000: 1719841316 +911000: 3966124343 +910000: 607707072 +909000: 61942114 +908000: 903881820 +907000: 4136948835 +906000: 3663861210 +905000: 3251888710 +904000: 227984688 +903000: 495030333 +902000: 863290992 +901000: 3297482717 +900000: 3821175085 +899000: 1679874522 +898000: 2033358728 +897000: 3495513776 +896000: 1613181881 +895000: 1729312232 +894000: 2171317375 +893000: 2508603694 +892000: 151095866 +891000: 1926096901 +890000: 4292888210 +889000: 2716307666 +888000: 737310728 +887000: 4172392976 +886000: 2322084662 +885000: 1034961047 +884000: 665072958 +883000: 368014441 +882000: 1914585160 +881000: 3836900884 +880000: 2073827187 +879000: 1650543625 +878000: 3581099222 +877000: 147580905 +876000: 4009421518 +875000: 3294244820 +874000: 2786720968 +873000: 1682434702 +872000: 620473876 +871000: 742752376 +870000: 385116650 +869000: 3882475387 +868000: 4259210265 +867000: 1329675866 +866000: 539876515 +865000: 2761681036 +864000: 2192063038 +863000: 1512848001 +862000: 3911973718 +861000: 399349760 +860000: 1449497249 +859000: 4241714042 +858000: 18611709 +857000: 1550083097 +856000: 3322762748 +855000: 283796511 +854000: 227907270 +853000: 3162559866 +852000: 1331946455 +851000: 2328467927 +850000: 1640242501 +849000: 3390154083 +848000: 22088346 +847000: 636412590 +846000: 1550672808 +845000: 763937899 +844000: 430123910 +843000: 3413971543 +842000: 900018421 +841000: 3295874222 +840000: 2470678073 +839000: 821401909 +838000: 3923898844 +837000: 429069328 +836000: 2030779868 +835000: 464625222 +834000: 3593024182 +833000: 3564354808 +832000: 2794783695 +831000: 97817593 +830000: 4197446076 +829000: 2367560230 +828000: 2180262123 +827000: 3149571964 +826000: 1364436763 +825000: 21599634 +824000: 448490256 +823000: 3775294409 +822000: 1132631425 +821000: 2046352434 +820000: 3380435217 +819000: 3672496486 +818000: 1634548077 +817000: 2881316258 +816000: 1808599559 +815000: 3298310748 +814000: 3744285741 +813000: 3540737709 +812000: 1143844515 +811000: 3091026783 +810000: 3771757792 +809000: 631375816 +808000: 1353831646 +807000: 3047756240 +806000: 818136890 +805000: 783072818 +804000: 3923416267 +803000: 3233085529 +802000: 674747602 +801000: 758523180 +800000: 2232308489 +799000: 2919643710 +798000: 623631722 +797000: 1302202741 +796000: 1083055596 +795000: 2358048936 +794000: 2836842068 +793000: 1612571734 +792000: 4243459584 +791000: 1585511173 +790000: 1493369943 +789000: 3649557715 +788000: 3223859588 +787000: 4001130195 +786000: 2949323631 +785000: 3887611007 +784000: 4091766333 +783000: 2954277998 +782000: 1281850218 +781000: 771664458 +780000: 2242576209 +779000: 3865479146 +778000: 1885013114 +777000: 2032659742 +776000: 4221167450 +775000: 1962824751 +774000: 209539683 +773000: 262945027 +772000: 452388820 +771000: 2006266573 +770000: 990063860 +769000: 1377951885 +768000: 4240978277 +767000: 2206801004 +766000: 258015097 +765000: 1990217201 +764000: 1336410303 +763000: 1004853228 +762000: 1404152873 +761000: 3356554358 +760000: 4052430907 +759000: 2833671166 +758000: 1561723151 +757000: 1752620777 +756000: 2622547462 +755000: 1843933196 +754000: 3728801998 +753000: 2776832730 +752000: 2626131293 +751000: 1528525830 +750000: 2716112581 +749000: 3306039713 +748000: 915271993 +747000: 4205133363 +746000: 3136321783 +745000: 1203154793 +744000: 3370017183 +743000: 4036456207 +742000: 3377556743 +741000: 3688568185 +740000: 3349738887 +739000: 1606411092 +738000: 331980874 +737000: 744409647 +736000: 3845688101 +735000: 3654026084 +734000: 786733128 +733000: 1938791337 +732000: 843210299 +731000: 622237260 +730000: 2851984401 +729000: 874906210 +728000: 485670931 +727000: 1522238607 +726000: 2167917076 +725000: 2304482464 +724000: 1053513779 +723000: 3535437378 +722000: 2842397393 +721000: 864490421 +720000: 920591184 +719000: 238249003 +718000: 400999105 +717000: 2476588521 +716000: 2501770197 +715000: 2307183887 +714000: 2461504446 +713000: 1055961242 +712000: 2112756603 +711000: 1691285107 +710000: 2318101701 +709000: 1113470660 +708000: 2880817109 +707000: 2105866601 +706000: 1441912219 +705000: 1684930572 +704000: 1652788290 +703000: 2359919145 +702000: 554008403 +701000: 3292620387 +700000: 3528106952 +699000: 3096375697 +698000: 4201459210 +697000: 1450879661 +696000: 3743939389 +695000: 3595614062 +694000: 4101634764 +693000: 364538097 +692000: 4204120947 +691000: 3706729229 +690000: 23134581 +689000: 2585120038 +688000: 488096133 +687000: 3437179533 +686000: 4233790378 +685000: 3093374794 +684000: 4054579709 +683000: 1275606548 +682000: 1966964511 +681000: 354765069 +680000: 3812578933 +679000: 781104418 +678000: 3281747368 +677000: 38547527 +676000: 1005246555 +675000: 74753563 +674000: 676561715 +673000: 1571462591 +672000: 1876054379 +671000: 1899005137 +670000: 4188106842 +669000: 1210903253 +668000: 2909261468 +667000: 3100970839 +666000: 758568698 +665000: 2456763236 +664000: 686978785 +663000: 349808361 +662000: 2804776250 +661000: 2660993423 +660000: 1758165672 +659000: 2116094507 +658000: 473425247 +657000: 563682488 +656000: 1454194093 +655000: 3211379305 +654000: 1298793267 +653000: 3374836733 +652000: 586356525 +651000: 1490379306 +650000: 2444980288 +649000: 47671514 +648000: 568687171 +647000: 452676234 +646000: 2752247721 +645000: 1473254180 +644000: 4189470166 +643000: 2619721788 +642000: 348627393 +641000: 675341258 +640000: 3183922211 +639000: 1266115377 +638000: 2331844572 +637000: 250721255 +636000: 4017517385 +635000: 1279621530 +634000: 1500904407 +633000: 2495457137 +632000: 1919479114 +631000: 1900388354 +630000: 370039669 +629000: 1207459690 +628000: 2314286843 +627000: 80099285 +626000: 2465533600 +625000: 1056979505 +624000: 4289445503 +623000: 1234007489 +622000: 2015973003 +621000: 2281387627 +620000: 1115405564 +619000: 1407699260 +618000: 3940256761 +617000: 3639431367 +616000: 3498942818 +615000: 2982957031 +614000: 3800830694 +613000: 1454837486 +612000: 158454584 +611000: 3414923339 +610000: 3752581462 +609000: 195868045 +608000: 3165948362 +607000: 2335822431 +606000: 3229210414 +605000: 1963422803 +604000: 2355005929 +603000: 2009365872 +602000: 1343084455 +601000: 2935056539 +600000: 2354171524 +599000: 3621510708 +598000: 3992266416 +597000: 682368260 +596000: 3290472265 +595000: 2215475388 +594000: 258049456 +593000: 365234760 +592000: 291875022 +591000: 3307168950 +590000: 2233802778 +589000: 1944100586 +588000: 7070250 +587000: 882601802 +586000: 1231725137 +585000: 4169259917 +584000: 2123453163 +583000: 631823798 +582000: 2039925673 +581000: 2238172862 +580000: 1479379031 +579000: 2363652063 +578000: 3186953219 +577000: 1893181853 +576000: 2598096173 +575000: 938779920 +574000: 927622241 +573000: 3105026014 +572000: 2412852365 +571000: 644810722 +570000: 3576393744 +569000: 2625468928 +568000: 2167447563 +567000: 3391359662 +566000: 3178493511 +565000: 24044406 +564000: 3298992941 +563000: 2054886551 +562000: 42479754 +561000: 2681525651 +560000: 1110769583 +559000: 2140540905 +558000: 780964175 +557000: 1320986796 +556000: 3624725635 +555000: 2920977559 +554000: 4017386186 +553000: 1800018968 +552000: 2137743255 +551000: 2282561617 +550000: 1466333871 +549000: 2567190002 +548000: 3280136825 +547000: 1761114084 +546000: 413841088 +545000: 829808286 +544000: 283842712 +543000: 3524860517 +542000: 1853927454 +541000: 3087398009 +540000: 2535138654 +539000: 2224833733 +538000: 1673737994 +537000: 3963575809 +536000: 289926670 +535000: 2411609896 +534000: 1866933324 +533000: 259728174 +532000: 786327819 +531000: 870136645 +530000: 3603849411 +529000: 1687141824 +528000: 2973109656 +527000: 2120372902 +526000: 3554894341 +525000: 369365218 +524000: 2336210870 +523000: 1352671703 +522000: 4093185231 +521000: 44309897 +520000: 1308207751 +519000: 1489447779 +518000: 497784082 +517000: 2370135551 +516000: 2393982064 +515000: 3453216376 +514000: 349616264 +513000: 1057922348 +512000: 2061823561 +511000: 2221803921 +510000: 2518047997 +509000: 2783356981 +508000: 3842023593 +507000: 3105321997 +506000: 3540124104 +505000: 334821209 +504000: 2867156116 +503000: 3824184936 +502000: 2432119674 +501000: 3759474841 +500000: 3381305904 +499000: 3106640260 +498000: 4241569809 +497000: 2499659818 +496000: 3971155346 +495000: 2297624439 +494000: 3455216298 +493000: 2152855317 +492000: 3915728702 +491000: 1087687366 +490000: 3976823873 +489000: 1813936857 +488000: 2803197060 +487000: 4026575712 +486000: 3867909271 +485000: 644795069 +484000: 1051897856 +483000: 3091023530 +482000: 558963440 +481000: 2516346710 +480000: 2405618228 +479000: 1595155902 +478000: 1699460683 +477000: 645434559 +476000: 1457238083 +475000: 101746166 +474000: 1054127445 +473000: 1703635926 +472000: 3228750510 +471000: 2570095523 +470000: 2671516672 +469000: 219569232 +468000: 245973042 +467000: 1785352151 +466000: 1828704556 +465000: 2993350381 +464000: 1802995474 +463000: 3689392931 +462000: 2612188341 +461000: 1970287287 +460000: 179729165 +459000: 1971694777 +458000: 3031333568 +457000: 844564594 +456000: 979968160 +455000: 2169589334 +454000: 2315813244 +453000: 2333801403 +452000: 27632567 +451000: 3752181065 +450000: 3965825733 +449000: 969798494 +448000: 1028884180 +447000: 1127216392 +446000: 2477366335 +445000: 3752023316 +444000: 1679036165 +443000: 4241934865 +442000: 3360200587 +441000: 3533494907 +440000: 1888455616 +439000: 2668699748 +438000: 2728196631 +437000: 31348508 +436000: 2192326452 +435000: 286955043 +434000: 4097630027 +433000: 1185622743 +432000: 2870795553 +431000: 2246074692 +430000: 14797454 +429000: 2606207217 +428000: 2143322684 +427000: 1289559127 +426000: 3922285071 +425000: 590638427 +424000: 1098669098 +423000: 1597510568 +422000: 1623191243 +421000: 558862770 +420000: 3846690181 +419000: 3187756225 +418000: 2520849981 +417000: 492022774 +416000: 1621927303 +415000: 2828836994 +414000: 2840605981 +413000: 4260845378 +412000: 2200645444 +411000: 393061550 +410000: 3334889686 +409000: 1926958198 +408000: 2939424440 +407000: 4207748941 +406000: 4155428743 +405000: 89797563 +404000: 427509452 +403000: 1154877029 +402000: 4023324583 +401000: 359413604 +400000: 964788206 +399000: 3843097093 +398000: 1871599521 +397000: 2361845870 +396000: 4103568192 +395000: 622493054 +394000: 954921337 +393000: 3664395297 +392000: 2429042528 +391000: 1361036260 +390000: 1944048082 +389000: 1452288555 +388000: 1619598577 +387000: 481096019 +386000: 3719595713 +385000: 1840199850 +384000: 421723640 +383000: 2976677668 +382000: 618336385 +381000: 1777037748 +380000: 901802032 +379000: 621392881 +378000: 3857241587 +377000: 3115040335 +376000: 3173790487 +375000: 2517831056 +374000: 4125976072 +373000: 2294107866 +372000: 4127359945 +371000: 333946663 +370000: 3307391606 +369000: 4268094300 +368000: 91056295 +367000: 882600429 +366000: 730521557 +365000: 3957048081 +364000: 2139992409 +363000: 3504327478 +362000: 2637042137 +361000: 2718540805 +360000: 903036675 +359000: 1858031956 +358000: 1868403889 +357000: 2677157063 +356000: 1865569815 +355000: 224528281 +354000: 3144318856 +353000: 1968806079 +352000: 2836077060 +351000: 1981309964 +350000: 3105869514 +349000: 3793296439 +348000: 1267294125 +347000: 1962520375 +346000: 2150839102 +345000: 3811064048 +344000: 1298671776 +343000: 2150950779 +342000: 3522997671 +341000: 1378798782 +340000: 2213936395 +339000: 2117978968 +338000: 2444486361 +337000: 3928234621 +336000: 1645335376 +335000: 540013781 +334000: 1103798645 +333000: 1723781016 +332000: 1805323374 +331000: 3590394804 +330000: 4178797476 +329000: 3350975600 +328000: 1556948383 +327000: 2282601074 +326000: 1709618426 +325000: 637957139 +324000: 2719080929 +323000: 1847444832 +322000: 547261068 +321000: 581409575 +320000: 586567018 +319000: 1579880779 +318000: 1049735969 +317000: 3233747918 +316000: 351376358 +315000: 3446473138 +314000: 2099035319 +313000: 2827833754 +312000: 2717063452 +311000: 2212978977 +310000: 1583494069 +309000: 3119642323 +308000: 2946038826 +307000: 167580491 +306000: 3916319765 +305000: 3480693946 +304000: 2709010304 +303000: 3265576420 +302000: 3439318492 +301000: 1896109937 +300000: 339896540 +299000: 313850585 +298000: 2600289987 +297000: 4060531515 +296000: 3894455718 +295000: 3183544633 +294000: 1551799240 +293000: 3574197425 +292000: 2380783887 +291000: 3130665581 +290000: 1135162832 +289000: 3460550191 +288000: 3366619355 +287000: 501626025 +286000: 1070097358 +285000: 1023235560 +284000: 925313877 +283000: 3758987940 +282000: 1935539406 +281000: 3727463323 +280000: 4040081802 +279000: 2462105177 +278000: 322183212 +277000: 2437872102 +276000: 1085894622 +275000: 2118601354 +274000: 1720719726 +273000: 56294175 +272000: 2046218040 +271000: 2871320919 +270000: 3111863367 +269000: 726835633 +268000: 916866344 +267000: 1208374677 +266000: 2914608557 +265000: 449456198 +264000: 2645640532 +263000: 997311800 +262000: 2872564998 +261000: 1964496124 +260000: 2802080932 +259000: 387636194 +258000: 3813984224 +257000: 1921258264 +256000: 1414333533 +255000: 997845727 +254000: 3671258247 +253000: 3244313331 +252000: 44297738 +251000: 1055697350 +250000: 403951609 +249000: 3558182356 +248000: 3441722116 +247000: 3598259825 +246000: 2495236386 +245000: 4150113079 +244000: 4092477475 +243000: 1352323466 +242000: 4228179784 +241000: 3509286314 +240000: 1117669666 +239000: 1821539001 +238000: 2685425558 +237000: 3282158412 +236000: 976807931 +235000: 1960913234 +234000: 675404937 +233000: 2016845981 +232000: 3778769531 +231000: 1321297859 +230000: 84609577 +229000: 2736973360 +228000: 1143462599 +227000: 1152334102 +226000: 2661675401 +225000: 3384049744 +224000: 3321570349 +223000: 2151575803 +222000: 2950365334 +221000: 2791341163 +220000: 2912181889 +219000: 700726300 +218000: 3236687629 +217000: 384678680 +216000: 3027284798 +215000: 2124466541 +214000: 1634885735 +213000: 3025139089 +212000: 1913485355 +211000: 2451444114 +210000: 1597224573 +209000: 2863042887 +208000: 1462999033 +207000: 853998677 +206000: 1532111742 +205000: 3533822378 +204000: 1057056422 +203000: 2585913344 +202000: 1776380902 +201000: 2652271540 +200000: 2500553547 +199000: 3943435104 +198000: 615742187 +197000: 2089667313 +196000: 1649690458 +195000: 582691711 +194000: 1197398266 +193000: 2682453813 +192000: 1739971049 +191000: 1543584807 +190000: 4224852565 +189000: 2330603128 +188000: 2738873539 +187000: 2462336661 +186000: 538134005 +185000: 618406175 +184000: 3258203829 +183000: 3565635398 +182000: 2437456159 +181000: 1103703144 +180000: 3142082412 +179000: 3635072449 +178000: 2831183465 +177000: 3067391696 +176000: 4243880329 +175000: 3847103503 +174000: 1886736895 +173000: 3994782354 +172000: 2180961421 +171000: 2657714328 +170000: 1783032069 +169000: 3288794122 +168000: 4214505744 +167000: 3893811403 +166000: 301673242 +165000: 1008606441 +164000: 4241744599 +163000: 4077366883 +162000: 947408771 +161000: 2893412067 +160000: 4239854096 +159000: 837488883 +158000: 1035341013 +157000: 2979612216 +156000: 622879904 +155000: 2239033946 +154000: 1793603359 +153000: 3403674755 +152000: 1757769702 +151000: 3104338771 +150000: 4050901279 +149000: 1064027760 +148000: 1232980113 +147000: 1940798204 +146000: 1520506974 +145000: 1602654645 +144000: 3827165041 +143000: 2333560581 +142000: 1078945096 +141000: 4164769913 +140000: 1004088705 +139000: 1918334274 +138000: 2376094733 +137000: 2114404244 +136000: 610887654 +135000: 2061314834 +134000: 2934949429 +133000: 1384359308 +132000: 2214638498 +131000: 4091637905 +130000: 1178600936 +129000: 3673332079 +128000: 335936353 +127000: 1680711257 +126000: 1535342908 +125000: 1797602927 +124000: 1277174958 +123000: 3114077321 +122000: 149498793 +121000: 864366602 +120000: 104510626 +119000: 1518395286 +118000: 3111302078 +117000: 3110116836 +116000: 3233967498 +115000: 1017896311 +114000: 692827001 +113000: 3779537224 +112000: 2905474934 +111000: 3465999202 +110000: 1915694049 +109000: 2628022627 +108000: 875271541 +107000: 2022225002 +106000: 1671971011 +105000: 3334748297 +104000: 1332184097 +103000: 1555681497 +102000: 3406253965 +101000: 4045141299 +100000: 3058680000 +99000: 555036606 +98000: 46275609 +97000: 3853135904 +96000: 4229006385 +95000: 4108164708 +94000: 2566945975 +93000: 3797900910 +92000: 3355992329 +91000: 1635484145 +90000: 1382023482 +89000: 3690432221 +88000: 1892056918 +87000: 1120722079 +86000: 2675052236 +85000: 4165748502 +84000: 10230467 +83000: 4138070209 +82000: 1570296924 +81000: 3126342757 +80000: 598265835 +79000: 541475291 +78000: 2784920265 +77000: 4169891577 +76000: 1101249184 +75000: 2090307927 +74000: 3780559777 +73000: 19873425 +72000: 1118190767 +71000: 3485912405 +70000: 1322638834 +69000: 1096526516 +68000: 1370553703 +67000: 3631120381 +66000: 1806420191 +65000: 2701118072 +64000: 483879470 +63000: 2124403158 +62000: 1877513812 +61000: 1289006766 +60000: 3733667461 +59000: 3457358686 +58000: 732502949 +57000: 3971773677 +56000: 883589946 +55000: 290212168 +54000: 2244967385 +53000: 3848247179 +52000: 2228476206 +51000: 2372703555 +50000: 1200411530 +49000: 2060190456 +48000: 2511902942 +47000: 4007272287 +46000: 2854231300 +45000: 2518671311 +44000: 815143404 +43000: 1972543143 +42000: 3063716128 +41000: 3326571310 +40000: 3180391453 +39000: 2568545510 +38000: 573110821 +37000: 3814257324 +36000: 4163248735 +35000: 943584186 +34000: 387069186 +33000: 3519377243 +32000: 3861206003 +31000: 2378381393 +30000: 3259365221 +29000: 3960625204 +28000: 3476394666 +27000: 1995310421 +26000: 1884341166 +25000: 3181801013 +24000: 116492838 +23000: 3276567587 +22000: 3693343729 +21000: 2595820568 +20000: 2397879436 +19000: 2692679578 +18000: 2368648652 +17000: 3098196844 +16000: 3913788179 +15000: 1240694507 +14000: 1586030084 +13000: 1211450031 +12000: 3458253062 +11000: 1804606651 +10000: 2128587109 +9000: 1894810186 +8000: 2221431098 +7000: 113605713 +6000: 4020003580 +5000: 2988041351 +4000: 2310084217 +3000: 1475476779 +2000: 760651391 +1000: 4031656975 +0: 2206428413 |