diff options
Diffstat (limited to 'tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 6f8327e62..6efaa543d 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 233856 # Simulator instruction rate (inst/s) -host_mem_usage 197400 # Number of bytes of host memory used -host_seconds 7795.57 # Real time elapsed on the host -host_tick_rate 90456464 # Simulator tick rate (ticks/s) +host_inst_rate 178423 # Simulator instruction rate (inst/s) +host_mem_usage 199584 # Number of bytes of host memory used +host_seconds 10217.56 # Real time elapsed on the host +host_tick_rate 69014447 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated sim_seconds 0.705159 # Number of seconds simulated @@ -95,6 +95,8 @@ system.cpu.dcache.demand_mshr_misses 1534074 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.104513 # Average occupied blocks per context system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency @@ -201,6 +203,8 @@ system.cpu.icache.demand_mshr_misses 9768 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.788136 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1614.102824 # Average occupied blocks per context system.cpu.icache.overall_accesses 348447899 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 15851.065828 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency @@ -391,6 +395,10 @@ system.cpu.l2cache.demand_mshr_misses 1511777 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.927694 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.046416 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 30398.691034 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1520.954518 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 1540711 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34361.852641 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency |