diff options
Diffstat (limited to 'tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini')
-rw-r--r-- | tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini new file mode 100644 index 000000000..59c6e25e2 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -0,0 +1,90 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.workload] +type=LiveProcess +cmd=perlbmk -I. -I lib lgred.makerand.pl +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic +egid=100 +env= +euid=100 +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + |