diff options
Diffstat (limited to 'tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index c88cbd8f6..0966bdbb1 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 584935 # Simulator instruction rate (inst/s) -host_mem_usage 232204 # Number of bytes of host memory used -host_seconds 3434.55 # Real time elapsed on the host -host_tick_rate 819166202 # Simulator tick rate (ticks/s) +host_inst_rate 2647820 # Simulator instruction rate (inst/s) +host_mem_usage 209816 # Number of bytes of host memory used +host_seconds 758.73 # Real time elapsed on the host +host_tick_rate 3708113045 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.813468 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 1530144 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999806 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4095.204626 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999806 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54553.304787 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 10596 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.721886 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1478.423269 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.721886 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 1479815 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.880371 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.094050 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 28848.012979 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 3081.828747 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.880371 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.094050 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 1332688300 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_mem_refs 722298387 # number of memory refs system.cpu.num_store_insts 210809477 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 39 # Number of system calls +system.cpu.workload.num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- |