diff options
Diffstat (limited to 'tests/long/40.perlbmk/ref/alpha')
8 files changed, 196 insertions, 193 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index d7298148c..f5ffa5534 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 4c38c001d..2316b9142 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 21:45:13 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:35 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 870c3ba76..c6cbb8474 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 161084 # Simulator instruction rate (inst/s) -host_mem_usage 215416 # Number of bytes of host memory used -host_seconds 11317.35 # Real time elapsed on the host -host_tick_rate 60889223 # Simulator tick rate (ticks/s) +host_inst_rate 299190 # Simulator instruction rate (inst/s) +host_mem_usage 211252 # Number of bytes of host memory used +host_seconds 6093.26 # Real time elapsed on the host +host_tick_rate 113092899 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated sim_seconds 0.689105 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 28355376 # Nu system.cpu.BPredUnit.condPredicted 229155282 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 342127414 # Number of BP lookups system.cpu.BPredUnit.usedRAS 49327534 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 266706457 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 71745000 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1283484985 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.565260 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.221446 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 584328523 45.53% 45.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 266282466 20.75% 66.27% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 167965913 13.09% 79.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 72752284 5.67% 85.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 49726595 3.87% 88.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 31709768 2.47% 91.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 15719812 1.22% 92.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 23254624 1.81% 94.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 71745000 5.59% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1283484985 # Number of insts commited each cycle -system.cpu.commit.COM:count 2008987604 # Number of instructions committed -system.cpu.commit.COM:fp_insts 71824891 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 39955347 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1778941351 # Number of committed integer instructions. -system.cpu.commit.COM:loads 511070026 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 721864922 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 28343556 # The number of times a branch was mispredicted +system.cpu.commit.branches 266706457 # Number of branches committed +system.cpu.commit.bw_lim_events 71745000 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 649535600 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1283484985 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.565260 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.221446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 584328523 45.53% 45.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 266282466 20.75% 66.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 167965913 13.09% 79.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 72752284 5.67% 85.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 49726595 3.87% 88.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 31709768 2.47% 91.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15719812 1.22% 92.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23254624 1.81% 94.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 71745000 5.59% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1283484985 # Number of insts commited each cycle +system.cpu.commit.count 2008987604 # Number of instructions committed +system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. +system.cpu.commit.function_calls 39955347 # Number of function calls committed. +system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. +system.cpu.commit.loads 511070026 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 721864922 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated system.cpu.cpi 0.755994 # CPI: Cycles Per Instruction @@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses 1530600 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999779 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4095.093805 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999779 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 672939834 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 37287.441089 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 34206.572586 # average overall mshr miss latency @@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse 4095.093805 # Cy system.cpu.dcache.total_refs 670466697 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 272263000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107391 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 27367471 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 11874 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 29084935 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2889732822 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 703418574 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 551446436 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 94589845 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45736 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1252504 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 27367471 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 11874 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 29084935 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 2889732822 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 703418574 # Number of cycles decode is idle +system.cpu.decode.RunCycles 551446436 # Number of cycles decode is running +system.cpu.decode.SquashCycles 94589845 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 45736 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 1252504 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 766409541 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 765750752 # DTB hits @@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses 9774 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.787641 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1613.087790 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.787641 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 343698672 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 15692.605534 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11569.674647 # average overall mshr miss latency @@ -233,21 +233,13 @@ system.cpu.icache.total_refs 343688083 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 134338 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 273848647 # Number of branches executed -system.cpu.iew.EXEC:nop 323098610 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.444031 # Inst execution rate -system.cpu.iew.EXEC:refs 766410290 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 251723816 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1598918223 # num instructions consuming a value -system.cpu.iew.WB:count 1989129822 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.699683 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1118735591 # num instructions producing a value -system.cpu.iew.WB:rate 1.443271 # insts written-back per cycle -system.cpu.iew.WB:sent 1990119861 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 30877415 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 273848647 # Number of branches executed +system.cpu.iew.exec_nop 323098610 # number of nop insts executed +system.cpu.iew.exec_rate 1.444031 # Inst execution rate +system.cpu.iew.exec_refs 766410290 # number of memory reference insts executed +system.cpu.iew.exec_stores 251723816 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 3355843 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 641174032 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 62 # Number of dispatched non-speculative instructions @@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 84105156 # system.cpu.iew.memOrderViolationEvents 1647 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 787925 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 30089490 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1598918223 # num instructions consuming a value +system.cpu.iew.wb_count 1989129822 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.699683 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1118735591 # num instructions producing a value +system.cpu.iew.wb_rate 1.443271 # insts written-back per cycle +system.cpu.iew.wb_sent 1990119861 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 2524191182 # number of integer regfile reads system.cpu.int_regfile_writes 1452780579 # number of integer regfile writes system.cpu.ipc 1.322762 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.322762 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1197059589 57.90% 57.90% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 18404 0.00% 57.90% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.90% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27850873 1.35% 59.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254690 0.40% 59.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204648 0.35% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 550666151 26.63% 86.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 276547322 13.38% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2067604433 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 36218004 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017517 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5127 0.01% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 27845547 76.88% 76.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 8367330 23.10% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1378074830 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.500357 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637561 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 509079016 36.94% 36.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 296362701 21.51% 58.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 259221008 18.81% 77.26% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 152505049 11.07% 88.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 67550622 4.90% 93.23% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 50043003 3.63% 96.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 31234899 2.27% 99.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 9170584 0.67% 99.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 2907948 0.21% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1378074830 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.500211 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1197059589 57.90% 57.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 18404 0.00% 57.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27850873 1.35% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254690 0.40% 59.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204648 0.35% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 550666151 26.63% 86.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 276547322 13.38% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 2067604433 # Type of FU issued system.cpu.iq.fp_alu_accesses 75415887 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 148066359 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 72617602 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 74982161 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 36218004 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017517 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5127 0.01% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27845547 76.88% 76.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8367330 23.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 2028403798 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 5422106783 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 1916512220 # Number of integer instruction queue wakeup accesses @@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined 522645709 # Nu system.cpu.iq.iqSquashedInstsIssued 20671442 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 487946872 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1378074830 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.500357 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.637561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 509079016 36.94% 36.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 296362701 21.51% 58.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 259221008 18.81% 77.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 152505049 11.07% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 67550622 4.90% 93.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 50043003 3.63% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 31234899 2.27% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9170584 0.67% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2907948 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1378074830 # Number of insts issued each cycle +system.cpu.iq.rate 1.500211 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses 1480593 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.881563 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.093197 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 28887.056134 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 3053.875830 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.881563 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.093197 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 1540374 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34301.836494 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.797489 # average overall mshr miss latency @@ -477,28 +477,28 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 1378209168 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 17364773 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 667601 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 717318588 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 9756545 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3251110860 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2789102688 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1858404761 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 538784806 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 94589845 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 9995832 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 473435691 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 109436331 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 3141674529 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 20986 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2820 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 26060288 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 67 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 17364773 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 667601 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 717318588 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 9756545 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 3251110860 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 2789102688 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1858404761 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 538784806 # Number of cycles rename is running +system.cpu.rename.SquashCycles 94589845 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 9995832 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 473435691 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 109436331 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 3141674529 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 20986 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2820 # count of serializing insts renamed +system.cpu.rename.skidInsts 26060288 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 3864626779 # The number of ROB reads system.cpu.rob.rob_writes 5411636382 # The number of ROB writes system.cpu.timesIdled 3611 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 39 # Number of system calls +system.cpu.workload.num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index b7ecd550d..01eff331e 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:05:07 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 855c5964e..f1d866c8d 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1477901 # Simulator instruction rate (inst/s) -host_mem_usage 224424 # Number of bytes of host memory used -host_seconds 1359.35 # Real time elapsed on the host -host_tick_rate 739109964 # Simulator tick rate (ticks/s) +host_inst_rate 5736498 # Simulator instruction rate (inst/s) +host_mem_usage 202144 # Number of bytes of host memory used +host_seconds 350.21 # Real time elapsed on the host +host_tick_rate 2868866718 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 1.004711 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 1332688300 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_mem_refs 722298387 # number of memory refs system.cpu.num_store_insts 210809477 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 39 # Number of system calls +system.cpu.workload.num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 9be1cb679..d0df4a5be 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout index 03731b56d..fd9623671 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:38 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:00:30 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index c88cbd8f6..0966bdbb1 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 584935 # Simulator instruction rate (inst/s) -host_mem_usage 232204 # Number of bytes of host memory used -host_seconds 3434.55 # Real time elapsed on the host -host_tick_rate 819166202 # Simulator tick rate (ticks/s) +host_inst_rate 2647820 # Simulator instruction rate (inst/s) +host_mem_usage 209816 # Number of bytes of host memory used +host_seconds 758.73 # Real time elapsed on the host +host_tick_rate 3708113045 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.813468 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 1530144 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999806 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4095.204626 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999806 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54553.304787 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 10596 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.721886 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1478.423269 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.721886 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 1479815 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.880371 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.094050 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 28848.012979 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 3081.828747 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.880371 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.094050 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 1332688300 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_mem_refs 722298387 # number of memory refs system.cpu.num_store_insts 210809477 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 39 # Number of system calls +system.cpu.workload.num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- |