diff options
Diffstat (limited to 'tests/long/40.perlbmk/ref')
24 files changed, 0 insertions, 11822 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini deleted file mode 100644 index c87170fbe..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ /dev/null @@ -1,535 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -cachePorts=200 -checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 -clock=500 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -defer_registration=false -dispatchWidth=8 -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -phase=0 -predType=tournament -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -squashWidth=8 -store_set_clear_period=250000 -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbDepth=1 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -issueLat=1 -opClass=SimdAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -issueLat=1 -opClass=SimdAddAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -issueLat=1 -opClass=SimdAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -issueLat=1 -opClass=SimdCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -issueLat=1 -opClass=SimdCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -issueLat=1 -opClass=SimdMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -issueLat=1 -opClass=SimdMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -issueLat=1 -opClass=SimdMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -issueLat=1 -opClass=SimdShift -opLat=1 - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -issueLat=1 -opClass=SimdShiftAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -issueLat=1 -opClass=SimdSqrt -opLat=1 - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -issueLat=1 -opClass=SimdFloatAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -issueLat=1 -opClass=SimdFloatAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -issueLat=1 -opClass=SimdFloatCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -issueLat=1 -opClass=SimdFloatCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -issueLat=1 -opClass=SimdFloatDiv -opLat=1 - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -issueLat=1 -opClass=SimdFloatMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -issueLat=1 -opClass=SimdFloatMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -issueLat=1 -opClass=SimdFloatMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -issueLat=1 -opClass=SimdFloatSqrt -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr deleted file mode 100755 index ca52b457d..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(0, 1, ...) -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout deleted file mode 100755 index 2a099e16b..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ /dev/null @@ -1,1388 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:26:04 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -1375000: 2038431008 -1374000: 3487365506 -1373000: 4184770123 -1372000: 1943746837 -1371000: 2651673663 -1370000: 1493817016 -1369000: 2894014801 -1368000: 1932092157 -1367000: 1670009799 -1366000: 828662248 -1365000: 1816650195 -1364000: 4173139012 -1363000: 3990577549 -1362000: 1330366815 -1361000: 3316935553 -1360000: 961300001 -1359000: 344963924 -1358000: 1930356625 -1357000: 1640964266 -1356000: 3777883312 -1355000: 1651132665 -1354000: 1971433151 -1353000: 3024027448 -1352000: 1956387036 -1351000: 1490224841 -1350000: 3286956460 -1349000: 2793131848 -1348000: 2529224907 -1347000: 2622295253 -1346000: 1414103189 -1345000: 3861617587 -1344000: 3506378216 -1343000: 1667466720 -1342000: 2899224065 -1341000: 1681491556 -1340000: 1076311729 -1339000: 4066972664 -1338000: 3438059028 -1337000: 2938359730 -1336000: 1214615378 -1335000: 3814432458 -1334000: 2944038793 -1333000: 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4224852565 -189000: 2330603128 -188000: 2738873539 -187000: 2462336661 -186000: 538134005 -185000: 618406175 -184000: 3258203829 -183000: 3565635398 -182000: 2437456159 -181000: 1103703144 -180000: 3142082412 -179000: 3635072449 -178000: 2831183465 -177000: 3067391696 -176000: 4243880329 -175000: 3847103503 -174000: 1886736895 -173000: 3994782354 -172000: 2180961421 -171000: 2657714328 -170000: 1783032069 -169000: 3288794122 -168000: 4214505744 -167000: 3893811403 -166000: 301673242 -165000: 1008606441 -164000: 4241744599 -163000: 4077366883 -162000: 947408771 -161000: 2893412067 -160000: 4239854096 -159000: 837488883 -158000: 1035341013 -157000: 2979612216 -156000: 622879904 -155000: 2239033946 -154000: 1793603359 -153000: 3403674755 -152000: 1757769702 -151000: 3104338771 -150000: 4050901279 -149000: 1064027760 -148000: 1232980113 -147000: 1940798204 -146000: 1520506974 -145000: 1602654645 -144000: 3827165041 -143000: 2333560581 -142000: 1078945096 -141000: 4164769913 -140000: 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3690432221 -88000: 1892056918 -87000: 1120722079 -86000: 2675052236 -85000: 4165748502 -84000: 10230467 -83000: 4138070209 -82000: 1570296924 -81000: 3126342757 -80000: 598265835 -79000: 541475291 -78000: 2784920265 -77000: 4169891577 -76000: 1101249184 -75000: 2090307927 -74000: 3780559777 -73000: 19873425 -72000: 1118190767 -71000: 3485912405 -70000: 1322638834 -69000: 1096526516 -68000: 1370553703 -67000: 3631120381 -66000: 1806420191 -65000: 2701118072 -64000: 483879470 -63000: 2124403158 -62000: 1877513812 -61000: 1289006766 -60000: 3733667461 -59000: 3457358686 -58000: 732502949 -57000: 3971773677 -56000: 883589946 -55000: 290212168 -54000: 2244967385 -53000: 3848247179 -52000: 2228476206 -51000: 2372703555 -50000: 1200411530 -49000: 2060190456 -48000: 2511902942 -47000: 4007272287 -46000: 2854231300 -45000: 2518671311 -44000: 815143404 -43000: 1972543143 -42000: 3063716128 -41000: 3326571310 -40000: 3180391453 -39000: 2568545510 -38000: 573110821 -37000: 3814257324 -36000: 4163248735 -35000: 943584186 -34000: 387069186 -33000: 3519377243 -32000: 3861206003 -31000: 2378381393 -30000: 3259365221 -29000: 3960625204 -28000: 3476394666 -27000: 1995310421 -26000: 1884341166 -25000: 3181801013 -24000: 116492838 -23000: 3276567587 -22000: 3693343729 -21000: 2595820568 -20000: 2397879436 -19000: 2692679578 -18000: 2368648652 -17000: 3098196844 -16000: 3913788179 -15000: 1240694507 -14000: 1586030084 -13000: 1211450031 -12000: 3458253062 -11000: 1804606651 -10000: 2128587109 -9000: 1894810186 -8000: 2221431098 -7000: 113605713 -6000: 4020003580 -5000: 2988041351 -4000: 2310084217 -3000: 1475476779 -2000: 760651391 -1000: 4031656975 -0: 2206428413 -Exiting @ tick 643030478500 because target called exit() diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt deleted file mode 100644 index 90210da82..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ /dev/null @@ -1,526 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.643030 # Number of seconds simulated -sim_ticks 643030478500 # Number of ticks simulated -final_tick 643030478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153915 # Simulator instruction rate (inst/s) -host_tick_rate 54289503 # Simulator tick rate (ticks/s) -host_mem_usage 215008 # Number of bytes of host memory used -host_seconds 11844.47 # Real time elapsed on the host -sim_insts 1823043370 # Number of instructions simulated -system.physmem.bytes_read 94779264 # Number of bytes read from this memory -system.physmem.bytes_inst_read 185664 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4281472 # Number of bytes written to this memory -system.physmem.num_reads 1480926 # Number of read requests responded to by this memory -system.physmem.num_writes 66898 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 147394668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 288733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 6658272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 154052940 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 520282071 # DTB read hits -system.cpu.dtb.read_misses 658976 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 520941047 # DTB read accesses -system.cpu.dtb.write_hits 283837075 # DTB write hits -system.cpu.dtb.write_misses 53680 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283890755 # DTB write accesses -system.cpu.dtb.data_hits 804119146 # DTB hits -system.cpu.dtb.data_misses 712656 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 804831802 # DTB accesses -system.cpu.itb.fetch_hits 398310361 # ITB hits -system.cpu.itb.fetch_misses 225 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 398310586 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1286060958 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 402586298 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 267183275 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 28898117 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 333702913 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 271687015 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 60998120 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7269 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 415096525 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3352093116 # Number of instructions fetch has processed -system.cpu.fetch.Branches 402586298 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 332685135 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 645195661 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 165271358 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 89752324 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 4176 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 398310361 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11197226 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1285935042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.606736 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.132660 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 640739381 49.83% 49.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57260959 4.45% 54.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 45174683 3.51% 57.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 73956325 5.75% 63.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 134643957 10.47% 74.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 43704830 3.40% 77.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 44948525 3.50% 80.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8228368 0.64% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 237278014 18.45% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1285935042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.313038 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.606481 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 451176980 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 71498937 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 618592802 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8792068 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 135874255 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 30910962 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12070 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3252787569 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 45959 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 135874255 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 481268394 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 29024257 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 25510 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 595950971 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43791655 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3151351284 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 355 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 750555 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 36590752 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2105050619 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3698513195 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3586317765 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 112195430 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 720081549 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4177 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 124172087 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 732020123 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 345520616 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 66357929 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8901879 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2642218507 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 75 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2155449111 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17941201 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 818701684 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 780988431 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 36 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1285935042 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.676173 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.767949 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 465245543 36.18% 36.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 229606292 17.86% 54.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 242969112 18.89% 72.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 129449912 10.07% 83.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 105111994 8.17% 91.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 71454382 5.56% 96.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 23774402 1.85% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15398679 1.20% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2924726 0.23% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1285935042 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 19151 0.06% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 21356146 65.69% 65.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11134345 34.25% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1238361266 57.45% 57.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 16703 0.00% 57.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27850917 1.29% 58.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254688 0.38% 59.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204646 0.33% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 584304865 27.11% 86.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 289453270 13.43% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2155449111 # Type of FU issued -system.cpu.iq.rate 1.676009 # Inst issue rate -system.cpu.iq.fu_busy_cnt 32509642 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015083 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5498808910 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3382020905 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1990959088 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 148475197 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 78969876 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 72622847 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2112315501 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 75640500 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67702370 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 220950097 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 171000 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 71734 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 134725720 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4434 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 135874255 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3818188 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 203306 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3005431260 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2750522 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 732020123 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 345520616 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 75 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 131111 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4921 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 71734 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 30723187 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 903682 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 31626869 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2066254472 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 520941220 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 89194639 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363212678 # number of nop insts executed -system.cpu.iew.exec_refs 804832688 # number of memory reference insts executed -system.cpu.iew.exec_branches 279771397 # Number of branches executed -system.cpu.iew.exec_stores 283891468 # Number of stores executed -system.cpu.iew.exec_rate 1.606654 # Inst execution rate -system.cpu.iew.wb_sent 2065581707 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2063581935 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1176945723 # num instructions producing a value -system.cpu.iew.wb_consumers 1742555439 # num instructions consuming a value -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.604576 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675414 # average fanout of values written-back -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 979738658 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 28886163 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1150060787 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.746853 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.513737 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 543040951 47.22% 47.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 216685952 18.84% 66.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119778809 10.41% 76.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 61132291 5.32% 81.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 44136002 3.84% 85.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24968433 2.17% 87.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19265020 1.68% 89.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16055764 1.40% 90.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 104997565 9.13% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1150060787 # Number of insts commited each cycle -system.cpu.commit.count 2008987604 # Number of instructions committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 721864922 # Number of memory references committed -system.cpu.commit.loads 511070026 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 266706457 # Number of branches committed -system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. -system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 104997565 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4028153074 # The number of ROB reads -system.cpu.rob.rob_writes 6113513811 # The number of ROB writes -system.cpu.timesIdled 3507 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 125916 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1823043370 # Number of Instructions Simulated -system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.705447 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.705447 # CPI: Total CPI of All Threads -system.cpu.ipc 1.417540 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.417540 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2630724063 # number of integer regfile reads -system.cpu.int_regfile_writes 1493026464 # number of integer regfile writes -system.cpu.fp_regfile_reads 77824314 # number of floating regfile reads -system.cpu.fp_regfile_writes 52830391 # number of floating regfile writes -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8239 # number of replacements -system.cpu.icache.tagsinuse 1650.873085 # Cycle average of tags in use -system.cpu.icache.total_refs 398299261 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9946 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 40046.175447 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1650.873085 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.806090 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 398299261 # number of ReadReq hits -system.cpu.icache.demand_hits 398299261 # number of demand (read+write) hits -system.cpu.icache.overall_hits 398299261 # number of overall hits -system.cpu.icache.ReadReq_misses 11100 # number of ReadReq misses -system.cpu.icache.demand_misses 11100 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11100 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 182477500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 182477500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 182477500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 398310361 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 398310361 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 398310361 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000028 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 16439.414414 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 16439.414414 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 16439.414414 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1153 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1153 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1153 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 9947 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 9947 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 9947 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 119555000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 119555000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 119555000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12019.201769 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12019.201769 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12019.201769 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527592 # number of replacements -system.cpu.dcache.tagsinuse 4095.113983 # Cycle average of tags in use -system.cpu.dcache.total_refs 660890207 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1531688 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 431.478347 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 255376000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.113983 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999784 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 450646939 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 210243259 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 660890198 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 660890198 # number of overall hits -system.cpu.dcache.ReadReq_misses 1928305 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 551637 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2479942 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2479942 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 71444429000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 20878144491 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 59000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 92322573491 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 92322573491 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 452575244 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 663370140 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 663370140 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.004261 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.002617 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.003738 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.003738 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 37050.377923 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 37847.614448 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 29500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 37227.714798 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 37227.714798 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 79500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5678.571429 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20500 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107326 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 468223 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 480032 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 948255 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 948255 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1460082 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 71605 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1531687 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1531687 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 49942277500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2493130000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 52435407500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 52435407500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003226 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.090909 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002309 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002309 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34205.118274 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34817.819985 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34233.761532 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34233.761532 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480630 # number of replacements -system.cpu.l2cache.tagsinuse 31935.913288 # Cycle average of tags in use -system.cpu.l2cache.total_refs 63583 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513317 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.042016 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 28876.475418 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3059.437870 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.881240 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.093367 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 55959 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107326 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 4750 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 60709 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 60709 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1414071 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 66855 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 1480926 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 1480926 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 48513510000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2349021500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 50862531500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 50862531500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1470030 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107326 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 71605 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1541635 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1541635 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.961933 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.933664 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.960620 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.960620 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34307.690349 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.063122 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34345.086453 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34345.086453 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7500 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 66898 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1414071 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 66855 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1480926 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1480926 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 43837380500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2147695000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 45985075500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 45985075500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961933 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933664 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.960620 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.960620 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.834117 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32124.672799 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.568748 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.568748 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini deleted file mode 100644 index a895468a4..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ /dev/null @@ -1,102 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=AtomicSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -simulate_data_stalls=false -simulate_inst_stalls=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr deleted file mode 100755 index ca52b457d..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(0, 1, ...) -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout deleted file mode 100755 index 67c7a90bd..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ /dev/null @@ -1,1388 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:26:36 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. 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/dev/null @@ -1,77 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.004711 # Number of seconds simulated -sim_ticks 1004710587000 # Number of ticks simulated -final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4051601 # Simulator instruction rate (inst/s) -host_tick_rate 2026237516 # Simulator tick rate (ticks/s) -host_mem_usage 204820 # Number of bytes of host memory used -host_seconds 495.85 # Real time elapsed on the host -sim_insts 2008987605 # Number of instructions simulated -system.physmem.bytes_read 11607100996 # Number of bytes read from this memory -system.physmem.bytes_inst_read 8037684280 # Number of instructions bytes read from this memory -system.physmem.bytes_written 1586125963 # Number of bytes written to this memory -system.physmem.num_reads 2520491096 # Number of read requests responded to by this memory -system.physmem.num_writes 210794896 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11552681087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999999586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1578689409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 13131370496 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 511070026 # DTB read hits -system.cpu.dtb.read_misses 418884 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 511488910 # DTB read accesses -system.cpu.dtb.write_hits 210794896 # DTB write hits -system.cpu.dtb.write_misses 14581 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 210809477 # DTB write accesses -system.cpu.dtb.data_hits 721864922 # DTB hits -system.cpu.dtb.data_misses 433465 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 722298387 # DTB accesses -system.cpu.itb.fetch_hits 2009421070 # ITB hits -system.cpu.itb.fetch_misses 105 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2009421175 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 2009421175 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2008987605 # Number of instructions executed -system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses -system.cpu.num_func_calls 79910682 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls -system.cpu.num_int_insts 1779374816 # number of integer instructions -system.cpu.num_fp_insts 71831671 # number of float instructions -system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read -system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written -system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read -system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written -system.cpu.num_mem_refs 722298387 # number of memory refs -system.cpu.num_load_insts 511488910 # Number of load instructions -system.cpu.num_store_insts 210809477 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2009421175 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini deleted file mode 100644 index f60b78837..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ /dev/null @@ -1,205 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr deleted file mode 100755 index ca52b457d..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(0, 1, ...) -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout deleted file mode 100755 index e767ec1c4..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ /dev/null @@ -1,1388 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:28:03 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -1375000: 2038431008 -1374000: 3487365506 -1373000: 4184770123 -1372000: 1943746837 -1371000: 2651673663 -1370000: 1493817016 -1369000: 2894014801 -1368000: 1932092157 -1367000: 1670009799 -1366000: 828662248 -1365000: 1816650195 -1364000: 4173139012 -1363000: 3990577549 -1362000: 1330366815 -1361000: 3316935553 -1360000: 961300001 -1359000: 344963924 -1358000: 1930356625 -1357000: 1640964266 -1356000: 3777883312 -1355000: 1651132665 -1354000: 1971433151 -1353000: 3024027448 -1352000: 1956387036 -1351000: 1490224841 -1350000: 3286956460 -1349000: 2793131848 -1348000: 2529224907 -1347000: 2622295253 -1346000: 1414103189 -1345000: 3861617587 -1344000: 3506378216 -1343000: 1667466720 -1342000: 2899224065 -1341000: 1681491556 -1340000: 1076311729 -1339000: 4066972664 -1338000: 3438059028 -1337000: 2938359730 -1336000: 1214615378 -1335000: 3814432458 -1334000: 2944038793 -1333000: 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4163248735 -35000: 943584186 -34000: 387069186 -33000: 3519377243 -32000: 3861206003 -31000: 2378381393 -30000: 3259365221 -29000: 3960625204 -28000: 3476394666 -27000: 1995310421 -26000: 1884341166 -25000: 3181801013 -24000: 116492838 -23000: 3276567587 -22000: 3693343729 -21000: 2595820568 -20000: 2397879436 -19000: 2692679578 -18000: 2368648652 -17000: 3098196844 -16000: 3913788179 -15000: 1240694507 -14000: 1586030084 -13000: 1211450031 -12000: 3458253062 -11000: 1804606651 -10000: 2128587109 -9000: 1894810186 -8000: 2221431098 -7000: 113605713 -6000: 4020003580 -5000: 2988041351 -4000: 2310084217 -3000: 1475476779 -2000: 760651391 -1000: 4031656975 -0: 2206428413 -Exiting @ tick 2813467842000 because target called exit() diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt deleted file mode 100644 index 668a6f1dd..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ /dev/null @@ -1,266 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.813468 # Number of seconds simulated -sim_ticks 2813467842000 # Number of ticks simulated -final_tick 2813467842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1954286 # Simulator instruction rate (inst/s) -host_tick_rate 2736861040 # Simulator tick rate (ticks/s) -host_mem_usage 213480 # Number of bytes of host memory used -host_seconds 1027.99 # Real time elapsed on the host -sim_insts 2008987605 # Number of instructions simulated -system.physmem.bytes_read 94708160 # Number of bytes read from this memory -system.physmem.bytes_inst_read 152128 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4281472 # Number of bytes written to this memory -system.physmem.num_reads 1479815 # Number of read requests responded to by this memory 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-system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.961978 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.929411 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.960457 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.960457 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 66898 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1412942 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 66873 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1479815 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1479815 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56517680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2674920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 59192600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 59192600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961978 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.929411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.960457 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.960457 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini deleted file mode 100644 index 7e5e4838d..000000000 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ /dev/null @@ -1,535 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -cachePorts=200 -checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 -clock=500 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -defer_registration=false -dispatchWidth=8 -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -phase=0 -predType=tournament -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -squashWidth=8 -store_set_clear_period=250000 -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbDepth=1 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=ArmTLB -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -issueLat=1 -opClass=SimdAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -issueLat=1 -opClass=SimdAddAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -issueLat=1 -opClass=SimdAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -issueLat=1 -opClass=SimdCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -issueLat=1 -opClass=SimdCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -issueLat=1 -opClass=SimdMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -issueLat=1 -opClass=SimdMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -issueLat=1 -opClass=SimdMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -issueLat=1 -opClass=SimdShift -opLat=1 - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -issueLat=1 -opClass=SimdShiftAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -issueLat=1 -opClass=SimdSqrt -opLat=1 - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -issueLat=1 -opClass=SimdFloatAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -issueLat=1 -opClass=SimdFloatAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -issueLat=1 -opClass=SimdFloatCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -issueLat=1 -opClass=SimdFloatCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -issueLat=1 -opClass=SimdFloatDiv -opLat=1 - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -issueLat=1 -opClass=SimdFloatMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -issueLat=1 -opClass=SimdFloatMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -issueLat=1 -opClass=SimdFloatMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -issueLat=1 -opClass=SimdFloatSqrt -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=ArmTLB -size=64 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr deleted file mode 100755 index cba73e085..000000000 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: fcntl64(3, 2) passed through to host -hack: be nice to actually delete the event here diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout deleted file mode 100755 index af8b043ac..000000000 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ /dev/null @@ -1,1388 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:08:55 -gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -1375000: 2038431008 -1374000: 3487365506 -1373000: 4184770123 -1372000: 1943746837 -1371000: 2651673663 -1370000: 1493817016 -1369000: 2894014801 -1368000: 1932092157 -1367000: 1670009799 -1366000: 828662248 -1365000: 1816650195 -1364000: 4173139012 -1363000: 3990577549 -1362000: 1330366815 -1361000: 3316935553 -1360000: 961300001 -1359000: 344963924 -1358000: 1930356625 -1357000: 1640964266 -1356000: 3777883312 -1355000: 1651132665 -1354000: 1971433151 -1353000: 3024027448 -1352000: 1956387036 -1351000: 1490224841 -1350000: 3286956460 -1349000: 2793131848 -1348000: 2529224907 -1347000: 2622295253 -1346000: 1414103189 -1345000: 3861617587 -1344000: 3506378216 -1343000: 1667466720 -1342000: 2899224065 -1341000: 1681491556 -1340000: 1076311729 -1339000: 4066972664 -1338000: 3438059028 -1337000: 2938359730 -1336000: 1214615378 -1335000: 3814432458 -1334000: 2944038793 -1333000: 3428045644 -1332000: 2815822229 -1331000: 1093465585 -1330000: 3012217108 -1329000: 2230916791 -1328000: 208547885 -1327000: 3592585825 -1326000: 3948677052 -1325000: 1817805162 -1324000: 135366494 -1323000: 3309148112 -1322000: 1685035744 -1321000: 3293068577 -1320000: 4097808567 -1319000: 1594097274 -1318000: 2607196971 -1317000: 1763785306 -1316000: 2157394178 -1315000: 2399031328 -1314000: 2954547004 -1313000: 82348686 -1312000: 3120930785 -1311000: 2192747320 -1310000: 1580299400 -1309000: 4085061477 -1308000: 3627048345 -1307000: 3756533178 -1306000: 77997329 -1305000: 1343359499 -1304000: 1124031730 -1303000: 1161755432 -1302000: 1855858423 -1301000: 3985872257 -1300000: 3188250811 -1299000: 3621615933 -1298000: 962624248 -1297000: 447138785 -1296000: 1459144309 -1295000: 3454504226 -1294000: 2154913347 -1293000: 2356291788 -1292000: 458348817 -1291000: 3639562699 -1290000: 3596847973 -1289000: 117168222 -1288000: 3531023849 -1287000: 3135920051 -1286000: 234987844 -1285000: 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3690432221 -88000: 1892056918 -87000: 1120722079 -86000: 2675052236 -85000: 4165748502 -84000: 10230467 -83000: 4138070209 -82000: 1570296924 -81000: 3126342757 -80000: 598265835 -79000: 541475291 -78000: 2784920265 -77000: 4169891577 -76000: 1101249184 -75000: 2090307927 -74000: 3780559777 -73000: 19873425 -72000: 1118190767 -71000: 3485912405 -70000: 1322638834 -69000: 1096526516 -68000: 1370553703 -67000: 3631120381 -66000: 1806420191 -65000: 2701118072 -64000: 483879470 -63000: 2124403158 -62000: 1877513812 -61000: 1289006766 -60000: 3733667461 -59000: 3457358686 -58000: 732502949 -57000: 3971773677 -56000: 883589946 -55000: 290212168 -54000: 2244967385 -53000: 3848247179 -52000: 2228476206 -51000: 2372703555 -50000: 1200411530 -49000: 2060190456 -48000: 2511902942 -47000: 4007272287 -46000: 2854231300 -45000: 2518671311 -44000: 815143404 -43000: 1972543143 -42000: 3063716128 -41000: 3326571310 -40000: 3180391453 -39000: 2568545510 -38000: 573110821 -37000: 3814257324 -36000: 4163248735 -35000: 943584186 -34000: 387069186 -33000: 3519377243 -32000: 3861206003 -31000: 2378381393 -30000: 3259365221 -29000: 3960625204 -28000: 3476394666 -27000: 1995310421 -26000: 1884341166 -25000: 3181801013 -24000: 116492838 -23000: 3276567587 -22000: 3693343729 -21000: 2595820568 -20000: 2397879436 -19000: 2692679578 -18000: 2368648652 -17000: 3098196844 -16000: 3913788179 -15000: 1240694507 -14000: 1586030084 -13000: 1211450031 -12000: 3458253062 -11000: 1804606651 -10000: 2128587109 -9000: 1894810186 -8000: 2221431098 -7000: 113605713 -6000: 4020003580 -5000: 2988041351 -4000: 2310084217 -3000: 1475476779 -2000: 760651391 -1000: 4031656975 -0: 2206428413 -Exiting @ tick 708403313500 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt deleted file mode 100644 index 7b72f7ce4..000000000 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ /dev/null @@ -1,544 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.708403 # Number of seconds simulated -sim_ticks 708403313500 # Number of ticks simulated -final_tick 708403313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118434 # Simulator instruction rate (inst/s) -host_tick_rate 44501063 # Simulator tick rate (ticks/s) -host_mem_usage 226576 # Number of bytes of host memory used -host_seconds 15918.80 # Real time elapsed on the host -sim_insts 1885333786 # Number of instructions simulated -system.physmem.bytes_read 94812032 # Number of bytes read from this memory -system.physmem.bytes_inst_read 200960 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4230336 # Number of bytes written to this memory -system.physmem.num_reads 1481438 # Number of read requests responded to by this memory -system.physmem.num_writes 66099 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 133839058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 283680 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5971649 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 139810707 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1416806628 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 503033036 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 388160087 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 32894916 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 402481986 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 281923865 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 59796610 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2840141 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 410550003 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2542460473 # Number of instructions fetch has processed -system.cpu.fetch.Branches 503033036 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 341720475 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 682921340 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 205013758 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 105428035 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2115 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 34704 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 384233965 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12151873 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1365478165 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.588855 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.160415 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 682595631 49.99% 49.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48342952 3.54% 53.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 108702790 7.96% 61.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 62379051 4.57% 66.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 89292584 6.54% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 54148565 3.97% 76.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35470304 2.60% 79.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 34965610 2.56% 81.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249580678 18.28% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1365478165 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.355047 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.794501 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 455361727 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 85217138 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 647145530 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 11223736 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 166530034 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 68649997 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12124 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3424361675 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 24057 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 166530034 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 496888956 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 29110139 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3718079 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 615295356 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53935601 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3298153337 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4569845 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42334817 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3261061532 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 15624755618 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14989571898 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 635183720 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993153599 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1267907933 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 310582 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 306325 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 155884977 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1045137132 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 527476218 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 35886570 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 45267364 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3077754179 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 303954 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2619291842 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18689867 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1192085861 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2899457281 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 92624 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1365478165 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.918223 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.900205 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 480779837 35.21% 35.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182587607 13.37% 48.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 216609244 15.86% 64.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 179766275 13.17% 77.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 150868799 11.05% 88.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 89721779 6.57% 95.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 48758870 3.57% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11536421 0.84% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4849333 0.36% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1365478165 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2044403 2.26% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23929 0.03% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55649007 61.42% 63.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 32885475 36.30% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1200920026 45.85% 45.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11234109 0.43% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.26% 46.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5505406 0.21% 46.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 24362118 0.93% 47.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 895924024 34.20% 81.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 473094394 18.06% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2619291842 # Type of FU issued -system.cpu.iq.rate 1.848729 # Inst issue rate -system.cpu.iq.fu_busy_cnt 90602814 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.034591 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6584849993 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4170838685 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2409550549 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 128504537 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 99358414 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 57073276 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2644267181 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 65627475 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 71974387 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 413748263 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 264274 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1389738 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 250479234 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 166530034 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16377218 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1473925 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3078126585 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12745051 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1045137132 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 527476218 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 292477 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1470662 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 212 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1389738 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 34580674 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8873578 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 43454252 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2534450261 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 842463670 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 84841581 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 68452 # number of nop insts executed -system.cpu.iew.exec_refs 1294415982 # number of memory reference insts executed -system.cpu.iew.exec_branches 344601931 # Number of branches executed -system.cpu.iew.exec_stores 451952312 # Number of stores executed -system.cpu.iew.exec_rate 1.788847 # Inst execution rate -system.cpu.iew.wb_sent 2495608341 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2466623825 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1448525550 # num instructions producing a value -system.cpu.iew.wb_consumers 2707902616 # num instructions consuming a value -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.740974 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534925 # average fanout of values written-back -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1885344802 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 1192782047 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 38420798 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1198948133 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.572499 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.256451 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 532143962 44.38% 44.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 299077946 24.95% 69.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 106761313 8.90% 78.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 77538501 6.47% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 53400435 4.45% 89.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23357302 1.95% 91.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17130441 1.43% 92.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9348033 0.78% 93.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 80190200 6.69% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1198948133 # Number of insts commited each cycle -system.cpu.commit.count 1885344802 # Number of instructions committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385853 # Number of memory references committed -system.cpu.commit.loads 631388869 # Number of loads committed -system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291350232 # Number of branches committed -system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705623 # Number of committed integer instructions. -system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 80190200 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4196866437 # The number of ROB reads -system.cpu.rob.rob_writes 6322804382 # The number of ROB writes -system.cpu.timesIdled 1340913 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 51328463 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1885333786 # Number of Instructions Simulated -system.cpu.committedInsts_total 1885333786 # Number of Instructions Simulated -system.cpu.cpi 0.751488 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.751488 # CPI: Total CPI of All Threads -system.cpu.ipc 1.330692 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.330692 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12567203807 # number of integer regfile reads -system.cpu.int_regfile_writes 2360160094 # number of integer regfile writes -system.cpu.fp_regfile_reads 68800597 # number of floating regfile reads -system.cpu.fp_regfile_writes 50187558 # number of floating regfile writes -system.cpu.misc_regfile_reads 3980455481 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776276 # number of misc regfile writes -system.cpu.icache.replacements 27305 # number of replacements -system.cpu.icache.tagsinuse 1638.856970 # Cycle average of tags in use -system.cpu.icache.total_refs 384199729 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 28984 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13255.579941 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1638.856970 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.800223 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 384199814 # number of ReadReq hits -system.cpu.icache.demand_hits 384199814 # number of demand (read+write) hits -system.cpu.icache.overall_hits 384199814 # number of overall hits -system.cpu.icache.ReadReq_misses 34151 # number of ReadReq misses -system.cpu.icache.demand_misses 34151 # number of demand (read+write) misses -system.cpu.icache.overall_misses 34151 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 301141000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 301141000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 301141000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 384233965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 384233965 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 384233965 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 8817.926269 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 8817.926269 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 8817.926269 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 772 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 772 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 772 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 33379 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 33379 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 33379 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 180850500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 180850500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 180850500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5418.092214 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5418.092214 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5418.092214 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1531788 # number of replacements -system.cpu.dcache.tagsinuse 4094.791932 # Cycle average of tags in use -system.cpu.dcache.total_refs 1029449306 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1535884 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 670.265011 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 305577000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.791932 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999705 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 753290045 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 276118528 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 15313 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 11672 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 1029408573 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1029408573 # number of overall hits -system.cpu.dcache.ReadReq_misses 1938158 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 817150 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2755308 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2755308 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 69348240500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 28488261000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 97836501500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 97836501500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 755228203 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 15316 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 11672 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 1032163881 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 1032163881 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002566 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.002951 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000196 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.002669 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002669 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35780.488742 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 34862.951722 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35508.372022 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35508.372022 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 62000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15500 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 106544 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 474971 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 740057 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1215028 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1215028 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1463187 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 77093 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1540280 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1540280 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 50020048000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2484862000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 52504910000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 52504910000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001937 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001492 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001492 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34185.683716 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32232.005500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34087.899603 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34087.899603 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480006 # number of replacements -system.cpu.l2cache.tagsinuse 31970.917218 # Cycle average of tags in use -system.cpu.l2cache.total_refs 84924 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512726 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.056140 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 29008.328912 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 2962.588306 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.885264 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.090411 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 76788 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 106544 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 6616 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 83404 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 83404 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1415384 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 4391 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 66082 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 1481466 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 1481466 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 48555371000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2252634000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 50808005000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 50808005000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1492172 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 106544 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 4395 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 72698 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1564870 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1564870 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.948539 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.999090 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.908993 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.946702 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.946702 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34305.440078 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34088.465845 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34295.761766 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34295.761766 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 66099 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 28 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 28 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 28 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1415356 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 4391 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1481438 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1481438 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 43973863500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 136121000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048597500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 46022461000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 46022461000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948521 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999090 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908993 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.946684 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.946684 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31069.118653 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.839866 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31066.072964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31066.072964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini deleted file mode 100644 index 6a275dc9a..000000000 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ /dev/null @@ -1,102 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=AtomicSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -simulate_data_stalls=false -simulate_inst_stalls=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] - -[system.cpu.dtb] -type=ArmTLB -size=64 - -[system.cpu.itb] -type=ArmTLB -size=64 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr deleted file mode 100755 index cba73e085..000000000 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: fcntl64(3, 2) passed through to host -hack: be nice to actually delete the event here diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout deleted file mode 100755 index dd29e750e..000000000 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ /dev/null @@ -1,1388 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:17:45 -gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. 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1004088705 -139000: 1918334274 -138000: 2376094733 -137000: 2114404244 -136000: 610887654 -135000: 2061314834 -134000: 2934949429 -133000: 1384359308 -132000: 2214638498 -131000: 4091637905 -130000: 1178600936 -129000: 3673332079 -128000: 335936353 -127000: 1680711257 -126000: 1535342908 -125000: 1797602927 -124000: 1277174958 -123000: 3114077321 -122000: 149498793 -121000: 864366602 -120000: 104510626 -119000: 1518395286 -118000: 3111302078 -117000: 3110116836 -116000: 3233967498 -115000: 1017896311 -114000: 692827001 -113000: 3779537224 -112000: 2905474934 -111000: 3465999202 -110000: 1915694049 -109000: 2628022627 -108000: 875271541 -107000: 2022225002 -106000: 1671971011 -105000: 3334748297 -104000: 1332184097 -103000: 1555681497 -102000: 3406253965 -101000: 4045141299 -100000: 3058680000 -99000: 555036606 -98000: 46275609 -97000: 3853135904 -96000: 4229006385 -95000: 4108164708 -94000: 2566945975 -93000: 3797900910 -92000: 3355992329 -91000: 1635484145 -90000: 1382023482 -89000: 3690432221 -88000: 1892056918 -87000: 1120722079 -86000: 2675052236 -85000: 4165748502 -84000: 10230467 -83000: 4138070209 -82000: 1570296924 -81000: 3126342757 -80000: 598265835 -79000: 541475291 -78000: 2784920265 -77000: 4169891577 -76000: 1101249184 -75000: 2090307927 -74000: 3780559777 -73000: 19873425 -72000: 1118190767 -71000: 3485912405 -70000: 1322638834 -69000: 1096526516 -68000: 1370553703 -67000: 3631120381 -66000: 1806420191 -65000: 2701118072 -64000: 483879470 -63000: 2124403158 -62000: 1877513812 -61000: 1289006766 -60000: 3733667461 -59000: 3457358686 -58000: 732502949 -57000: 3971773677 -56000: 883589946 -55000: 290212168 -54000: 2244967385 -53000: 3848247179 -52000: 2228476206 -51000: 2372703555 -50000: 1200411530 -49000: 2060190456 -48000: 2511902942 -47000: 4007272287 -46000: 2854231300 -45000: 2518671311 -44000: 815143404 -43000: 1972543143 -42000: 3063716128 -41000: 3326571310 -40000: 3180391453 -39000: 2568545510 -38000: 573110821 -37000: 3814257324 -36000: 4163248735 -35000: 943584186 -34000: 387069186 -33000: 3519377243 -32000: 3861206003 -31000: 2378381393 -30000: 3259365221 -29000: 3960625204 -28000: 3476394666 -27000: 1995310421 -26000: 1884341166 -25000: 3181801013 -24000: 116492838 -23000: 3276567587 -22000: 3693343729 -21000: 2595820568 -20000: 2397879436 -19000: 2692679578 -18000: 2368648652 -17000: 3098196844 -16000: 3913788179 -15000: 1240694507 -14000: 1586030084 -13000: 1211450031 -12000: 3458253062 -11000: 1804606651 -10000: 2128587109 -9000: 1894810186 -8000: 2221431098 -7000: 113605713 -6000: 4020003580 -5000: 2988041351 -4000: 2310084217 -3000: 1475476779 -2000: 760651391 -1000: 4031656975 -0: 2206428413 -Exiting @ tick 945613131000 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt deleted file mode 100644 index 49ae2817e..000000000 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ /dev/null @@ -1,87 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.945613 # Number of seconds simulated -sim_ticks 945613131000 # Number of ticks simulated -final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2997522 # Simulator instruction rate (inst/s) -host_tick_rate 1503443037 # Simulator tick rate (ticks/s) -host_mem_usage 215364 # Number of bytes of host memory used -host_seconds 628.97 # Real time elapsed on the host -sim_insts 1885336367 # Number of instructions simulated -system.physmem.bytes_read 8025491315 # Number of bytes read from this memory -system.physmem.bytes_inst_read 5561086040 # Number of instructions bytes read from this memory -system.physmem.bytes_written 1123958396 # Number of bytes written to this memory -system.physmem.num_reads 2010616909 # Number of read requests responded to by this memory -system.physmem.num_writes 276945663 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 8487076852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 5880931491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1188602780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9675679632 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1891226263 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1885336367 # Number of instructions executed -system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_func_calls 80344203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls -system.cpu.num_int_insts 1653698876 # number of integer instructions -system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 8601515950 # number of times the integer registers were read -system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written -system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read -system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_mem_refs 908382480 # number of memory refs -system.cpu.num_load_insts 631387182 # Number of load instructions -system.cpu.num_store_insts 276995298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1891226263 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini deleted file mode 100644 index 01aaafc03..000000000 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ /dev/null @@ -1,205 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=ArmTLB -size=64 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=ArmTLB -size=64 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr deleted file mode 100755 index cba73e085..000000000 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: fcntl64(3, 2) passed through to host -hack: be nice to actually delete the event here diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout deleted file mode 100755 index df0dd80b9..000000000 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout +++ /dev/null @@ -1,1388 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:28:26 -gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -1375000: 2038431008 -1374000: 3487365506 -1373000: 4184770123 -1372000: 1943746837 -1371000: 2651673663 -1370000: 1493817016 -1369000: 2894014801 -1368000: 1932092157 -1367000: 1670009799 -1366000: 828662248 -1365000: 1816650195 -1364000: 4173139012 -1363000: 3990577549 -1362000: 1330366815 -1361000: 3316935553 -1360000: 961300001 -1359000: 344963924 -1358000: 1930356625 -1357000: 1640964266 -1356000: 3777883312 -1355000: 1651132665 -1354000: 1971433151 -1353000: 3024027448 -1352000: 1956387036 -1351000: 1490224841 -1350000: 3286956460 -1349000: 2793131848 -1348000: 2529224907 -1347000: 2622295253 -1346000: 1414103189 -1345000: 3861617587 -1344000: 3506378216 -1343000: 1667466720 -1342000: 2899224065 -1341000: 1681491556 -1340000: 1076311729 -1339000: 4066972664 -1338000: 3438059028 -1337000: 2938359730 -1336000: 1214615378 -1335000: 3814432458 -1334000: 2944038793 -1333000: 3428045644 -1332000: 2815822229 -1331000: 1093465585 -1330000: 3012217108 -1329000: 2230916791 -1328000: 208547885 -1327000: 3592585825 -1326000: 3948677052 -1325000: 1817805162 -1324000: 135366494 -1323000: 3309148112 -1322000: 1685035744 -1321000: 3293068577 -1320000: 4097808567 -1319000: 1594097274 -1318000: 2607196971 -1317000: 1763785306 -1316000: 2157394178 -1315000: 2399031328 -1314000: 2954547004 -1313000: 82348686 -1312000: 3120930785 -1311000: 2192747320 -1310000: 1580299400 -1309000: 4085061477 -1308000: 3627048345 -1307000: 3756533178 -1306000: 77997329 -1305000: 1343359499 -1304000: 1124031730 -1303000: 1161755432 -1302000: 1855858423 -1301000: 3985872257 -1300000: 3188250811 -1299000: 3621615933 -1298000: 962624248 -1297000: 447138785 -1296000: 1459144309 -1295000: 3454504226 -1294000: 2154913347 -1293000: 2356291788 -1292000: 458348817 -1291000: 3639562699 -1290000: 3596847973 -1289000: 117168222 -1288000: 3531023849 -1287000: 3135920051 -1286000: 234987844 -1285000: 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4163248735 -35000: 943584186 -34000: 387069186 -33000: 3519377243 -32000: 3861206003 -31000: 2378381393 -30000: 3259365221 -29000: 3960625204 -28000: 3476394666 -27000: 1995310421 -26000: 1884341166 -25000: 3181801013 -24000: 116492838 -23000: 3276567587 -22000: 3693343729 -21000: 2595820568 -20000: 2397879436 -19000: 2692679578 -18000: 2368648652 -17000: 3098196844 -16000: 3913788179 -15000: 1240694507 -14000: 1586030084 -13000: 1211450031 -12000: 3458253062 -11000: 1804606651 -10000: 2128587109 -9000: 1894810186 -8000: 2221431098 -7000: 113605713 -6000: 4020003580 -5000: 2988041351 -4000: 2310084217 -3000: 1475476779 -2000: 760651391 -1000: 4031656975 -0: 2206428413 -Exiting @ tick 2369901960000 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt deleted file mode 100644 index 117215dc5..000000000 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ /dev/null @@ -1,280 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.369902 # Number of seconds simulated -sim_ticks 2369901960000 # Number of ticks simulated -final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1407810 # Simulator instruction rate (inst/s) -host_tick_rate 1780114775 # Simulator tick rate (ticks/s) -host_mem_usage 224180 # Number of bytes of host memory used -host_seconds 1331.32 # Real time elapsed on the host -sim_insts 1874244950 # Number of instructions simulated -system.physmem.bytes_read 94696320 # Number of bytes read from this memory -system.physmem.bytes_inst_read 144448 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4230336 # Number of bytes written to this memory -system.physmem.num_reads 1479630 # Number of read requests responded to by this memory -system.physmem.num_writes 66099 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 39957906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 60951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1785026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 41742932 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits 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-system.cpu.dcache.demand_miss_latency 83520808000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 83520808000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 620335414 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 897271092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 897271092 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000263 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.001709 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.001709 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54458.738711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54458.738711 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107259 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1460873 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 72780 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1533653 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1533653 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 75343363000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 78919849000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 78919849000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1478755 # number of replacements -system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use -system.cpu.l2cache.total_refs 75453 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3041.423322 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.881757 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.092817 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 67139 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107259 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 6687 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 73826 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 73826 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1413537 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 66093 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 1479630 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 1479630 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 73503924000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3436836000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 76940760000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 76940760000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1480676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107259 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1553456 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1553456 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.954657 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.908120 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.952476 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.952476 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 66099 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1413537 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1479630 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1479630 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56541480000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2643720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 59185200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 59185200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954657 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908120 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.952476 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.952476 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- |