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-rw-r--r--tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini90
-rwxr-xr-xtests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr5
-rwxr-xr-xtests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout1393
-rw-r--r--tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt36
-rw-r--r--tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini190
-rwxr-xr-xtests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr5
-rwxr-xr-xtests/long/40.perlbmk/ref/arm/linux/simple-timing/simout1393
-rw-r--r--tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt233
8 files changed, 3345 insertions, 0 deletions
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..3428438b6
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,90 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..805a6606f
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,5 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: fcntl64(3, 2) passed through to host
+For more information see: http://www.m5sim.org/warn/a55e2c46
+hack: be nice to actually delete the event here
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..57190e92a
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,1393 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 25 2010 20:52:35
+M5 revision ffac9df60637 7512 default tip
+M5 started Jul 26 2010 23:53:56
+M5 executing on zizzer
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+Exiting @ tick 922809447000 because target called exit()
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..6f84a3553
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,36 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2704949 # Simulator instruction rate (inst/s)
+host_mem_usage 202656 # Number of bytes of host memory used
+host_seconds 680.13 # Real time elapsed on the host
+host_tick_rate 1356804201 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1839728999 # Number of instructions simulated
+sim_seconds 0.922809 # Number of seconds simulated
+sim_ticks 922809447000 # Number of ticks simulated
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 1845618895 # number of cpu cycles simulated
+system.cpu.num_insts 1839728999 # Number of instructions executed
+system.cpu.num_refs 908401146 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
new file mode 100644
index 000000000..406381ed3
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -0,0 +1,190 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr
new file mode 100755
index 000000000..805a6606f
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1,5 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: fcntl64(3, 2) passed through to host
+For more information see: http://www.m5sim.org/warn/a55e2c46
+hack: be nice to actually delete the event here
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
new file mode 100755
index 000000000..55aff9333
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -0,0 +1,1393 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 25 2010 20:52:35
+M5 revision ffac9df60637 7512 default tip
+M5 started Jul 26 2010 23:56:56
+M5 executing on zizzer
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+Exiting @ tick 2371369572000 because target called exit()
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..489e4d962
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -0,0 +1,233 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1313947 # Simulator instruction rate (inst/s)
+host_mem_usage 210340 # Number of bytes of host memory used
+host_seconds 1391.71 # Real time elapsed on the host
+host_tick_rate 1703921021 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1828637582 # Number of instructions simulated
+sim_seconds 2.371370 # Number of seconds simulated
+sim_ticks 2371369572000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 620364065 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 55313.788145 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52313.788145 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 618902904 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 80822350000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1461161 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 76438867000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1461161 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 276945663 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 55999.799022 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.799022 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 276871028 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 4179545000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 74635 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 3955640000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 74635 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 583.970170 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 897309728 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 55347.126181 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52347.126181 # average overall mshr miss latency
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+system.cpu.dcache.demand_miss_latency 85001895000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.001712 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1535796 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 80394507000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.001712 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1535796 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.999747 # Average percentage of cache occupancy
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+system.cpu.dcache.overall_avg_mshr_miss_latency 52347.126181 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 895773932 # number of overall hits
+system.cpu.dcache.overall_miss_latency 85001895000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.001712 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1535796 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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+system.cpu.dcache.overall_mshr_misses 1535796 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 1529845 # number of replacements
+system.cpu.dcache.sampled_refs 1533941 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4094.964018 # Cycle average of tags in use
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+system.cpu.dcache.warmup_cycle 995704000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 74508 # number of writebacks
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
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+system.cpu.icache.ReadReq_accesses 1390241555 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15784.729586 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1390221752 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 371994000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_mshr_miss_latency 312585000 # number of ReadReq MSHR miss cycles
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+system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses
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+system.cpu.icache.avg_refs 70202.583043 # Average number of references to valid blocks.
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+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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+system.cpu.icache.demand_accesses 1390241555 # number of demand (read+write) accesses
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+system.cpu.icache.demand_avg_mshr_miss_latency 15784.729586 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1390221752 # number of demand (read+write) hits
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+system.cpu.icache.demand_misses 19803 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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+system.cpu.icache.demand_mshr_misses 19803 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.679846 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1392.324951 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 1390241555 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 18784.729586 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15784.729586 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1390221752 # number of overall hits
+system.cpu.icache.overall_miss_latency 371994000 # number of overall miss cycles
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+system.cpu.icache.overall_misses 19803 # number of overall misses
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+system.cpu.icache.replacements 18364 # number of replacements
+system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1392.324951 # Cycle average of tags in use
+system.cpu.icache.total_refs 1390221752 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
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+system.cpu.itb.write_accesses 0 # DTB write accesses
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+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 72780 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2911200000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 72780 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 1480964 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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+system.cpu.l2cache.UpgradeReq_accesses 1855 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51579.514825 # average UpgradeReq miss latency
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+system.cpu.l2cache.demand_misses 1512324 # number of demand (read+write) misses
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+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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+system.cpu.l2cache.overall_mshr_miss_latency 60492960000 # number of overall MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_misses 1512324 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 1472870 # number of replacements
+system.cpu.l2cache.sampled_refs 1505525 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 31920.827295 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 48363 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 66101 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 4742739144 # number of cpu cycles simulated
+system.cpu.num_insts 1828637582 # Number of instructions executed
+system.cpu.num_refs 908401146 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls
+
+---------- End Simulation Statistics ----------
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 08:01:00 +0000