diff options
Diffstat (limited to 'tests/long/40.perlbmk')
3 files changed, 51 insertions, 52 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 7ccc4388b..155b89d4e 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -169,6 +169,7 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index 0c4f37988..b73b39051 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1159414 # Simulator instruction rate (inst/s) -host_mem_usage 206548 # Number of bytes of host memory used -host_seconds 1732.76 # Real time elapsed on the host -host_tick_rate 1597499589 # Simulator tick rate (ticks/s) +host_inst_rate 883544 # Simulator instruction rate (inst/s) +host_mem_usage 162840 # Number of bytes of host memory used +host_seconds 2273.78 # Real time elapsed on the host +host_tick_rate 1217345227 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated -sim_seconds 2.768086 # Number of seconds simulated -sim_ticks 2768085828000 # Number of ticks simulated +sim_seconds 2.767980 # Number of seconds simulated +sim_ticks 2767979952000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24898.959808 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22898.959808 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 24826.352085 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22826.352085 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36307464000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 36201588000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 33391080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 33285204000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 24903.889094 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22903.889094 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 24834.823569 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22834.823569 # average overall mshr miss latency system.cpu.dcache.demand_hits 720331943 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 38177139000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 38071263000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002124 # miss rate for demand accesses system.cpu.dcache.demand_misses 1532979 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 35111181000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 35005305000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002124 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1532979 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 24903.889094 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22903.889094 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 24834.823569 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22834.823569 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 720331943 # number of overall hits -system.cpu.dcache.overall_miss_latency 38177139000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 38071263000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002124 # miss rate for overall accesses system.cpu.dcache.overall_misses 1532979 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 35111181000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 35005305000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002124 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.361643 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.361619 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 795905000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 74589 # number of writebacks @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 9046 # number of replacements system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1478.559335 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.559454 # Cycle average of tags in use system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -171,13 +171,13 @@ system.cpu.l2cache.ReadExReq_mshr_misses 71952 # nu system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 20497 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 31862402000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.986045 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1448291 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15931201000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.986045 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1448291 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 29320 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 31668296000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.980038 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1439468 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 15834148000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980038 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1439468 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 2835 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 21821.516755 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -188,13 +188,10 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31185000 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 2835 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 74589 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 74589 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.015643 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.023744 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -203,14 +200,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 20497 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 33445346000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.986697 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1520243 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 29320 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 33251240000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.980970 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1511420 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 16722673000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.986697 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1520243 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 16625620000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.980970 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1511420 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -218,14 +215,14 @@ system.cpu.l2cache.overall_accesses 1540740 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 20497 # number of overall hits -system.cpu.l2cache.overall_miss_latency 33445346000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.986697 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1520243 # number of overall misses +system.cpu.l2cache.overall_hits 29320 # number of overall hits +system.cpu.l2cache.overall_miss_latency 33251240000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1511420 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 16722673000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.986697 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1520243 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 16625620000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1511420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -237,15 +234,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 1412930 # number of replacements -system.cpu.l2cache.sampled_refs 1445479 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1473608 # number of replacements +system.cpu.l2cache.sampled_refs 1506166 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31165.186472 # Cycle average of tags in use -system.cpu.l2cache.total_refs 22612 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 31924.676313 # Cycle average of tags in use +system.cpu.l2cache.total_refs 35763 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.writebacks 66899 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5536171656 # number of cpu cycles simulated +system.cpu.numCycles 5535959904 # number of cpu cycles simulated system.cpu.num_insts 2008987605 # Number of instructions executed system.cpu.num_refs 722823898 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr index a6133a5ee..aa60d7c13 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,4 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 0, ...) |