diff options
Diffstat (limited to 'tests/long/40.perlbmk')
20 files changed, 430 insertions, 360 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 7c1b2f7e5..c87170fbe 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ type=System children=cpu membus physmem mem_mode=atomic memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -18,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU @@ -477,7 +479,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -519,7 +521,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -529,5 +531,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index ec96cb05b..2a099e16b 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 16:10:02 -gem5 started Aug 20 2011 21:33:28 +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 05:26:04 gem5 executing on zizzer -command line: ./build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index c68641234..90210da82 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -2,12 +2,23 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.643030 # Number of seconds simulated sim_ticks 643030478500 # Number of ticks simulated +final_tick 643030478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153773 # Simulator instruction rate (inst/s) -host_tick_rate 54239400 # Simulator tick rate (ticks/s) -host_mem_usage 218648 # Number of bytes of host memory used -host_seconds 11855.41 # Real time elapsed on the host +host_inst_rate 153915 # Simulator instruction rate (inst/s) +host_tick_rate 54289503 # Simulator tick rate (ticks/s) +host_mem_usage 215008 # Number of bytes of host memory used +host_seconds 11844.47 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated +system.physmem.bytes_read 94779264 # Number of bytes read from this memory +system.physmem.bytes_inst_read 185664 # Number of instructions bytes read from this memory +system.physmem.bytes_written 4281472 # Number of bytes written to this memory +system.physmem.num_reads 1480926 # Number of read requests responded to by this memory +system.physmem.num_writes 66898 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 147394668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 288733 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 6658272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 154052940 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index f80631f28..a895468a4 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -17,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU @@ -44,8 +47,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[2] -icache_port=system.membus.port[1] +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] [system.cpu.dtb] type=AlphaTLB @@ -61,7 +64,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic +cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic egid=100 env= errout=cerr @@ -85,7 +88,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory @@ -95,5 +98,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index c5f9e3fdc..67c7a90bd 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 20 2011 12:33:29 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 05:26:36 +gem5 executing on zizzer +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index b6ea3474a..5a9e50b92 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -2,12 +2,23 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.004711 # Number of seconds simulated sim_ticks 1004710587000 # Number of ticks simulated +final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3394241 # Simulator instruction rate (inst/s) -host_tick_rate 1697486503 # Simulator tick rate (ticks/s) -host_mem_usage 190248 # Number of bytes of host memory used -host_seconds 591.88 # Real time elapsed on the host +host_inst_rate 4051601 # Simulator instruction rate (inst/s) +host_tick_rate 2026237516 # Simulator tick rate (ticks/s) +host_mem_usage 204820 # Number of bytes of host memory used +host_seconds 495.85 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated +system.physmem.bytes_read 11607100996 # Number of bytes read from this memory +system.physmem.bytes_inst_read 8037684280 # Number of instructions bytes read from this memory +system.physmem.bytes_written 1586125963 # Number of bytes written to this memory +system.physmem.num_reads 2520491096 # Number of read requests responded to by this memory +system.physmem.num_writes 210794896 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 11552681087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 7999999586 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 1578689409 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 13131370496 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index d0df4a5be..f60b78837 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -17,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU @@ -146,7 +149,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -164,7 +167,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing +cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing egid=100 env= errout=cerr @@ -188,7 +191,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -198,5 +201,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout index 8bb74946d..e767ec1c4 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 20 2011 13:15:24 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 05:28:03 +gem5 executing on zizzer +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index eed39f9d4..668a6f1dd 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -2,12 +2,23 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.813468 # Number of seconds simulated sim_ticks 2813467842000 # Number of ticks simulated +final_tick 2813467842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1436300 # Simulator instruction rate (inst/s) -host_tick_rate 2011453251 # Simulator tick rate (ticks/s) -host_mem_usage 198964 # Number of bytes of host memory used -host_seconds 1398.72 # Real time elapsed on the host +host_inst_rate 1954286 # Simulator instruction rate (inst/s) +host_tick_rate 2736861040 # Simulator tick rate (ticks/s) +host_mem_usage 213480 # Number of bytes of host memory used +host_seconds 1027.99 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated +system.physmem.bytes_read 94708160 # Number of bytes read from this memory +system.physmem.bytes_inst_read 152128 # Number of instructions bytes read from this memory +system.physmem.bytes_written 4281472 # Number of bytes written to this memory +system.physmem.num_reads 1479815 # Number of read requests responded to by this memory +system.physmem.num_writes 66898 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 33662428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 54071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 1521777 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 35184206 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini index eaf32daa6..7e5e4838d 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ type=System children=cpu membus physmem mem_mode=atomic memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -18,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU @@ -477,7 +479,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -500,7 +502,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -519,7 +521,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -529,5 +531,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout index fc03e6958..af8b043ac 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 21 2011 16:28:02 -gem5 started Nov 22 2011 18:31:45 -gem5 executing on u200540-lin +gem5 compiled Jan 23 2012 04:16:21 +gem5 started Jan 23 2012 09:08:55 +gem5 executing on zizzer command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index e47b3cac2..7b72f7ce4 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -2,12 +2,23 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.708403 # Number of seconds simulated sim_ticks 708403313500 # Number of ticks simulated +final_tick 708403313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129621 # Simulator instruction rate (inst/s) -host_tick_rate 48704258 # Simulator tick rate (ticks/s) -host_mem_usage 220728 # Number of bytes of host memory used -host_seconds 14545.00 # Real time elapsed on the host +host_inst_rate 118434 # Simulator instruction rate (inst/s) +host_tick_rate 44501063 # Simulator tick rate (ticks/s) +host_mem_usage 226576 # Number of bytes of host memory used +host_seconds 15918.80 # Real time elapsed on the host sim_insts 1885333786 # Number of instructions simulated +system.physmem.bytes_read 94812032 # Number of bytes read from this memory +system.physmem.bytes_inst_read 200960 # Number of instructions bytes read from this memory +system.physmem.bytes_written 4230336 # Number of bytes written to this memory +system.physmem.num_reads 1481438 # Number of read requests responded to by this memory +system.physmem.num_writes 66099 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 133839058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 283680 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5971649 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 139810707 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 97cb6c6e4..6a275dc9a 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -17,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU @@ -44,8 +47,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[2] -icache_port=system.membus.port[1] +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB @@ -61,7 +64,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic egid=100 env= errout=cerr @@ -85,7 +88,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory @@ -95,5 +98,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr index 805a6606f..cba73e085 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr @@ -1,5 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: fcntl64(3, 2) passed through to host -For more information see: http://www.m5sim.org/warn/a55e2c46 hack: be nice to actually delete the event here diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout index 343cd2a25..dd29e750e 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 13:03:45 -M5 executing on maize -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic +gem5 compiled Jan 23 2012 04:16:21 +gem5 started Jan 23 2012 09:17:45 +gem5 executing on zizzer +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 9d864db40..49ae2817e 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,76 +1,87 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1799997 # Simulator instruction rate (inst/s) -host_mem_usage 258316 # Number of bytes of host memory used -host_seconds 1047.41 # Real time elapsed on the host -host_tick_rate 902810159 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1885336367 # Number of instructions simulated sim_seconds 0.945613 # Number of seconds simulated sim_ticks 945613131000 # Number of ticks simulated -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses +final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 2997522 # Simulator instruction rate (inst/s) +host_tick_rate 1503443037 # Simulator tick rate (ticks/s) +host_mem_usage 215364 # Number of bytes of host memory used +host_seconds 628.97 # Real time elapsed on the host +sim_insts 1885336367 # Number of instructions simulated +system.physmem.bytes_read 8025491315 # Number of bytes read from this memory +system.physmem.bytes_inst_read 5561086040 # Number of instructions bytes read from this memory +system.physmem.bytes_written 1123958396 # Number of bytes written to this memory +system.physmem.num_reads 2010616909 # Number of read requests responded to by this memory +system.physmem.num_writes 276945663 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 8487076852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 5880931491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 1188602780 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 9675679632 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 1411 # Number of system calls system.cpu.numCycles 1891226263 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 1891226263 # Number of busy cycles -system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read -system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_func_calls 80344203 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 1885336367 # Number of instructions executed system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses +system.cpu.num_func_calls 80344203 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls system.cpu.num_int_insts 1653698876 # number of integer instructions +system.cpu.num_fp_insts 52289415 # number of float instructions system.cpu.num_int_register_reads 8601515950 # number of times the integer registers were read system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written -system.cpu.num_load_insts 631387182 # Number of load instructions +system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read +system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written system.cpu.num_mem_refs 908382480 # number of memory refs +system.cpu.num_load_insts 631387182 # Number of load instructions system.cpu.num_store_insts 276995298 # Number of store instructions -system.cpu.workload.num_syscalls 1411 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1891226263 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini index f566d5f40..01aaafc03 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -17,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU @@ -146,7 +149,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -164,7 +167,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing egid=100 env= errout=cerr @@ -188,7 +191,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -198,5 +201,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr index 805a6606f..cba73e085 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr @@ -1,5 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: fcntl64(3, 2) passed through to host -For more information see: http://www.m5sim.org/warn/a55e2c46 hack: be nice to actually delete the event here diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout index 5a9581642..df0dd80b9 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 13:11:59 -M5 executing on maize -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing +gem5 compiled Jan 23 2012 04:16:21 +gem5 started Jan 23 2012 09:28:26 +gem5 executing on zizzer +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index fd9599dfa..117215dc5 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,269 +1,280 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 933614 # Simulator instruction rate (inst/s) -host_mem_usage 266072 # Number of bytes of host memory used -host_seconds 2007.52 # Real time elapsed on the host -host_tick_rate 1180515097 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1874244950 # Number of instructions simulated sim_seconds 2.369902 # Number of seconds simulated sim_ticks 2369901960000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 9985 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 620335414 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 618874541 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 79725982000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1460873 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 75343363000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1460873 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 9985 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 276862898 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3794826000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000263 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 72780 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 72780 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 897271092 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 54458.738711 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency -system.cpu.dcache.demand_hits 895737439 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 83520808000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.001709 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1533653 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 78919849000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1533653 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4094.960333 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999746 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 897271092 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 54458.738711 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 895737439 # number of overall hits -system.cpu.dcache.overall_miss_latency 83520808000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.001709 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1533653 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 78919849000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1533653 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1529557 # number of replacements -system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use -system.cpu.dcache.total_refs 895757409 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 997882000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 107259 # number of writebacks -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses +final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1407810 # Simulator instruction rate (inst/s) +host_tick_rate 1780114775 # Simulator tick rate (ticks/s) +host_mem_usage 224180 # Number of bytes of host memory used +host_seconds 1331.32 # Real time elapsed on the host +sim_insts 1874244950 # Number of instructions simulated +system.physmem.bytes_read 94696320 # Number of bytes read from this memory +system.physmem.bytes_inst_read 144448 # Number of instructions bytes read from this memory +system.physmem.bytes_written 4230336 # Number of bytes written to this memory +system.physmem.num_reads 1479630 # Number of read requests responded to by this memory +system.physmem.num_writes 66099 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 39957906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 60951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 1785026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 41742932 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 1390271511 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 18786.850477 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477 # average ReadReq mshr miss latency +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 1411 # Number of system calls +system.cpu.numCycles 4739803920 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 1874244950 # Number of instructions executed +system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses +system.cpu.num_func_calls 80344203 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls +system.cpu.num_int_insts 1653698876 # number of integer instructions +system.cpu.num_fp_insts 52289415 # number of float instructions +system.cpu.num_int_register_reads 10466679954 # number of times the integer registers were read +system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written +system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read +system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written +system.cpu.num_mem_refs 908382480 # number of memory refs +system.cpu.num_load_insts 631387182 # Number of load instructions +system.cpu.num_store_insts 276995298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 4739803920 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 18364 # number of replacements +system.cpu.icache.tagsinuse 1392.324437 # Cycle average of tags in use +system.cpu.icache.total_refs 1390251708 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1392.324437 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.679846 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits 1390251708 # number of ReadReq hits +system.cpu.icache.demand_hits 1390251708 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1390251708 # number of overall hits +system.cpu.icache.ReadReq_misses 19803 # number of ReadReq misses +system.cpu.icache.demand_misses 19803 # number of demand (read+write) misses +system.cpu.icache.overall_misses 19803 # number of overall misses system.cpu.icache.ReadReq_miss_latency 372036000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 372036000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 372036000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1390271511 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1390271511 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1390271511 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 19803 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 312627000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 18786.850477 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 18786.850477 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1390271511 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 18786.850477 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency -system.cpu.icache.demand_hits 1390251708 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 372036000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses -system.cpu.icache.demand_misses 19803 # number of demand (read+write) misses +system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 19803 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 19803 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 312627000 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 312627000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 312627000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 19803 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1392.324437 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.679846 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 1390271511 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency +system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1390251708 # number of overall hits -system.cpu.icache.overall_miss_latency 372036000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses -system.cpu.icache.overall_misses 19803 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 312627000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 19803 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 18364 # number of replacements -system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1392.324437 # Cycle average of tags in use -system.cpu.icache.total_refs 1390251708 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1529557 # number of replacements +system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use +system.cpu.dcache.total_refs 895757409 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 997882000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.960333 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999746 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 618874541 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 276862898 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 9985 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 9985 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 895737439 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 895737439 # number of overall hits +system.cpu.dcache.ReadReq_misses 1460873 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 72780 # number of WriteReq misses +system.cpu.dcache.demand_misses 1533653 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1533653 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 79725982000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3794826000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 83520808000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 83520808000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 620335414 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 9985 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 9985 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 897271092 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 897271092 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.000263 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.001709 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.001709 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 54458.738711 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 54458.738711 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 107259 # number of writebacks +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1460873 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 72780 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1533653 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1533653 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 75343363000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3576486000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 78919849000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 78919849000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.001709 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001709 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 1478755 # number of replacements +system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use +system.cpu.l2cache.total_refs 75453 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3041.423322 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.881757 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.092817 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 67139 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 107259 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 6687 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 3436836000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.908120 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 73826 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 73826 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1413537 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 66093 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2643720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908120 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1480676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 67139 # number of ReadReq hits +system.cpu.l2cache.demand_misses 1479630 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 1479630 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 73503924000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.954657 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1413537 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56541480000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954657 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1413537 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 3436836000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 76940760000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 76940760000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1480676 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 107259 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 107259 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1553456 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1553456 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.954657 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.908120 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.952476 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.952476 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1553456 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 73826 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 76940760000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.952476 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1479630 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 66099 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 1413537 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 66093 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 1479630 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 1479630 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 56541480000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2643720000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 59185200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 59185200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954657 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908120 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.952476 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1479630 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3041.423322 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.881757 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.092817 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 1553456 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.952476 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 73826 # number of overall hits -system.cpu.l2cache.overall_miss_latency 76940760000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.952476 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1479630 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 59185200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.952476 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1479630 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 1478755 # number of replacements -system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use -system.cpu.l2cache.total_refs 75453 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 66099 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4739803920 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 4739803920 # Number of busy cycles -system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read -system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_func_calls 80344203 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 1874244950 # Number of instructions executed -system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses -system.cpu.num_int_insts 1653698876 # number of integer instructions -system.cpu.num_int_register_reads 10466679954 # number of times the integer registers were read -system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written -system.cpu.num_load_insts 631387182 # Number of load instructions -system.cpu.num_mem_refs 908382480 # number of memory refs -system.cpu.num_store_insts 276995298 # Number of store instructions -system.cpu.workload.num_syscalls 1411 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |