diff options
Diffstat (limited to 'tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt')
-rw-r--r-- | tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 254fb17d5..d2ad10f5b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 254468 # Simulator instruction rate (inst/s) -host_mem_usage 199708 # Number of bytes of host memory used -host_seconds 312.78 # Real time elapsed on the host -host_tick_rate 86754409 # Simulator tick rate (ticks/s) +host_inst_rate 172212 # Simulator instruction rate (inst/s) +host_mem_usage 201796 # Number of bytes of host memory used +host_seconds 462.17 # Real time elapsed on the host +host_tick_rate 58711424 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.027135 # Number of seconds simulated @@ -95,6 +95,8 @@ system.cpu.dcache.demand_mshr_misses 211325 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.995440 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4077.324152 # Average occupied blocks per context system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency @@ -201,6 +203,8 @@ system.cpu.icache.demand_mshr_misses 85936 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.936032 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1916.994169 # Average occupied blocks per context system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency @@ -391,6 +395,10 @@ system.cpu.l2cache.demand_mshr_misses 188071 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.089962 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.474123 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2947.876007 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15536.049051 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency |