diff options
Diffstat (limited to 'tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt')
| -rw-r--r-- | tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt | 118 |
1 files changed, 59 insertions, 59 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 068d99b92..fcf32cd99 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 866615 # Simulator instruction rate (inst/s) -host_mem_usage 218536 # Number of bytes of host memory used -host_seconds 101.94 # Real time elapsed on the host -host_tick_rate 1271060462 # Simulator tick rate (ticks/s) +host_inst_rate 1478736 # Simulator instruction rate (inst/s) +host_mem_usage 210524 # Number of bytes of host memory used +host_seconds 59.74 # Real time elapsed on the host +host_tick_rate 2262580844 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.129569 # Number of seconds simulated -sim_ticks 129569130000 # Number of ticks simulated +sim_seconds 0.135169 # Number of seconds simulated +sim_ticks 135168711000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21389.665103 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18389.665103 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 37874.302641 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.302641 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1299743000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2301432000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1117448000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2119137000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.752992 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.752992 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4044374000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 8388371000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3594995000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 25380.735949 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22380.735949 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 50768.923527 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5344117000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10689803000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4712443000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10058129000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 25380.735949 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22380.735949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 50768.923527 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34679457 # number of overall hits -system.cpu.dcache.overall_miss_latency 5344117000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10689803000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses system.cpu.dcache.overall_misses 210558 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4712443000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10058129000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 200247 # number of replacements system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4080.797262 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.869222 # Cycle average of tags in use system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 750583000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 947580000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.dtb.accesses 34987415 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 14613377 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15489.023497 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12489.023497 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 18810.691297 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1183919000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1437814000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 954611000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 1208506000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15489.023497 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12489.023497 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 18810.691297 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1183919000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1437814000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 954611000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 1208506000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15489.023497 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12489.023497 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 88361638 # number of overall hits -system.cpu.icache.overall_miss_latency 1183919000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1437814000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 954611000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 1208506000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1876.637848 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.769418 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 88438074 # ITB hits system.cpu.itb.misses 3934 # ITB misses system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3302294000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 7466056000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1579358000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 995808000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 2251392000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.315566 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 43296 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 476256000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1731840000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315566 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 43296 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22863.073210 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 142094000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 321256000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 68365000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248600000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) @@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4298102000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 9717448000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.665555 # miss rate for demand accesses system.cpu.l2cache.demand_misses 186874 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2055614000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 7474960000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.665555 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 186874 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 280779 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 93905 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4298102000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 9717448000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.665555 # miss rate for overall accesses system.cpu.l2cache.overall_misses 186874 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2055614000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 7474960000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.665555 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 186874 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 147560 # number of replacements system.cpu.l2cache.sampled_refs 172765 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18265.835561 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18255.753819 # Cycle average of tags in use system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120634 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 259138260 # number of cpu cycles simulated +system.cpu.numCycles 270337422 # number of cpu cycles simulated system.cpu.num_insts 88340673 # Number of instructions executed system.cpu.num_refs 35321418 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls |