diff options
Diffstat (limited to 'tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index cc2716377..3f747beae 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2287584 # Simulator instruction rate (inst/s) -host_mem_usage 215192 # Number of bytes of host memory used -host_seconds 38.62 # Real time elapsed on the host -host_tick_rate 3500174868 # Simulator tick rate (ticks/s) +host_inst_rate 1182325 # Simulator instruction rate (inst/s) +host_mem_usage 200332 # Number of bytes of host memory used +host_seconds 74.72 # Real time elapsed on the host +host_tick_rate 1809050434 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.135169 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 210559 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.995818 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4078.872537 # Average occupied blocks per context system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency @@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses 76436 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.913950 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1871.768668 # Average occupied blocks per context system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency @@ -209,6 +213,10 @@ system.cpu.l2cache.demand_mshr_misses 186875 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.081795 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.475328 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2680.267907 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15575.557767 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency |