diff options
Diffstat (limited to 'tests/long/50.vortex/ref/alpha/tru64/simple-timing')
| -rw-r--r-- | tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt | 118 | ||||
| -rwxr-xr-x | tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout | 8 |
2 files changed, 63 insertions, 63 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 828a42be2..4078e993e 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,23 +1,23 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1704355 # Simulator instruction rate (inst/s) -host_mem_usage 211324 # Number of bytes of host memory used -host_seconds 51.83 # Real time elapsed on the host -host_tick_rate 2607795037 # Simulator tick rate (ticks/s) +host_inst_rate 1655989 # Simulator instruction rate (inst/s) +host_mem_usage 211348 # Number of bytes of host memory used +host_seconds 53.35 # Real time elapsed on the host +host_tick_rate 2533794438 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.135169 # Number of seconds simulated -sim_ticks 135168711000 # Number of ticks simulated +sim_ticks 135168766000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37874.302641 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.302641 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2301432000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2301488000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2119137000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2119190000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency @@ -30,38 +30,38 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # m system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 50768.923527 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency -system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10689803000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency +system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10689859000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses -system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10058129000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10058182000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 50768.923527 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 34679457 # number of overall hits -system.cpu.dcache.overall_miss_latency 10689803000 # number of overall miss cycles +system.cpu.dcache.overall_hits 34679456 # number of overall hits +system.cpu.dcache.overall_miss_latency 10689859000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses -system.cpu.dcache.overall_misses 210558 # number of overall misses +system.cpu.dcache.overall_misses 210559 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10058129000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10058182000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -73,12 +73,12 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200247 # number of replacements -system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200248 # number of replacements +system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.869222 # Cycle average of tags in use -system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 947580000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4078.872537 # Cycle average of tags in use +system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.dtb.accesses 34987415 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1871.769418 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.768668 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -168,16 +168,16 @@ system.cpu.l2cache.ReadExReq_misses 143578 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2251392000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.315566 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 43296 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1731840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315566 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 43296 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 2251444000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.315571 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 43297 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1731880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315571 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 43297 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency @@ -191,38 +191,38 @@ system.cpu.l2cache.Writeback_accesses 147714 # nu system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.630834 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.630830 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9717448000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.665555 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 186874 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 9717500000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.665557 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 186875 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 7474960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.665555 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 186874 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 7475000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.665557 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 186875 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 280779 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 93905 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9717448000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.665555 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 186874 # number of overall misses +system.cpu.l2cache.overall_miss_latency 9717500000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.665557 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 186875 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 7474960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.665555 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 186874 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 7475000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -234,15 +234,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 147560 # number of replacements -system.cpu.l2cache.sampled_refs 172765 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 147561 # number of replacements +system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18255.753819 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18255.825674 # Cycle average of tags in use system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120634 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 270337422 # number of cpu cycles simulated +system.cpu.numCycles 270337532 # number of cpu cycles simulated system.cpu.num_insts 88340673 # Number of instructions executed system.cpu.num_refs 35321418 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout index 8bed4881a..7c7d8426c 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 21:27:23 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:28:00 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second |