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-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini11
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout8
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt10
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini11
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt31
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini13
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr6
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout10
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt26
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini13
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr6
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/simple-timing/simout10
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt26
14 files changed, 145 insertions, 44 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index 83b3078ca..46d47f481 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=InOrderCPU
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
index 38b60786d..1ec8b66f1 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 24 2011 21:05:28
-M5 revision Unknown
-M5 started Jan 24 2011 21:53:14
-M5 executing on m55-002.pool
+M5 compiled Feb 7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb 7 2011 01:47:38
+M5 executing on burrito
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index 827d1ba1c..d26ecb349 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 68116 # Simulator instruction rate (inst/s)
-host_mem_usage 1627972 # Number of bytes of host memory used
-host_seconds 1296.92 # Real time elapsed on the host
-host_tick_rate 33685044 # Simulator tick rate (ticks/s)
+host_inst_rate 27953 # Simulator instruction rate (inst/s)
+host_mem_usage 1692040 # Number of bytes of host memory used
+host_seconds 3160.33 # Real time elapsed on the host
+host_tick_rate 13823537 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340674 # Number of instructions simulated
sim_seconds 0.043687 # Number of seconds simulated
@@ -272,6 +272,8 @@ system.cpu.l2cache.total_refs 134496 # To
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 120516 # number of writebacks
system.cpu.numCycles 87373938 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.runCycles 61786224 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index a73ef9125..669e84c5b 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=DerivO3CPU
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
index 2cca5705e..ea4e5025f 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 17 2011 16:24:53
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 16:25:07
-M5 executing on zizzer
+M5 compiled Feb 7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb 7 2011 01:47:37
+M5 executing on burrito
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 4f92cd575..553c740bc 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 227615 # Simulator instruction rate (inst/s)
-host_mem_usage 215572 # Number of bytes of host memory used
-host_seconds 349.68 # Real time elapsed on the host
-host_tick_rate 77104293 # Simulator tick rate (ticks/s)
+host_inst_rate 86589 # Simulator instruction rate (inst/s)
+host_mem_usage 236008 # Number of bytes of host memory used
+host_seconds 919.19 # Real time elapsed on the host
+host_tick_rate 29331748 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.026962 # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 51426557 # Number of insts commited each cycle
system.cpu.commit.COM:count 88340672 # Number of instructions committed
+system.cpu.commit.COM:fp_insts 267754 # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls 1661057 # Number of function calls committed.
+system.cpu.commit.COM:int_insts 77942044 # Number of committed integer instructions.
system.cpu.commit.COM:loads 20276638 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 34890015 # Number of memory references committed
@@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 52727427 # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads 245061 # number of floating regfile reads
+system.cpu.fp_regfile_writes 242344 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 13394904 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 9553.478677 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6055.148214 # average ReadReq mshr miss latency
@@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 1499472 #
system.cpu.iew.memOrderViolationEvents 20765 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 133024 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 270323 # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads 112261025 # number of integer regfile reads
+system.cpu.int_regfile_writes 55957664 # number of integer regfile writes
system.cpu.ipc 1.476021 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.476021 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
@@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 52727427 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.584713 # Inst issue rate
+system.cpu.iq.fp_alu_accesses 300330 # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads 600062 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses 291336 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes 449677 # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses 86057957 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 223986187 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses 84142849 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes 99078725 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 89657627 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 85452764 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 5005 # Number of non-speculative instructions added to the IQ
@@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 12487229 # Nu
system.cpu.memDep0.conflictingStores 11176863 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 22901502 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 16112849 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 38001 # number of misc regfile reads
+system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.numCycles 53923173 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 1782763 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 52474 # Number of times rename has blocked due to IQ full
@@ -471,10 +490,14 @@ system.cpu.rename.RENAME:RunCycles 19225803 # Nu
system.cpu.rename.RENAME:SquashCycles 1300870 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 1439133 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 8237313 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups 444545 # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups 121310909 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 77780 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 5276 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 3015491 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 5274 # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads 143406999 # The number of ROB reads
+system.cpu.rob.rob_writes 194680217 # The number of ROB writes
system.cpu.timesIdled 39379 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index e19472c60..d98970549 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr
index 67f69f09d..79a2396a6 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr
@@ -1,5 +1,11 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
index 9be789dc3..47e63ab68 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov 2 2010 21:44:15
-M5 executing on aus-bc2-b15
+M5 compiled Feb 7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb 7 2011 01:47:38
+M5 executing on burrito
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index 65fd7857e..1ad0b8bf6 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 5477905 # Simulator instruction rate (inst/s)
-host_mem_usage 240580 # Number of bytes of host memory used
-host_seconds 16.13 # Real time elapsed on the host
-host_tick_rate 2742055845 # Simulator tick rate (ticks/s)
+host_inst_rate 1614429 # Simulator instruction rate (inst/s)
+host_mem_usage 226740 # Number of bytes of host memory used
+host_seconds 54.72 # Real time elapsed on the host
+host_tick_rate 808136192 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.044221 # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 88442007 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 88442007 # Number of busy cycles
+system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
+system.cpu.num_fp_insts 267757 # number of float instructions
+system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
+system.cpu.num_func_calls 3321606 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 88340673 # Number of instructions executed
-system.cpu.num_refs 34987415 # Number of memory references
+system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
+system.cpu.num_int_insts 78039444 # number of integer instructions
+system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
+system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
+system.cpu.num_load_insts 20366786 # Number of load instructions
+system.cpu.num_mem_refs 34987415 # number of memory refs
+system.cpu.num_store_insts 14620629 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 0830e222d..6f171a7fa 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -157,7 +166,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
index 67f69f09d..79a2396a6 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
@@ -1,5 +1,11 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
index 121823232..4f3f97870 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov 2 2010 21:40:34
-M5 executing on aus-bc2-b15
+M5 compiled Feb 7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb 7 2011 01:47:37
+M5 executing on burrito
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 291724593..4a3fdb24c 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2249900 # Simulator instruction rate (inst/s)
-host_mem_usage 248308 # Number of bytes of host memory used
-host_seconds 39.26 # Real time elapsed on the host
-host_tick_rate 3419804648 # Simulator tick rate (ticks/s)
+host_inst_rate 599191 # Simulator instruction rate (inst/s)
+host_mem_usage 234452 # Number of bytes of host memory used
+host_seconds 147.43 # Real time elapsed on the host
+host_tick_rate 910763031 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.134277 # Number of seconds simulated
@@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 120506 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 268553976 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 268553976 # Number of busy cycles
+system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
+system.cpu.num_fp_insts 267757 # number of float instructions
+system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
+system.cpu.num_func_calls 3321606 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 88340673 # Number of instructions executed
-system.cpu.num_refs 34987415 # Number of memory references
+system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
+system.cpu.num_int_insts 78039444 # number of integer instructions
+system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
+system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
+system.cpu.num_load_insts 20366786 # Number of load instructions
+system.cpu.num_mem_refs 34987415 # number of memory refs
+system.cpu.num_store_insts 14620629 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------