diff options
Diffstat (limited to 'tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt | 816 |
1 files changed, 409 insertions, 407 deletions
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index 95c5d6049..67af91500 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.036358 # Number of seconds simulated -sim_ticks 36358325000 # Number of ticks simulated +sim_seconds 0.031378 # Number of seconds simulated +sim_ticks 31377609500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119827 # Simulator instruction rate (inst/s) -host_tick_rate 43292688 # Simulator tick rate (ticks/s) -host_mem_usage 272264 # Number of bytes of host memory used -host_seconds 839.83 # Real time elapsed on the host -sim_insts 100633775 # Number of instructions simulated +host_inst_rate 86505 # Simulator instruction rate (inst/s) +host_tick_rate 26972311 # Simulator tick rate (ticks/s) +host_mem_usage 272452 # Number of bytes of host memory used +host_seconds 1163.33 # Real time elapsed on the host +sim_insts 100633440 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,300 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 72716651 # number of cpu cycles simulated +system.cpu.numCycles 62755220 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 18013375 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11772112 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 832376 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15327252 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 9900840 # Number of BTB hits +system.cpu.BPredUnit.lookups 17750529 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11606544 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 829921 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15137991 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 9794974 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1964037 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 178584 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 13247418 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90436613 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18013375 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11864877 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 23481643 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3251985 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 32424598 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1373 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12458457 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 221175 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 71500308 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.766045 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.955660 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1897089 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 178911 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 13034693 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 89118710 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17750529 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11692063 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 23121914 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2980918 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 23222293 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1054 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12266935 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 235956 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 61445707 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.021826 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.078498 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 48035418 67.18% 67.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2508903 3.51% 70.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2594650 3.63% 74.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2541855 3.56% 77.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1760239 2.46% 80.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1724167 2.41% 82.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1024110 1.43% 84.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1345153 1.88% 86.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9965813 13.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 38339721 62.40% 62.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2446048 3.98% 66.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2617640 4.26% 70.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2484251 4.04% 74.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1726192 2.81% 77.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1710249 2.78% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1014832 1.65% 81.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1300729 2.12% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9806045 15.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 71500308 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.247720 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.243685 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15629487 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 30668783 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20991644 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1963924 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2246470 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3557308 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 100615 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123225405 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 322834 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2246470 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17904325 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3174295 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20084450 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20590055 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7500713 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 119940984 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 135288 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5895117 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 346 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 121539560 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 551911893 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 551809859 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 102034 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99143709 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22395801 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 778680 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 778694 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 18433689 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30390382 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 23021081 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 18365996 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 16439244 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 114579507 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 778229 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107939670 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 154653 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14553196 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 40300795 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 77221 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 71500308 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.509639 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.632123 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 61445707 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.282853 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.420100 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14959115 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 21951327 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21472779 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1093721 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1968765 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3488107 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98503 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 121008055 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 332806 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1968765 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16904329 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2023707 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15518382 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20592468 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4438056 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 117725717 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3874 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3096804 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 422 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 119617057 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 541668803 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 541574389 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 94414 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99143173 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 20473879 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 769482 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 769728 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12274515 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29853222 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22441342 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2796873 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3745515 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112284917 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 766220 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107896322 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 310095 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12199571 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 30868237 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 65279 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 61445707 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.755962 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.898029 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25383976 35.50% 35.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17917807 25.06% 60.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 11054386 15.46% 76.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7575334 10.59% 86.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5467314 7.65% 94.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2200256 3.08% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1169231 1.64% 98.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 554865 0.78% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 177139 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 22301465 36.29% 36.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11812133 19.22% 55.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8597395 13.99% 69.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7417461 12.07% 81.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4807172 7.82% 89.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3508678 5.71% 95.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1667450 2.71% 97.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 811386 1.32% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 522567 0.85% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 71500308 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 61445707 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 116974 6.43% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1491133 81.95% 88.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 211505 11.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 87227 3.33% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1494399 56.99% 60.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1040416 39.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57828785 53.58% 53.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 87098 0.08% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 50 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 3 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28711971 26.60% 80.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21311756 19.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57176503 52.99% 52.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 87495 0.08% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 4 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29053069 26.93% 80.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21579219 20.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107939670 # Type of FU issued -system.cpu.iq.rate 1.484387 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1819612 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016858 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 289353682 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 129921210 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106049922 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 300 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 90 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109759169 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1061783 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107896322 # Type of FU issued +system.cpu.iq.rate 1.719320 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2622042 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024301 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 280170245 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125277700 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105616251 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 243 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 88 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110518239 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 125 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1858517 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3081882 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2255 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10977 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2463953 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2544801 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4085 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28033 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1884293 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 46 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 45 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 54 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2246470 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1025437 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 38382 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115436550 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 596020 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30390382 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 23021081 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 761032 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4943 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5670 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10977 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 689404 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 204972 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 894376 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106732644 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28388861 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1207019 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1968765 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 949271 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 28405 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 113127739 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 631806 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29853222 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22441342 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 749089 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 969 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1264 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28033 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 689722 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 200512 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 890234 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106504319 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28672397 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1392003 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 78814 # number of nop insts executed -system.cpu.iew.exec_refs 49502432 # number of memory reference insts executed -system.cpu.iew.exec_branches 14773493 # Number of branches executed -system.cpu.iew.exec_stores 21113571 # Number of stores executed -system.cpu.iew.exec_rate 1.467788 # Inst execution rate -system.cpu.iew.wb_sent 106273270 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106050012 # cumulative count of insts written-back -system.cpu.iew.wb_producers 55103842 # num instructions producing a value -system.cpu.iew.wb_consumers 106001150 # num instructions consuming a value +system.cpu.iew.exec_nop 76602 # number of nop insts executed +system.cpu.iew.exec_refs 49938031 # number of memory reference insts executed +system.cpu.iew.exec_branches 14639990 # Number of branches executed +system.cpu.iew.exec_stores 21265634 # Number of stores executed +system.cpu.iew.exec_rate 1.697139 # Inst execution rate +system.cpu.iew.wb_sent 105945343 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105616339 # cumulative count of insts written-back +system.cpu.iew.wb_producers 52584494 # num instructions producing a value +system.cpu.iew.wb_consumers 101353649 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.458401 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.519842 # average fanout of values written-back +system.cpu.iew.wb_rate 1.682989 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.518822 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 100639327 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 14717021 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 701008 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 796431 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 69253839 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.453195 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.128132 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 100638992 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 12404270 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 700941 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 795177 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 59476943 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.692067 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.421797 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 30742933 44.39% 44.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19764540 28.54% 72.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4768337 6.89% 79.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4180096 6.04% 85.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3349632 4.84% 90.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1422305 2.05% 92.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 712095 1.03% 93.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 496006 0.72% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3817895 5.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 26426974 44.43% 44.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14734590 24.77% 69.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4278530 7.19% 76.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3643335 6.13% 82.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2295146 3.86% 86.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1888116 3.17% 89.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 696870 1.17% 90.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 492103 0.83% 91.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5021279 8.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 69253839 # Number of insts commited each cycle -system.cpu.commit.count 100639327 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 59476943 # Number of insts commited each cycle +system.cpu.commit.count 100638992 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47865603 # Number of memory references committed -system.cpu.commit.loads 27308487 # Number of loads committed +system.cpu.commit.refs 47865469 # Number of memory references committed +system.cpu.commit.loads 27308420 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13670006 # Number of branches committed +system.cpu.commit.branches 13669939 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91478299 # Number of committed integer instructions. +system.cpu.commit.int_insts 91478031 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 3817895 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5021279 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 180766993 # The number of ROB reads -system.cpu.rob.rob_writes 232965550 # The number of ROB writes -system.cpu.timesIdled 61914 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1216343 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 100633775 # Number of Instructions Simulated -system.cpu.committedInsts_total 100633775 # Number of Instructions Simulated -system.cpu.cpi 0.722587 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.722587 # CPI: Total CPI of All Threads -system.cpu.ipc 1.383917 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.383917 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 512803523 # number of integer regfile reads -system.cpu.int_regfile_writes 104642569 # number of integer regfile writes -system.cpu.fp_regfile_reads 286 # number of floating regfile reads -system.cpu.fp_regfile_writes 254 # number of floating regfile writes -system.cpu.misc_regfile_reads 148108878 # number of misc regfile reads -system.cpu.misc_regfile_writes 34596 # number of misc regfile writes -system.cpu.icache.replacements 27541 # number of replacements -system.cpu.icache.tagsinuse 1822.972635 # Cycle average of tags in use -system.cpu.icache.total_refs 12427797 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 29578 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 420.170295 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 167473627 # The number of ROB reads +system.cpu.rob.rob_writes 228061528 # The number of ROB writes +system.cpu.timesIdled 61721 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1309513 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 100633440 # Number of Instructions Simulated +system.cpu.committedInsts_total 100633440 # Number of Instructions Simulated +system.cpu.cpi 0.623602 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.623602 # CPI: Total CPI of All Threads +system.cpu.ipc 1.603587 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.603587 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 512681755 # number of integer regfile reads +system.cpu.int_regfile_writes 104103098 # number of integer regfile writes +system.cpu.fp_regfile_reads 154 # number of floating regfile reads +system.cpu.fp_regfile_writes 120 # number of floating regfile writes +system.cpu.misc_regfile_reads 146929222 # number of misc regfile reads +system.cpu.misc_regfile_writes 34462 # number of misc regfile writes +system.cpu.icache.replacements 26055 # number of replacements +system.cpu.icache.tagsinuse 1807.169356 # Cycle average of tags in use +system.cpu.icache.total_refs 12237713 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 28088 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 435.691861 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1822.972635 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.890123 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 12427797 # number of ReadReq hits -system.cpu.icache.demand_hits 12427797 # number of demand (read+write) hits -system.cpu.icache.overall_hits 12427797 # number of overall hits -system.cpu.icache.ReadReq_misses 30660 # number of ReadReq misses -system.cpu.icache.demand_misses 30660 # number of demand (read+write) misses -system.cpu.icache.overall_misses 30660 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 366375500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 366375500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 366375500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 12458457 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 12458457 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 12458457 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.002461 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.002461 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.002461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 11949.624918 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 11949.624918 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 11949.624918 # average overall miss latency +system.cpu.icache.occ_blocks::0 1807.169356 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.882407 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 12237715 # number of ReadReq hits +system.cpu.icache.demand_hits 12237715 # number of demand (read+write) hits +system.cpu.icache.overall_hits 12237715 # number of overall hits +system.cpu.icache.ReadReq_misses 29220 # number of ReadReq misses +system.cpu.icache.demand_misses 29220 # number of demand (read+write) misses +system.cpu.icache.overall_misses 29220 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 359586000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 359586000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 359586000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 12266935 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 12266935 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 12266935 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.002382 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.002382 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.002382 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 12306.160164 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 12306.160164 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 12306.160164 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,143 +354,145 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1075 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1075 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1075 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 29585 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 29585 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 29585 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1104 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1104 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1104 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 28116 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 28116 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 28116 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 250083000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 250083000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 250083000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 247135000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 247135000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 247135000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.002375 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.002375 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.002375 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8453.033632 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8453.033632 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8453.033632 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.002292 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.002292 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.002292 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8789.834969 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8789.834969 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8789.834969 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157556 # number of replacements -system.cpu.dcache.tagsinuse 4075.680070 # Cycle average of tags in use -system.cpu.dcache.total_refs 45321004 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 161652 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 280.361542 # Average number of references to valid blocks. +system.cpu.dcache.replacements 157895 # number of replacements +system.cpu.dcache.tagsinuse 4072.454592 # Cycle average of tags in use +system.cpu.dcache.total_refs 44804358 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 161991 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 276.585477 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 307509000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4075.680070 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995039 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 26986530 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 18297810 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 19355 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 17297 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 45284340 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 45284340 # number of overall hits -system.cpu.dcache.ReadReq_misses 104939 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1552091 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 27 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1657030 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1657030 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2337604500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 51739462000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 386500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 54077066500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 54077066500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 27091469 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 4072.454592 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994252 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 26458104 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 18310282 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 18655 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 17230 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 44768386 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 44768386 # number of overall hits +system.cpu.dcache.ReadReq_misses 108049 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1539619 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 28 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1647668 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1647668 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2398708000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 52285313500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 392000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 54684021500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 54684021500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 26566153 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 19382 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 17297 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 46941370 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 46941370 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.003874 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.078191 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.001393 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.035300 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.035300 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 22275.841203 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33335.327632 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 14314.814815 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 32634.935095 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 32634.935095 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 18683 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 17230 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 46416054 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 46416054 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.004067 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.077563 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.001499 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.035498 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.035498 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 22200.186952 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33959.904041 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 14000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 33188.737962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33188.737962 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 166000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18444.444444 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19600 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 123342 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 50191 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1445181 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 27 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1495372 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1495372 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 54748 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 106910 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 161658 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 161658 # number of overall MSHR misses +system.cpu.dcache.writebacks 123449 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 52916 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1432732 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 28 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1485648 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1485648 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 55133 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 106887 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 162020 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 162020 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1029521500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3652232000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4681753500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4681753500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1036639500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3662530000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4699169500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4699169500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005386 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003444 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003444 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18804.732593 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34161.743523 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 28960.852541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 28960.852541 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002075 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.003491 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003491 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18802.522990 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34265.439202 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29003.638440 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29003.638440 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 114899 # number of replacements -system.cpu.l2cache.tagsinuse 18376.822812 # Cycle average of tags in use -system.cpu.l2cache.total_refs 73444 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 133749 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.549118 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 114951 # number of replacements +system.cpu.l2cache.tagsinuse 18297.678495 # Cycle average of tags in use +system.cpu.l2cache.total_refs 72351 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 133808 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.540708 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2396.199422 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15980.623390 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.073126 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487690 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 51683 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 123342 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 4309 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 55992 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 55992 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32640 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 102597 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 135237 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 135237 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1115857000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3525923000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4641780000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4641780000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 84323 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 123342 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 6 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 106906 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 191229 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 191229 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.387083 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.666667 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.959694 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.707199 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.707199 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34186.795343 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.726123 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34323.299097 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34323.299097 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 2366.019129 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15931.659366 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.072205 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.486196 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 50475 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 123449 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 9 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 4296 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 54771 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 54771 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32704 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 102598 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 135302 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 135302 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1119458500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 34000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3525951000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4645409500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4645409500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 83179 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 123449 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 106894 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 190073 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 190073 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.393176 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.678571 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.959811 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.711842 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.711842 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34230.017735 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 1789.473684 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.664068 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34333.635127 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34333.635127 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -499,32 +501,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 88453 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 81 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 81 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32559 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 102597 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 135156 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 135156 # number of overall MSHR misses +system.cpu.l2cache.writebacks 88458 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 87 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 87 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32617 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 102598 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 135215 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 135215 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1011231500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3200947000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 4212178500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 4212178500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1013752000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 589000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3197491000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4211243000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4211243000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.386122 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.666667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959694 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.706776 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.706776 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31058.432384 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.392130 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.678571 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959811 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.711385 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.711385 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.479505 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31199.226098 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.308976 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.308976 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31165.237139 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31144.791628 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31144.791628 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |