diff options
Diffstat (limited to 'tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt index 0bdccd82b..4142f5d9a 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 558313 # Simulator instruction rate (inst/s) -host_mem_usage 262448 # Number of bytes of host memory used -host_seconds 178.74 # Real time elapsed on the host -host_tick_rate 744762819 # Simulator tick rate (ticks/s) +host_inst_rate 2031292 # Simulator instruction rate (inst/s) +host_mem_usage 221580 # Number of bytes of host memory used +host_seconds 49.13 # Real time elapsed on the host +host_tick_rate 2709639216 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 99791663 # Number of instructions simulated sim_seconds 0.133117 # Number of seconds simulated @@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 159998 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995345 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4076.934010 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995345 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 46990235 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 47946.924337 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency @@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 18908 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.847746 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1736.182852 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.847746 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 78145078 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24211.233340 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency @@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 133917 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.066099 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.489066 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2165.921088 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 16025.699940 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.066099 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.489066 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 178906 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 73126599 # nu system.cpu.num_load_insts 27307109 # Number of load instructions system.cpu.num_mem_refs 47862848 # number of memory refs system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls +system.cpu.workload.num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- |